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First of all the DW uMCTL2 DDRC IP-core supports the individual IRQ lines for each standard event: ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection, Scrubber-Done signal, DFI Parity/CRC Error. It's possible that the platform engineers merge them up in the IRQ controller level. So let's add both configuration support to the DT-schema. Secondly the DW uMCTL2 DDRC IP-core can have clock sources like APB reference clock, AXI-ports clock, main DDRC core reference clock and Scrubber low-power clock. In addition to that each clock domain can have a dedicated reset signal. Let's add the properties for at least the denoted clock sources and the corresponding reset controls. Note the IRQs and the phandles order is deliberately not fixed since some of the sources may be absent depending on the IP-core synthesize parameters and the particular platform setups. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220910195659.11843-3-Sergey.Semin@baikalelectronics.ru
119 lines
3.3 KiB
YAML
119 lines
3.3 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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- Manish Narani <manish.narani@xilinx.com>
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- Michal Simek <michal.simek@xilinx.com>
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description: |
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Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
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working with the memory devices supporting up to (LP)DDR4 protocol. It can
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be equipped with SEC/DEC ECC feature if DRAM data bus width is either
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16-bits or 32-bits or 64-bits wide.
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For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a
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controller. It has an optional SEC/DEC ECC support in 64- and 32-bits
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bus width configurations.
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properties:
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compatible:
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oneOf:
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- deprecated: true
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description: Synopsys DW uMCTL2 DDR controller v3.80a
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const: snps,ddrc-3.80a
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- description: Synopsys DW uMCTL2 DDR controller
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const: snps,dw-umctl2-ddrc
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- description: Xilinx ZynqMP DDR controller v2.40a
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const: xlnx,zynqmp-ddrc-2.40a
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interrupts:
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description:
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DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"
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ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection,
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Scrubber-Done signal, DFI Parity/CRC Error. Some platforms may have the
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signals merged before they reach the IRQ controller or have some of them
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absent in case if the corresponding feature is unavailable/disabled.
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minItems: 1
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maxItems: 5
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interrupt-names:
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minItems: 1
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maxItems: 5
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oneOf:
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- description: Common ECC CE/UE/Scrubber/DFI Errors IRQ
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items:
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- const: ecc
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- description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs
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items:
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enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ]
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reg:
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maxItems: 1
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clocks:
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description:
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A standard set of the clock sources contains CSRs bus clock, AXI-ports
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reference clock, DDRC core clock, Scrubber standalone clock
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(synchronous to the DDRC clock).
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minItems: 1
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maxItems: 4
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clock-names:
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minItems: 1
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maxItems: 4
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items:
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enum: [ pclk, aclk, core, sbr ]
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resets:
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description:
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Each clock domain can have separate reset signal.
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minItems: 1
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maxItems: 4
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reset-names:
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minItems: 1
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maxItems: 4
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items:
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enum: [ prst, arst, core, sbr ]
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required:
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- compatible
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- reg
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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memory-controller@fd070000 {
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compatible = "xlnx,zynqmp-ddrc-2.40a";
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reg = <0xfd070000 0x30000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ecc";
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};
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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memory-controller@3d400000 {
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compatible = "snps,dw-umctl2-ddrc";
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reg = <0x3d400000 0x400000>;
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interrupts = <147 IRQ_TYPE_LEVEL_HIGH>, <148 IRQ_TYPE_LEVEL_HIGH>,
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<149 IRQ_TYPE_LEVEL_HIGH>, <150 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ecc_ce", "ecc_ue", "ecc_sbr", "dfi_e";
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clocks = <&pclk>, <&aclk>, <&core_clk>, <&sbr_clk>;
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clock-names = "pclk", "aclk", "core", "sbr";
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};
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...
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