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LoongArch CPUINTC stands for CSR.ECFG/CSR.ESTAT and related interrupt controller that described in Section 7.4 of "LoongArch Reference Manual, Vol 1". For more information please refer Documentation/loongarch/irq- chip-model.rst. LoongArch CPUINTC has 13 interrupt sources: SWI0~1, HWI0~7, IPI, TI (Timer) and PCOV (PMC). IRQ mappings of HWI0~7 are configurable (can be created from DT/ACPI), but IPI, TI (Timer) and PCOV (PMC) are hardcoded bits, so we expose the fwnode_handle to map them, and get mapped irq by irq_create_mapping when using them. Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1658314292-35346-13-git-send-email-lvjianmin@loongson.cn
138 lines
3.2 KiB
C
138 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#include <linux/kernel.h>
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#include <linux/acpi.h>
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#include <linux/atomic.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip.h>
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#include <linux/kernel_stat.h>
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#include <linux/proc_fs.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/seq_file.h>
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#include <linux/kallsyms.h>
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#include <linux/uaccess.h>
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#include <asm/irq.h>
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#include <asm/loongson.h>
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#include <asm/setup.h>
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DEFINE_PER_CPU(unsigned long, irq_stack);
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DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
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EXPORT_PER_CPU_SYMBOL(irq_stat);
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struct acpi_vector_group pch_group[MAX_IO_PICS];
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struct acpi_vector_group msi_group[MAX_IO_PICS];
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/*
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* 'what should we do if we get a hw irq event on an illegal vector'.
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* each architecture has to answer this themselves.
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*/
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void ack_bad_irq(unsigned int irq)
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{
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pr_warn("Unexpected IRQ # %d\n", irq);
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}
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atomic_t irq_err_count;
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asmlinkage void spurious_interrupt(void)
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{
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atomic_inc(&irq_err_count);
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}
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int arch_show_interrupts(struct seq_file *p, int prec)
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{
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#ifdef CONFIG_SMP
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show_ipi_list(p, prec);
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#endif
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seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
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return 0;
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}
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static int __init early_pci_mcfg_parse(struct acpi_table_header *header)
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{
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struct acpi_table_mcfg *mcfg;
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struct acpi_mcfg_allocation *mptr;
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int i, n;
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if (header->length < sizeof(struct acpi_table_mcfg))
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return -EINVAL;
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n = (header->length - sizeof(struct acpi_table_mcfg)) /
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sizeof(struct acpi_mcfg_allocation);
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mcfg = (struct acpi_table_mcfg *)header;
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mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
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for (i = 0; i < n; i++, mptr++) {
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msi_group[i].pci_segment = mptr->pci_segment;
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pch_group[i].node = msi_group[i].node = (mptr->address >> 44) & 0xf;
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}
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return 0;
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}
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static void __init init_vec_parent_group(void)
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{
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int i;
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for (i = 0; i < MAX_IO_PICS; i++) {
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msi_group[i].pci_segment = -1;
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msi_group[i].node = -1;
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pch_group[i].node = -1;
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}
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acpi_table_parse(ACPI_SIG_MCFG, early_pci_mcfg_parse);
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}
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static int __init get_ipi_irq(void)
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{
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struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
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if (d)
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return irq_create_mapping(d, EXCCODE_IPI - EXCCODE_INT_START);
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return -EINVAL;
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}
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void __init init_IRQ(void)
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{
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int i;
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#ifdef CONFIG_SMP
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int r, ipi_irq;
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static int ipi_dummy_dev;
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#endif
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unsigned int order = get_order(IRQ_STACK_SIZE);
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struct page *page;
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clear_csr_ecfg(ECFG0_IM);
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clear_csr_estat(ESTATF_IP);
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init_vec_parent_group();
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irqchip_init();
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#ifdef CONFIG_SMP
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ipi_irq = get_ipi_irq();
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if (ipi_irq < 0)
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panic("IPI IRQ mapping failed\n");
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irq_set_percpu_devid(ipi_irq);
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r = request_percpu_irq(ipi_irq, loongson3_ipi_interrupt, "IPI", &ipi_dummy_dev);
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if (r < 0)
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panic("IPI IRQ request failed\n");
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#endif
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for (i = 0; i < NR_IRQS; i++)
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irq_set_noprobe(i);
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for_each_possible_cpu(i) {
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page = alloc_pages_node(cpu_to_node(i), GFP_KERNEL, order);
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per_cpu(irq_stack, i) = (unsigned long)page_address(page);
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pr_debug("CPU%d IRQ stack at 0x%lx - 0x%lx\n", i,
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per_cpu(irq_stack, i), per_cpu(irq_stack, i) + IRQ_STACK_SIZE);
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}
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set_csr_ecfg(ECFGF_IP0 | ECFGF_IP1 | ECFGF_IP2 | ECFGF_IPI | ECFGF_PMC);
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}
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