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7760989e5e
Due to limitation of the count-compare system timer (not able to count when CPU is in sleep), the system timer had to be changed to use a peripheral timer/counter. The old COUNT-COMPARE code is still present in time.c as weak functions. The new timer is added to the architecture directory. This patch sets up TC0 as system timer The new timer has been tested on AT32AP7000/ATSTK1000 at 100 Hz, 250 Hz, 300 Hz and 1000 Hz. For more details about the timer/counter see the datasheet for AT32AP700x available at http://www.atmel.com/dyn/products/product_card.asp?part_id=3903 Signed-off-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com> Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
234 lines
4.9 KiB
C
234 lines
4.9 KiB
C
/*
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* Copyright (C) 2004-2007 Atmel Corporation
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*
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* Based on MIPS implementation arch/mips/kernel/time.c
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* Copyright 2001 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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#include <linux/time.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel_stat.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/profile.h>
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#include <linux/sysdev.h>
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#include <linux/err.h>
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#include <asm/div64.h>
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#include <asm/sysreg.h>
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#include <asm/io.h>
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#include <asm/sections.h>
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/* how many counter cycles in a jiffy? */
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static u32 cycles_per_jiffy;
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/* the count value for the next timer interrupt */
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static u32 expirelo;
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cycle_t __weak read_cycle_count(void)
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{
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return (cycle_t)sysreg_read(COUNT);
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}
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struct clocksource __weak clocksource_avr32 = {
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.name = "avr32",
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.rating = 350,
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.read = read_cycle_count,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 16,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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irqreturn_t __weak timer_interrupt(int irq, void *dev_id);
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struct irqaction timer_irqaction = {
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.handler = timer_interrupt,
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.flags = IRQF_DISABLED,
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.name = "timer",
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};
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/*
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* By default we provide the null RTC ops
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*/
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static unsigned long null_rtc_get_time(void)
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{
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return mktime(2007, 1, 1, 0, 0, 0);
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}
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static int null_rtc_set_time(unsigned long sec)
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{
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return 0;
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}
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static unsigned long (*rtc_get_time)(void) = null_rtc_get_time;
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static int (*rtc_set_time)(unsigned long) = null_rtc_set_time;
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static void avr32_timer_ack(void)
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{
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u32 count;
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/* Ack this timer interrupt and set the next one */
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expirelo += cycles_per_jiffy;
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/* setting COMPARE to 0 stops the COUNT-COMPARE */
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if (expirelo == 0) {
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sysreg_write(COMPARE, expirelo + 1);
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} else {
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sysreg_write(COMPARE, expirelo);
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}
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/* Check to see if we have missed any timer interrupts */
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count = sysreg_read(COUNT);
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if ((count - expirelo) < 0x7fffffff) {
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expirelo = count + cycles_per_jiffy;
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sysreg_write(COMPARE, expirelo);
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}
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}
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int __weak avr32_hpt_init(void)
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{
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int ret;
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unsigned long mult, shift, count_hz;
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count_hz = clk_get_rate(boot_cpu_data.clk);
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shift = clocksource_avr32.shift;
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mult = clocksource_hz2mult(count_hz, shift);
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clocksource_avr32.mult = mult;
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{
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u64 tmp;
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tmp = TICK_NSEC;
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tmp <<= shift;
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tmp += mult / 2;
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do_div(tmp, mult);
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cycles_per_jiffy = tmp;
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}
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ret = setup_irq(0, &timer_irqaction);
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if (ret) {
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pr_debug("timer: could not request IRQ 0: %d\n", ret);
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return -ENODEV;
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}
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printk(KERN_INFO "timer: AT32AP COUNT-COMPARE at irq 0, "
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"%lu.%03lu MHz\n",
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((count_hz + 500) / 1000) / 1000,
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((count_hz + 500) / 1000) % 1000);
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return 0;
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}
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/*
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* Taken from MIPS c0_hpt_timer_init().
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*
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* The reason COUNT is written twice is probably to make sure we don't get any
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* timer interrupts while we are messing with the counter.
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*/
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int __weak avr32_hpt_start(void)
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{
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u32 count = sysreg_read(COUNT);
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expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
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sysreg_write(COUNT, expirelo - cycles_per_jiffy);
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sysreg_write(COMPARE, expirelo);
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sysreg_write(COUNT, count);
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return 0;
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}
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/*
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* local_timer_interrupt() does profiling and process accounting on a
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* per-CPU basis.
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*
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* In UP mode, it is invoked from the (global) timer_interrupt.
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*/
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void local_timer_interrupt(int irq, void *dev_id)
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{
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if (current->pid)
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profile_tick(CPU_PROFILING);
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update_process_times(user_mode(get_irq_regs()));
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}
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irqreturn_t __weak timer_interrupt(int irq, void *dev_id)
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{
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/* ack timer interrupt and try to set next interrupt */
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avr32_timer_ack();
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/*
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* Call the generic timer interrupt handler
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*/
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write_seqlock(&xtime_lock);
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do_timer(1);
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write_sequnlock(&xtime_lock);
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/*
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* In UP mode, we call local_timer_interrupt() to do profiling
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* and process accounting.
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*
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* SMP is not supported yet.
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*/
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local_timer_interrupt(irq, dev_id);
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return IRQ_HANDLED;
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}
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void __init time_init(void)
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{
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int ret;
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/*
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* Make sure we don't get any COMPARE interrupts before we can
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* handle them.
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*/
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sysreg_write(COMPARE, 0);
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xtime.tv_sec = rtc_get_time();
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xtime.tv_nsec = 0;
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set_normalized_timespec(&wall_to_monotonic,
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-xtime.tv_sec, -xtime.tv_nsec);
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ret = avr32_hpt_init();
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if (ret) {
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pr_debug("timer: failed setup: %d\n", ret);
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return;
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}
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ret = clocksource_register(&clocksource_avr32);
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if (ret)
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pr_debug("timer: could not register clocksource: %d\n", ret);
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ret = avr32_hpt_start();
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if (ret) {
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pr_debug("timer: failed starting: %d\n", ret);
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return;
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}
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}
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static struct sysdev_class timer_class = {
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set_kset_name("timer"),
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};
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static struct sys_device timer_device = {
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.id = 0,
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.cls = &timer_class,
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};
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static int __init init_timer_sysfs(void)
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{
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int err = sysdev_class_register(&timer_class);
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if (!err)
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err = sysdev_register(&timer_device);
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return err;
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}
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device_initcall(init_timer_sysfs);
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