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We used to emit a flush_icache_all() whenever a dirty executable mapping is set in the page table but we can instead call flush_icache_mm() which will only send IPIs to cores that currently run this mm and add a deferred icache flush to the others. The number of calls to sbi_remote_fence_i() (tested without IPI support): With a simple buildroot rootfs: * Before: ~5k * After : 4 (!) Tested on HW, the boot to login is ~4.5% faster. With an ubuntu rootfs: * Before: ~24k * After : ~13k Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20240202124711.256146-1-alexghiti@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
145 lines
3.1 KiB
C
145 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <asm/pgalloc.h>
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#include <linux/gfp.h>
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#include <linux/kernel.h>
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#include <linux/pgtable.h>
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int ptep_set_access_flags(struct vm_area_struct *vma,
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unsigned long address, pte_t *ptep,
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pte_t entry, int dirty)
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{
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if (!pte_same(ptep_get(ptep), entry))
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__set_pte_at(vma->vm_mm, ptep, entry);
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/*
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* update_mmu_cache will unconditionally execute, handling both
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* the case that the PTE changed and the spurious fault case.
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*/
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return true;
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}
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int ptep_test_and_clear_young(struct vm_area_struct *vma,
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unsigned long address,
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pte_t *ptep)
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{
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if (!pte_young(ptep_get(ptep)))
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return 0;
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return test_and_clear_bit(_PAGE_ACCESSED_OFFSET, &pte_val(*ptep));
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}
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EXPORT_SYMBOL_GPL(ptep_test_and_clear_young);
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#ifdef CONFIG_64BIT
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pud_t *pud_offset(p4d_t *p4d, unsigned long address)
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{
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if (pgtable_l4_enabled)
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return p4d_pgtable(p4dp_get(p4d)) + pud_index(address);
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return (pud_t *)p4d;
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}
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p4d_t *p4d_offset(pgd_t *pgd, unsigned long address)
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{
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if (pgtable_l5_enabled)
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return pgd_pgtable(pgdp_get(pgd)) + p4d_index(address);
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return (p4d_t *)pgd;
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}
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#endif
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#ifdef CONFIG_HAVE_ARCH_HUGE_VMAP
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int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot)
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{
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return 0;
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}
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void p4d_clear_huge(p4d_t *p4d)
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{
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}
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int pud_set_huge(pud_t *pud, phys_addr_t phys, pgprot_t prot)
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{
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pud_t new_pud = pfn_pud(__phys_to_pfn(phys), prot);
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set_pud(pud, new_pud);
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return 1;
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}
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int pud_clear_huge(pud_t *pud)
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{
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if (!pud_leaf(pudp_get(pud)))
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return 0;
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pud_clear(pud);
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return 1;
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}
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int pud_free_pmd_page(pud_t *pud, unsigned long addr)
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{
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pmd_t *pmd = pud_pgtable(pudp_get(pud));
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int i;
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pud_clear(pud);
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flush_tlb_kernel_range(addr, addr + PUD_SIZE);
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for (i = 0; i < PTRS_PER_PMD; i++) {
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if (!pmd_none(pmd[i])) {
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pte_t *pte = (pte_t *)pmd_page_vaddr(pmd[i]);
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pte_free_kernel(NULL, pte);
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}
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}
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pmd_free(NULL, pmd);
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return 1;
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}
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int pmd_set_huge(pmd_t *pmd, phys_addr_t phys, pgprot_t prot)
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{
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pmd_t new_pmd = pfn_pmd(__phys_to_pfn(phys), prot);
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set_pmd(pmd, new_pmd);
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return 1;
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}
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int pmd_clear_huge(pmd_t *pmd)
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{
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if (!pmd_leaf(pmdp_get(pmd)))
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return 0;
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pmd_clear(pmd);
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return 1;
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}
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int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
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{
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pte_t *pte = (pte_t *)pmd_page_vaddr(pmdp_get(pmd));
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pmd_clear(pmd);
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flush_tlb_kernel_range(addr, addr + PMD_SIZE);
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pte_free_kernel(NULL, pte);
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return 1;
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}
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#endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
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unsigned long address, pmd_t *pmdp)
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{
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pmd_t pmd = pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp);
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VM_BUG_ON(address & ~HPAGE_PMD_MASK);
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VM_BUG_ON(pmd_trans_huge(pmdp_get(pmdp)));
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/*
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* When leaf PTE entries (regular pages) are collapsed into a leaf
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* PMD entry (huge page), a valid non-leaf PTE is converted into a
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* valid leaf PTE at the level 1 page table. Since the sfence.vma
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* forms that specify an address only apply to leaf PTEs, we need a
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* global flush here. collapse_huge_page() assumes these flushes are
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* eager, so just do the fence here.
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*/
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flush_tlb_mm(vma->vm_mm);
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return pmd;
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}
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#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
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