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5a70972e14
drivers/media/dvb-frontends/drxk_hard.c:68:13: warning: 'IsA1WithPatchCode' defined but not used [-Wunused-function] drivers/media/dvb-frontends/drxk_hard.c:73:13: warning: 'IsA1WithRomCode' defined but not used [-Wunused-function] Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
361 lines
11 KiB
C
361 lines
11 KiB
C
#include "drxk_map.h"
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#define DRXK_VERSION_MAJOR 0
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#define DRXK_VERSION_MINOR 9
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#define DRXK_VERSION_PATCH 4300
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#define HI_I2C_DELAY 42
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#define HI_I2C_BRIDGE_DELAY 350
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#define DRXK_MAX_RETRIES 100
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#define DRIVER_4400 1
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#define DRXX_JTAGID 0x039210D9
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#define DRXX_J_JTAGID 0x239310D9
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#define DRXX_K_JTAGID 0x039210D9
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#define DRX_UNKNOWN 254
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#define DRX_AUTO 255
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#define DRX_SCU_READY 0
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#define DRXK_MAX_WAITTIME (200)
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#define SCU_RESULT_OK 0
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#define SCU_RESULT_SIZE -4
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#define SCU_RESULT_INVPAR -3
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#define SCU_RESULT_UNKSTD -2
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#define SCU_RESULT_UNKCMD -1
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#ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT
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#define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200)
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#endif
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#define DRXK_8VSB_MPEG_BIT_RATE 19392658UL /*bps*/
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#define DRXK_DVBT_MPEG_BIT_RATE 32000000UL /*bps*/
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#define DRXK_QAM16_MPEG_BIT_RATE 27000000UL /*bps*/
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#define DRXK_QAM32_MPEG_BIT_RATE 33000000UL /*bps*/
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#define DRXK_QAM64_MPEG_BIT_RATE 40000000UL /*bps*/
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#define DRXK_QAM128_MPEG_BIT_RATE 46000000UL /*bps*/
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#define DRXK_QAM256_MPEG_BIT_RATE 52000000UL /*bps*/
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#define DRXK_MAX_MPEG_BIT_RATE 52000000UL /*bps*/
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#define IQM_CF_OUT_ENA_OFDM__M 0x4
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#define IQM_FS_ADJ_SEL_B_QAM 0x1
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#define IQM_FS_ADJ_SEL_B_OFF 0x0
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#define IQM_FS_ADJ_SEL_B_VSB 0x2
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#define IQM_RC_ADJ_SEL_B_OFF 0x0
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#define IQM_RC_ADJ_SEL_B_QAM 0x1
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#define IQM_RC_ADJ_SEL_B_VSB 0x2
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enum OperationMode {
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OM_NONE,
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OM_QAM_ITU_A,
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OM_QAM_ITU_B,
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OM_QAM_ITU_C,
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OM_DVBT
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};
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enum DRXPowerMode {
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DRX_POWER_UP = 0,
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DRX_POWER_MODE_1,
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DRX_POWER_MODE_2,
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DRX_POWER_MODE_3,
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DRX_POWER_MODE_4,
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DRX_POWER_MODE_5,
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DRX_POWER_MODE_6,
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DRX_POWER_MODE_7,
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DRX_POWER_MODE_8,
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DRX_POWER_MODE_9,
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DRX_POWER_MODE_10,
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DRX_POWER_MODE_11,
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DRX_POWER_MODE_12,
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DRX_POWER_MODE_13,
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DRX_POWER_MODE_14,
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DRX_POWER_MODE_15,
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DRX_POWER_MODE_16,
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DRX_POWER_DOWN = 255
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};
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/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */
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#ifndef DRXK_POWER_DOWN_OFDM
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#define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1
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#endif
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/** /brief Intermediate power mode for DRXK, power down core (sysclk) */
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#ifndef DRXK_POWER_DOWN_CORE
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#define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9
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#endif
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/** /brief Intermediate power mode for DRXK, power down pll (only osc runs) */
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#ifndef DRXK_POWER_DOWN_PLL
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#define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10
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#endif
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enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF };
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enum EDrxkState {
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DRXK_UNINITIALIZED = 0,
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DRXK_STOPPED,
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DRXK_DTV_STARTED,
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DRXK_ATV_STARTED,
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DRXK_POWERED_DOWN,
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DRXK_NO_DEV /* If drxk init failed */
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};
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enum EDrxkCoefArrayIndex {
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DRXK_COEF_IDX_MN = 0,
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DRXK_COEF_IDX_FM ,
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DRXK_COEF_IDX_L ,
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DRXK_COEF_IDX_LP ,
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DRXK_COEF_IDX_BG ,
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DRXK_COEF_IDX_DK ,
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DRXK_COEF_IDX_I ,
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DRXK_COEF_IDX_MAX
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};
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enum EDrxkSifAttenuation {
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DRXK_SIF_ATTENUATION_0DB,
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DRXK_SIF_ATTENUATION_3DB,
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DRXK_SIF_ATTENUATION_6DB,
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DRXK_SIF_ATTENUATION_9DB
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};
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enum EDrxkConstellation {
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DRX_CONSTELLATION_BPSK = 0,
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DRX_CONSTELLATION_QPSK,
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DRX_CONSTELLATION_PSK8,
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DRX_CONSTELLATION_QAM16,
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DRX_CONSTELLATION_QAM32,
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DRX_CONSTELLATION_QAM64,
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DRX_CONSTELLATION_QAM128,
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DRX_CONSTELLATION_QAM256,
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DRX_CONSTELLATION_QAM512,
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DRX_CONSTELLATION_QAM1024,
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DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
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DRX_CONSTELLATION_AUTO = DRX_AUTO
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};
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enum EDrxkInterleaveMode {
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DRXK_QAM_I12_J17 = 16,
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DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN
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};
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enum {
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DRXK_SPIN_A1 = 0,
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DRXK_SPIN_A2,
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DRXK_SPIN_A3,
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DRXK_SPIN_UNKNOWN
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};
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enum DRXKCfgDvbtSqiSpeed {
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DRXK_DVBT_SQI_SPEED_FAST = 0,
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DRXK_DVBT_SQI_SPEED_MEDIUM,
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DRXK_DVBT_SQI_SPEED_SLOW,
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DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
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} ;
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enum DRXFftmode_t {
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DRX_FFTMODE_2K = 0,
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DRX_FFTMODE_4K,
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DRX_FFTMODE_8K,
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DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN,
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DRX_FFTMODE_AUTO = DRX_AUTO
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};
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enum DRXMPEGStrWidth_t {
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DRX_MPEG_STR_WIDTH_1,
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DRX_MPEG_STR_WIDTH_8
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};
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enum DRXQamLockRange_t {
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DRX_QAM_LOCKRANGE_NORMAL,
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DRX_QAM_LOCKRANGE_EXTENDED
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};
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struct DRXKCfgDvbtEchoThres_t {
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u16 threshold;
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enum DRXFftmode_t fftMode;
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} ;
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struct SCfgAgc {
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enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */
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u16 outputLevel; /* range dependent on AGC */
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u16 minOutputLevel; /* range dependent on AGC */
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u16 maxOutputLevel; /* range dependent on AGC */
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u16 speed; /* range dependent on AGC */
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u16 top; /* rf-agc take over point */
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u16 cutOffCurrent; /* rf-agc is accelerated if output current
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is below cut-off current */
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u16 IngainTgtMax;
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u16 FastClipCtrlDelay;
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};
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struct SCfgPreSaw {
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u16 reference; /* pre SAW reference value, range 0 .. 31 */
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bool usePreSaw; /* TRUE algorithms must use pre SAW sense */
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};
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struct DRXKOfdmScCmd_t {
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u16 cmd; /**< Command number */
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u16 subcmd; /**< Sub-command parameter*/
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u16 param0; /**< General purpous param */
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u16 param1; /**< General purpous param */
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u16 param2; /**< General purpous param */
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u16 param3; /**< General purpous param */
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u16 param4; /**< General purpous param */
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};
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struct drxk_state {
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struct dvb_frontend frontend;
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struct dtv_frontend_properties props;
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struct device *dev;
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struct i2c_adapter *i2c;
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u8 demod_address;
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void *priv;
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struct mutex mutex;
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u32 m_Instance; /**< Channel 1,2,3 or 4 */
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int m_ChunkSize;
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u8 Chunk[256];
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bool m_hasLNA;
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bool m_hasDVBT;
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bool m_hasDVBC;
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bool m_hasAudio;
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bool m_hasATV;
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bool m_hasOOB;
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bool m_hasSAWSW; /**< TRUE if mat_tx is available */
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bool m_hasGPIO1; /**< TRUE if mat_rx is available */
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bool m_hasGPIO2; /**< TRUE if GPIO is available */
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bool m_hasIRQN; /**< TRUE if IRQN is available */
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u16 m_oscClockFreq;
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u16 m_HICfgTimingDiv;
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u16 m_HICfgBridgeDelay;
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u16 m_HICfgWakeUpKey;
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u16 m_HICfgTimeout;
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u16 m_HICfgCtrl;
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s32 m_sysClockFreq; /**< system clock frequency in kHz */
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enum EDrxkState m_DrxkState; /**< State of Drxk (init,stopped,started) */
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enum OperationMode m_OperationMode; /**< digital standards */
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struct SCfgAgc m_vsbRfAgcCfg; /**< settings for VSB RF-AGC */
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struct SCfgAgc m_vsbIfAgcCfg; /**< settings for VSB IF-AGC */
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u16 m_vsbPgaCfg; /**< settings for VSB PGA */
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struct SCfgPreSaw m_vsbPreSawCfg; /**< settings for pre SAW sense */
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s32 m_Quality83percent; /**< MER level (*0.1 dB) for 83% quality indication */
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s32 m_Quality93percent; /**< MER level (*0.1 dB) for 93% quality indication */
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bool m_smartAntInverted;
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bool m_bDebugEnableBridge;
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bool m_bPDownOpenBridge; /**< only open DRXK bridge before power-down once it has been accessed */
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bool m_bPowerDown; /**< Power down when not used */
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u32 m_IqmFsRateOfs; /**< frequency shift as written to DRXK register (28bit fixpoint) */
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bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */
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bool m_insertRSByte; /**< If TRUE, insert RS byte */
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bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */
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bool m_invertDATA; /**< If TRUE, invert DATA signals */
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bool m_invertERR; /**< If TRUE, invert ERR signal */
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bool m_invertSTR; /**< If TRUE, invert STR signals */
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bool m_invertVAL; /**< If TRUE, invert VAL signals */
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bool m_invertCLK; /**< If TRUE, invert CLK signals */
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bool m_DVBCStaticCLK;
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bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will
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be used, otherwise clockrate will
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adapt to the bitrate of the TS */
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u32 m_DVBTBitrate;
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u32 m_DVBCBitrate;
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u8 m_TSDataStrength;
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u8 m_TSClockkStrength;
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bool m_itut_annex_c; /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */
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enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width */
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u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case
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static clockrate is selected */
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/* LARGE_INTEGER m_StartTime; */ /**< Contains the time of the last demod start */
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s32 m_MpegLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */
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s32 m_DemodLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */
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bool m_disableTEIhandling;
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bool m_RfAgcPol;
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bool m_IfAgcPol;
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struct SCfgAgc m_atvRfAgcCfg; /**< settings for ATV RF-AGC */
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struct SCfgAgc m_atvIfAgcCfg; /**< settings for ATV IF-AGC */
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struct SCfgPreSaw m_atvPreSawCfg; /**< settings for ATV pre SAW sense */
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bool m_phaseCorrectionBypass;
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s16 m_atvTopVidPeak;
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u16 m_atvTopNoiseTh;
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enum EDrxkSifAttenuation m_sifAttenuation;
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bool m_enableCVBSOutput;
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bool m_enableSIFOutput;
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bool m_bMirrorFreqSpect;
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enum EDrxkConstellation m_Constellation; /**< Constellation type of the channel */
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u32 m_CurrSymbolRate; /**< Current QAM symbol rate */
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struct SCfgAgc m_qamRfAgcCfg; /**< settings for QAM RF-AGC */
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struct SCfgAgc m_qamIfAgcCfg; /**< settings for QAM IF-AGC */
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u16 m_qamPgaCfg; /**< settings for QAM PGA */
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struct SCfgPreSaw m_qamPreSawCfg; /**< settings for QAM pre SAW sense */
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enum EDrxkInterleaveMode m_qamInterleaveMode; /**< QAM Interleave mode */
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u16 m_fecRsPlen;
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u16 m_fecRsPrescale;
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enum DRXKCfgDvbtSqiSpeed m_sqiSpeed;
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u16 m_GPIO;
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u16 m_GPIOCfg;
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struct SCfgAgc m_dvbtRfAgcCfg; /**< settings for QAM RF-AGC */
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struct SCfgAgc m_dvbtIfAgcCfg; /**< settings for QAM IF-AGC */
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struct SCfgPreSaw m_dvbtPreSawCfg; /**< settings for QAM pre SAW sense */
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u16 m_agcFastClipCtrlDelay;
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bool m_adcCompPassed;
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u16 m_adcCompCoef[64];
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u16 m_adcState;
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u8 *m_microcode;
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int m_microcode_length;
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bool m_DRXK_A3_ROM_CODE;
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bool m_DRXK_A3_PATCH_CODE;
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bool m_rfmirror;
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u8 m_deviceSpin;
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u32 m_iqmRcRate;
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enum DRXPowerMode m_currentPowerMode;
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/* when true, avoids other devices to use the I2C bus */
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bool drxk_i2c_exclusive_lock;
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/*
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* Configurable parameters at the driver. They stores the values found
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* at struct drxk_config.
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*/
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u16 UIO_mask; /* Bits used by UIO */
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bool enable_merr_cfg;
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bool single_master;
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bool no_i2c_bridge;
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bool antenna_dvbt;
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u16 antenna_gpio;
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/* Firmware */
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const char *microcode_name;
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struct completion fw_wait_load;
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const struct firmware *fw;
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int qam_demod_parameter_count;
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};
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#define NEVER_LOCK 0
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#define NOT_LOCKED 1
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#define DEMOD_LOCK 2
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#define FEC_LOCK 3
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#define MPEG_LOCK 4
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