mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
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66e514c14a
- Inherit/reuse firmwar framebuffers (for real this time) from Jesse, less flicker for fastbooting. - More flexible cloning for hdmi (Ville). - Some PPGTT fixes from Ben. - Ring init fixes from Naresh Kumar. - set_cache_level regression fixes for the vma conversion from Ville&Chris. - Conversion to the new dp aux helpers (Jani). - Unification of runtime pm with pc8 support from Paulo, prep work for runtime pm on other platforms than HSW. - Larger cursor sizes (Sagar Kamble). - Piles of improvements and fixes all over, as usual. * tag 'drm-intel-next-2014-03-21' of git://anongit.freedesktop.org/drm-intel: (75 commits) drm/i915: Include a note about the dangers of I915_READ64/I915_WRITE64 drm/i915/sdvo: fix questionable return value check drm/i915: Fix unsafe loop iteration over vma whilst unbinding them drm/i915: Enabling 128x128 and 256x256 ARGB Cursor Support drm/i915: Print how many objects are shared in per-process stats drm/i915: Per-process stats work better when evaluated per-process drm/i915: remove rps local variables drm/i915: Remove extraneous MMIO for RPS drm/i915: Rename and comment all the RPS *stuff* drm/i915: Store the HW min frequency as min_freq drm/i915: Fix coding style for RPS drm/i915: Reorganize the overclock code drm/i915: init pm.suspended earlier drm/i915: update the PC8 and runtime PM documentation drm/i915: rename __hsw_do_{en, dis}able_pc8 drm/i915: kill struct i915_package_c8 drm/i915: move pc8.irqs_disabled to pm.irqs_disabled drm/i915: remove dev_priv->pc8.enabled drm/i915: don't get/put PC8 when getting/putting power wells drm/i915: make intel_aux_display_runtime_get get runtime PM, not PC8 ... Conflicts: drivers/gpu/drm/i915/intel_display.c drivers/gpu/drm/i915/intel_dp.c
1138 lines
32 KiB
C
1138 lines
32 KiB
C
/*
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* Copyright © 2006-2007 Intel Corporation
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* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Dave Airlie <airlied@linux.ie>
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* Jesse Barnes <jesse.barnes@intel.com>
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*/
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#include <acpi/button.h>
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#include <linux/dmi.h>
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#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_edid.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include <linux/acpi.h>
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/* Private structure for the integrated LVDS support */
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struct intel_lvds_connector {
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struct intel_connector base;
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struct notifier_block lid_notifier;
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};
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struct intel_lvds_encoder {
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struct intel_encoder base;
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bool is_dual_link;
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u32 reg;
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struct intel_lvds_connector *attached_connector;
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};
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static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
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{
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return container_of(encoder, struct intel_lvds_encoder, base.base);
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}
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static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
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{
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return container_of(connector, struct intel_lvds_connector, base.base);
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}
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static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
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enum pipe *pipe)
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{
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struct drm_device *dev = encoder->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
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u32 tmp;
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tmp = I915_READ(lvds_encoder->reg);
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if (!(tmp & LVDS_PORT_EN))
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return false;
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if (HAS_PCH_CPT(dev))
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*pipe = PORT_TO_PIPE_CPT(tmp);
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else
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*pipe = PORT_TO_PIPE(tmp);
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return true;
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}
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static void intel_lvds_get_config(struct intel_encoder *encoder,
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struct intel_crtc_config *pipe_config)
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{
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struct drm_device *dev = encoder->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 lvds_reg, tmp, flags = 0;
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int dotclock;
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if (HAS_PCH_SPLIT(dev))
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lvds_reg = PCH_LVDS;
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else
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lvds_reg = LVDS;
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tmp = I915_READ(lvds_reg);
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if (tmp & LVDS_HSYNC_POLARITY)
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flags |= DRM_MODE_FLAG_NHSYNC;
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else
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flags |= DRM_MODE_FLAG_PHSYNC;
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if (tmp & LVDS_VSYNC_POLARITY)
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flags |= DRM_MODE_FLAG_NVSYNC;
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else
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flags |= DRM_MODE_FLAG_PVSYNC;
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pipe_config->adjusted_mode.flags |= flags;
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/* gen2/3 store dither state in pfit control, needs to match */
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if (INTEL_INFO(dev)->gen < 4) {
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tmp = I915_READ(PFIT_CONTROL);
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pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
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}
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dotclock = pipe_config->port_clock;
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if (HAS_PCH_SPLIT(dev_priv->dev))
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ironlake_check_encoder_dotclock(pipe_config, dotclock);
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pipe_config->adjusted_mode.crtc_clock = dotclock;
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}
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/* The LVDS pin pair needs to be on before the DPLLs are enabled.
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* This is an exception to the general rule that mode_set doesn't turn
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* things on.
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*/
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static void intel_pre_enable_lvds(struct intel_encoder *encoder)
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{
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struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
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struct drm_device *dev = encoder->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
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const struct drm_display_mode *adjusted_mode =
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&crtc->config.adjusted_mode;
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int pipe = crtc->pipe;
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u32 temp;
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if (HAS_PCH_SPLIT(dev)) {
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assert_fdi_rx_pll_disabled(dev_priv, pipe);
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assert_shared_dpll_disabled(dev_priv,
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intel_crtc_to_shared_dpll(crtc));
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} else {
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assert_pll_disabled(dev_priv, pipe);
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}
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temp = I915_READ(lvds_encoder->reg);
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temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
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if (HAS_PCH_CPT(dev)) {
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temp &= ~PORT_TRANS_SEL_MASK;
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temp |= PORT_TRANS_SEL_CPT(pipe);
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} else {
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if (pipe == 1) {
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temp |= LVDS_PIPEB_SELECT;
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} else {
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temp &= ~LVDS_PIPEB_SELECT;
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}
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}
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/* set the corresponsding LVDS_BORDER bit */
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temp &= ~LVDS_BORDER_ENABLE;
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temp |= crtc->config.gmch_pfit.lvds_border_bits;
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/* Set the B0-B3 data pairs corresponding to whether we're going to
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* set the DPLLs for dual-channel mode or not.
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*/
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if (lvds_encoder->is_dual_link)
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temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
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else
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temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
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/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
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* appropriately here, but we need to look more thoroughly into how
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* panels behave in the two modes.
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*/
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/* Set the dithering flag on LVDS as needed, note that there is no
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* special lvds dither control bit on pch-split platforms, dithering is
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* only controlled through the PIPECONF reg. */
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if (INTEL_INFO(dev)->gen == 4) {
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/* Bspec wording suggests that LVDS port dithering only exists
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* for 18bpp panels. */
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if (crtc->config.dither && crtc->config.pipe_bpp == 18)
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temp |= LVDS_ENABLE_DITHER;
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else
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temp &= ~LVDS_ENABLE_DITHER;
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}
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temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
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if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
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temp |= LVDS_HSYNC_POLARITY;
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if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
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temp |= LVDS_VSYNC_POLARITY;
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I915_WRITE(lvds_encoder->reg, temp);
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}
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/**
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* Sets the power state for the panel.
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*/
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static void intel_enable_lvds(struct intel_encoder *encoder)
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{
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struct drm_device *dev = encoder->base.dev;
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struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
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struct intel_connector *intel_connector =
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&lvds_encoder->attached_connector->base;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 ctl_reg, stat_reg;
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if (HAS_PCH_SPLIT(dev)) {
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ctl_reg = PCH_PP_CONTROL;
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stat_reg = PCH_PP_STATUS;
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} else {
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ctl_reg = PP_CONTROL;
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stat_reg = PP_STATUS;
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}
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I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
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I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
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POSTING_READ(lvds_encoder->reg);
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if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
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DRM_ERROR("timed out waiting for panel to power on\n");
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intel_panel_enable_backlight(intel_connector);
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}
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static void intel_disable_lvds(struct intel_encoder *encoder)
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{
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struct drm_device *dev = encoder->base.dev;
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struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
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struct intel_connector *intel_connector =
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&lvds_encoder->attached_connector->base;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 ctl_reg, stat_reg;
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if (HAS_PCH_SPLIT(dev)) {
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ctl_reg = PCH_PP_CONTROL;
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stat_reg = PCH_PP_STATUS;
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} else {
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ctl_reg = PP_CONTROL;
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stat_reg = PP_STATUS;
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}
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intel_panel_disable_backlight(intel_connector);
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I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
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if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
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DRM_ERROR("timed out waiting for panel to power off\n");
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I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
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POSTING_READ(lvds_encoder->reg);
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}
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static enum drm_mode_status
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intel_lvds_mode_valid(struct drm_connector *connector,
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struct drm_display_mode *mode)
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{
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struct intel_connector *intel_connector = to_intel_connector(connector);
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struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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if (mode->hdisplay > fixed_mode->hdisplay)
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return MODE_PANEL;
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if (mode->vdisplay > fixed_mode->vdisplay)
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return MODE_PANEL;
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return MODE_OK;
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}
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static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
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struct intel_crtc_config *pipe_config)
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{
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struct drm_device *dev = intel_encoder->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_lvds_encoder *lvds_encoder =
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to_lvds_encoder(&intel_encoder->base);
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struct intel_connector *intel_connector =
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&lvds_encoder->attached_connector->base;
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struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
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struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
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unsigned int lvds_bpp;
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/* Should never happen!! */
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if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
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DRM_ERROR("Can't support LVDS on pipe A\n");
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return false;
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}
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if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) ==
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LVDS_A3_POWER_UP)
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lvds_bpp = 8*3;
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else
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lvds_bpp = 6*3;
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if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
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DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
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pipe_config->pipe_bpp, lvds_bpp);
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pipe_config->pipe_bpp = lvds_bpp;
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}
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/*
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* We have timings from the BIOS for the panel, put them in
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* to the adjusted mode. The CRTC will be set up for this mode,
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* with the panel scaling set up to source from the H/VDisplay
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* of the original mode.
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*/
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intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
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adjusted_mode);
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if (HAS_PCH_SPLIT(dev)) {
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pipe_config->has_pch_encoder = true;
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intel_pch_panel_fitting(intel_crtc, pipe_config,
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intel_connector->panel.fitting_mode);
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} else {
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intel_gmch_panel_fitting(intel_crtc, pipe_config,
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intel_connector->panel.fitting_mode);
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}
|
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|
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/*
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* XXX: It would be nice to support lower refresh rates on the
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* panels to reduce power consumption, and perhaps match the
|
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* user's requested refresh rate.
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*/
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return true;
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}
|
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|
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static void intel_lvds_mode_set(struct intel_encoder *encoder)
|
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{
|
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/*
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* We don't do anything here, the LVDS port is fully set up in the pre
|
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* enable hook - the ordering constraints for enabling the lvds port vs.
|
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* enabling the display pll are too strict.
|
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*/
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}
|
|
|
|
/**
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* Detect the LVDS connection.
|
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*
|
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* Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
|
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* connected and closed means disconnected. We also send hotplug events as
|
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* needed, using lid status notification from the input layer.
|
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*/
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static enum drm_connector_status
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intel_lvds_detect(struct drm_connector *connector, bool force)
|
|
{
|
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struct drm_device *dev = connector->dev;
|
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enum drm_connector_status status;
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DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
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connector->base.id, drm_get_connector_name(connector));
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|
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status = intel_panel_detect(dev);
|
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if (status != connector_status_unknown)
|
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return status;
|
|
|
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return connector_status_connected;
|
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}
|
|
|
|
/**
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* Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
|
|
*/
|
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static int intel_lvds_get_modes(struct drm_connector *connector)
|
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{
|
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struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
|
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struct drm_device *dev = connector->dev;
|
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struct drm_display_mode *mode;
|
|
|
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/* use cached edid if we have one */
|
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if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
|
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return drm_add_edid_modes(connector, lvds_connector->base.edid);
|
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|
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mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
|
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if (mode == NULL)
|
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return 0;
|
|
|
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drm_mode_probed_add(connector, mode);
|
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return 1;
|
|
}
|
|
|
|
static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
|
|
{
|
|
DRM_INFO("Skipping forced modeset for %s\n", id->ident);
|
|
return 1;
|
|
}
|
|
|
|
/* The GPU hangs up on these systems if modeset is performed on LID open */
|
|
static const struct dmi_system_id intel_no_modeset_on_lid[] = {
|
|
{
|
|
.callback = intel_no_modeset_on_lid_dmi_callback,
|
|
.ident = "Toshiba Tecra A11",
|
|
.matches = {
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
|
|
},
|
|
},
|
|
|
|
{ } /* terminating entry */
|
|
};
|
|
|
|
/*
|
|
* Lid events. Note the use of 'modeset':
|
|
* - we set it to MODESET_ON_LID_OPEN on lid close,
|
|
* and set it to MODESET_DONE on open
|
|
* - we use it as a "only once" bit (ie we ignore
|
|
* duplicate events where it was already properly set)
|
|
* - the suspend/resume paths will set it to
|
|
* MODESET_SUSPENDED and ignore the lid open event,
|
|
* because they restore the mode ("lid open").
|
|
*/
|
|
static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
|
|
void *unused)
|
|
{
|
|
struct intel_lvds_connector *lvds_connector =
|
|
container_of(nb, struct intel_lvds_connector, lid_notifier);
|
|
struct drm_connector *connector = &lvds_connector->base.base;
|
|
struct drm_device *dev = connector->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
|
|
return NOTIFY_OK;
|
|
|
|
mutex_lock(&dev_priv->modeset_restore_lock);
|
|
if (dev_priv->modeset_restore == MODESET_SUSPENDED)
|
|
goto exit;
|
|
/*
|
|
* check and update the status of LVDS connector after receiving
|
|
* the LID nofication event.
|
|
*/
|
|
connector->status = connector->funcs->detect(connector, false);
|
|
|
|
/* Don't force modeset on machines where it causes a GPU lockup */
|
|
if (dmi_check_system(intel_no_modeset_on_lid))
|
|
goto exit;
|
|
if (!acpi_lid_open()) {
|
|
/* do modeset on next lid open event */
|
|
dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
|
|
goto exit;
|
|
}
|
|
|
|
if (dev_priv->modeset_restore == MODESET_DONE)
|
|
goto exit;
|
|
|
|
/*
|
|
* Some old platform's BIOS love to wreak havoc while the lid is closed.
|
|
* We try to detect this here and undo any damage. The split for PCH
|
|
* platforms is rather conservative and a bit arbitrary expect that on
|
|
* those platforms VGA disabling requires actual legacy VGA I/O access,
|
|
* and as part of the cleanup in the hw state restore we also redisable
|
|
* the vga plane.
|
|
*/
|
|
if (!HAS_PCH_SPLIT(dev)) {
|
|
drm_modeset_lock_all(dev);
|
|
intel_modeset_setup_hw_state(dev, true);
|
|
drm_modeset_unlock_all(dev);
|
|
}
|
|
|
|
dev_priv->modeset_restore = MODESET_DONE;
|
|
|
|
exit:
|
|
mutex_unlock(&dev_priv->modeset_restore_lock);
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
/**
|
|
* intel_lvds_destroy - unregister and free LVDS structures
|
|
* @connector: connector to free
|
|
*
|
|
* Unregister the DDC bus for this connector then free the driver private
|
|
* structure.
|
|
*/
|
|
static void intel_lvds_destroy(struct drm_connector *connector)
|
|
{
|
|
struct intel_lvds_connector *lvds_connector =
|
|
to_lvds_connector(connector);
|
|
|
|
if (lvds_connector->lid_notifier.notifier_call)
|
|
acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
|
|
|
|
if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
|
|
kfree(lvds_connector->base.edid);
|
|
|
|
intel_panel_fini(&lvds_connector->base.panel);
|
|
|
|
drm_connector_cleanup(connector);
|
|
kfree(connector);
|
|
}
|
|
|
|
static int intel_lvds_set_property(struct drm_connector *connector,
|
|
struct drm_property *property,
|
|
uint64_t value)
|
|
{
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
|
struct drm_device *dev = connector->dev;
|
|
|
|
if (property == dev->mode_config.scaling_mode_property) {
|
|
struct drm_crtc *crtc;
|
|
|
|
if (value == DRM_MODE_SCALE_NONE) {
|
|
DRM_DEBUG_KMS("no scaling not supported\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (intel_connector->panel.fitting_mode == value) {
|
|
/* the LVDS scaling property is not changed */
|
|
return 0;
|
|
}
|
|
intel_connector->panel.fitting_mode = value;
|
|
|
|
crtc = intel_attached_encoder(connector)->base.crtc;
|
|
if (crtc && crtc->enabled) {
|
|
/*
|
|
* If the CRTC is enabled, the display will be changed
|
|
* according to the new panel fitting mode.
|
|
*/
|
|
intel_crtc_restore_mode(crtc);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
|
|
.get_modes = intel_lvds_get_modes,
|
|
.mode_valid = intel_lvds_mode_valid,
|
|
.best_encoder = intel_best_encoder,
|
|
};
|
|
|
|
static const struct drm_connector_funcs intel_lvds_connector_funcs = {
|
|
.dpms = intel_connector_dpms,
|
|
.detect = intel_lvds_detect,
|
|
.fill_modes = drm_helper_probe_single_connector_modes,
|
|
.set_property = intel_lvds_set_property,
|
|
.destroy = intel_lvds_destroy,
|
|
};
|
|
|
|
static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
|
|
.destroy = intel_encoder_destroy,
|
|
};
|
|
|
|
static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
|
|
{
|
|
DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
|
|
return 1;
|
|
}
|
|
|
|
/* These systems claim to have LVDS, but really don't */
|
|
static const struct dmi_system_id intel_no_lvds[] = {
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Apple Mac Mini (Core series)",
|
|
.matches = {
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Apple Mac Mini (Core 2 series)",
|
|
.matches = {
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "MSI IM-945GSE-A",
|
|
.matches = {
|
|
DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Dell Studio Hybrid",
|
|
.matches = {
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Dell OptiPlex FX170",
|
|
.matches = {
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "AOpen Mini PC",
|
|
.matches = {
|
|
DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "AOpen Mini PC MP915",
|
|
.matches = {
|
|
DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
|
|
DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "AOpen i915GMm-HFS",
|
|
.matches = {
|
|
DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
|
|
DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "AOpen i45GMx-I",
|
|
.matches = {
|
|
DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
|
|
DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Aopen i945GTt-VFA",
|
|
.matches = {
|
|
DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Clientron U800",
|
|
.matches = {
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Clientron E830",
|
|
.matches = {
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Asus EeeBox PC EB1007",
|
|
.matches = {
|
|
DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Asus AT5NM10T-I",
|
|
.matches = {
|
|
DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
|
|
DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Hewlett-Packard HP t5740",
|
|
.matches = {
|
|
DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
|
|
DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Hewlett-Packard t5745",
|
|
.matches = {
|
|
DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Hewlett-Packard st5747",
|
|
.matches = {
|
|
DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "MSI Wind Box DC500",
|
|
.matches = {
|
|
DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
|
|
DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Gigabyte GA-D525TUD",
|
|
.matches = {
|
|
DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
|
|
DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Supermicro X7SPA-H",
|
|
.matches = {
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Fujitsu Esprimo Q900",
|
|
.matches = {
|
|
DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Intel D410PT",
|
|
.matches = {
|
|
DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
|
|
DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Intel D425KT",
|
|
.matches = {
|
|
DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
|
|
DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Intel D510MO",
|
|
.matches = {
|
|
DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
|
|
DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
|
|
},
|
|
},
|
|
{
|
|
.callback = intel_no_lvds_dmi_callback,
|
|
.ident = "Intel D525MW",
|
|
.matches = {
|
|
DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
|
|
DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
|
|
},
|
|
},
|
|
|
|
{ } /* terminating entry */
|
|
};
|
|
|
|
/*
|
|
* Enumerate the child dev array parsed from VBT to check whether
|
|
* the LVDS is present.
|
|
* If it is present, return 1.
|
|
* If it is not present, return false.
|
|
* If no child dev is parsed from VBT, it assumes that the LVDS is present.
|
|
*/
|
|
static bool lvds_is_present_in_vbt(struct drm_device *dev,
|
|
u8 *i2c_pin)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
int i;
|
|
|
|
if (!dev_priv->vbt.child_dev_num)
|
|
return true;
|
|
|
|
for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
|
|
union child_device_config *uchild = dev_priv->vbt.child_dev + i;
|
|
struct old_child_dev_config *child = &uchild->old;
|
|
|
|
/* If the device type is not LFP, continue.
|
|
* We have to check both the new identifiers as well as the
|
|
* old for compatibility with some BIOSes.
|
|
*/
|
|
if (child->device_type != DEVICE_TYPE_INT_LFP &&
|
|
child->device_type != DEVICE_TYPE_LFP)
|
|
continue;
|
|
|
|
if (intel_gmbus_is_port_valid(child->i2c_pin))
|
|
*i2c_pin = child->i2c_pin;
|
|
|
|
/* However, we cannot trust the BIOS writers to populate
|
|
* the VBT correctly. Since LVDS requires additional
|
|
* information from AIM blocks, a non-zero addin offset is
|
|
* a good indicator that the LVDS is actually present.
|
|
*/
|
|
if (child->addin_offset)
|
|
return true;
|
|
|
|
/* But even then some BIOS writers perform some black magic
|
|
* and instantiate the device without reference to any
|
|
* additional data. Trust that if the VBT was written into
|
|
* the OpRegion then they have validated the LVDS's existence.
|
|
*/
|
|
if (dev_priv->opregion.vbt)
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
|
|
{
|
|
DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
|
|
return 1;
|
|
}
|
|
|
|
static const struct dmi_system_id intel_dual_link_lvds[] = {
|
|
{
|
|
.callback = intel_dual_link_lvds_callback,
|
|
.ident = "Apple MacBook Pro (Core i5/i7 Series)",
|
|
.matches = {
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
|
|
},
|
|
},
|
|
{ } /* terminating entry */
|
|
};
|
|
|
|
bool intel_is_dual_link_lvds(struct drm_device *dev)
|
|
{
|
|
struct intel_encoder *encoder;
|
|
struct intel_lvds_encoder *lvds_encoder;
|
|
|
|
list_for_each_entry(encoder, &dev->mode_config.encoder_list,
|
|
base.head) {
|
|
if (encoder->type == INTEL_OUTPUT_LVDS) {
|
|
lvds_encoder = to_lvds_encoder(&encoder->base);
|
|
|
|
return lvds_encoder->is_dual_link;
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
|
|
{
|
|
struct drm_device *dev = lvds_encoder->base.base.dev;
|
|
unsigned int val;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
/* use the module option value if specified */
|
|
if (i915.lvds_channel_mode > 0)
|
|
return i915.lvds_channel_mode == 2;
|
|
|
|
if (dmi_check_system(intel_dual_link_lvds))
|
|
return true;
|
|
|
|
/* BIOS should set the proper LVDS register value at boot, but
|
|
* in reality, it doesn't set the value when the lid is closed;
|
|
* we need to check "the value to be set" in VBT when LVDS
|
|
* register is uninitialized.
|
|
*/
|
|
val = I915_READ(lvds_encoder->reg);
|
|
if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
|
|
val = dev_priv->vbt.bios_lvds_val;
|
|
|
|
return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
|
|
}
|
|
|
|
static bool intel_lvds_supported(struct drm_device *dev)
|
|
{
|
|
/* With the introduction of the PCH we gained a dedicated
|
|
* LVDS presence pin, use it. */
|
|
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
|
|
return true;
|
|
|
|
/* Otherwise LVDS was only attached to mobile products,
|
|
* except for the inglorious 830gm */
|
|
if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
/**
|
|
* intel_lvds_init - setup LVDS connectors on this device
|
|
* @dev: drm device
|
|
*
|
|
* Create the connector, register the LVDS DDC bus, and try to figure out what
|
|
* modes we can display on the LVDS panel (if present).
|
|
*/
|
|
void intel_lvds_init(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_lvds_encoder *lvds_encoder;
|
|
struct intel_encoder *intel_encoder;
|
|
struct intel_lvds_connector *lvds_connector;
|
|
struct intel_connector *intel_connector;
|
|
struct drm_connector *connector;
|
|
struct drm_encoder *encoder;
|
|
struct drm_display_mode *scan; /* *modes, *bios_mode; */
|
|
struct drm_display_mode *fixed_mode = NULL;
|
|
struct drm_display_mode *downclock_mode = NULL;
|
|
struct edid *edid;
|
|
struct drm_crtc *crtc;
|
|
u32 lvds;
|
|
int pipe;
|
|
u8 pin;
|
|
|
|
if (!intel_lvds_supported(dev))
|
|
return;
|
|
|
|
/* Skip init on machines we know falsely report LVDS */
|
|
if (dmi_check_system(intel_no_lvds))
|
|
return;
|
|
|
|
pin = GMBUS_PORT_PANEL;
|
|
if (!lvds_is_present_in_vbt(dev, &pin)) {
|
|
DRM_DEBUG_KMS("LVDS is not present in VBT\n");
|
|
return;
|
|
}
|
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
|
|
return;
|
|
if (dev_priv->vbt.edp_support) {
|
|
DRM_DEBUG_KMS("disable LVDS for eDP support\n");
|
|
return;
|
|
}
|
|
}
|
|
|
|
lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
|
|
if (!lvds_encoder)
|
|
return;
|
|
|
|
lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
|
|
if (!lvds_connector) {
|
|
kfree(lvds_encoder);
|
|
return;
|
|
}
|
|
|
|
lvds_encoder->attached_connector = lvds_connector;
|
|
|
|
intel_encoder = &lvds_encoder->base;
|
|
encoder = &intel_encoder->base;
|
|
intel_connector = &lvds_connector->base;
|
|
connector = &intel_connector->base;
|
|
drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
|
|
DRM_MODE_CONNECTOR_LVDS);
|
|
|
|
drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
|
|
DRM_MODE_ENCODER_LVDS);
|
|
|
|
intel_encoder->enable = intel_enable_lvds;
|
|
intel_encoder->pre_enable = intel_pre_enable_lvds;
|
|
intel_encoder->compute_config = intel_lvds_compute_config;
|
|
intel_encoder->mode_set = intel_lvds_mode_set;
|
|
intel_encoder->disable = intel_disable_lvds;
|
|
intel_encoder->get_hw_state = intel_lvds_get_hw_state;
|
|
intel_encoder->get_config = intel_lvds_get_config;
|
|
intel_connector->get_hw_state = intel_connector_get_hw_state;
|
|
intel_connector->unregister = intel_connector_unregister;
|
|
|
|
intel_connector_attach_encoder(intel_connector, intel_encoder);
|
|
intel_encoder->type = INTEL_OUTPUT_LVDS;
|
|
|
|
intel_encoder->cloneable = 0;
|
|
if (HAS_PCH_SPLIT(dev))
|
|
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
|
|
else if (IS_GEN4(dev))
|
|
intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
|
|
else
|
|
intel_encoder->crtc_mask = (1 << 1);
|
|
|
|
drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
|
|
connector->display_info.subpixel_order = SubPixelHorizontalRGB;
|
|
connector->interlace_allowed = false;
|
|
connector->doublescan_allowed = false;
|
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
lvds_encoder->reg = PCH_LVDS;
|
|
} else {
|
|
lvds_encoder->reg = LVDS;
|
|
}
|
|
|
|
/* create the scaling mode property */
|
|
drm_mode_create_scaling_mode_property(dev);
|
|
drm_object_attach_property(&connector->base,
|
|
dev->mode_config.scaling_mode_property,
|
|
DRM_MODE_SCALE_ASPECT);
|
|
intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
|
|
/*
|
|
* LVDS discovery:
|
|
* 1) check for EDID on DDC
|
|
* 2) check for VBT data
|
|
* 3) check to see if LVDS is already on
|
|
* if none of the above, no panel
|
|
* 4) make sure lid is open
|
|
* if closed, act like it's not there for now
|
|
*/
|
|
|
|
/*
|
|
* Attempt to get the fixed panel mode from DDC. Assume that the
|
|
* preferred mode is the right one.
|
|
*/
|
|
mutex_lock(&dev->mode_config.mutex);
|
|
edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
|
|
if (edid) {
|
|
if (drm_add_edid_modes(connector, edid)) {
|
|
drm_mode_connector_update_edid_property(connector,
|
|
edid);
|
|
} else {
|
|
kfree(edid);
|
|
edid = ERR_PTR(-EINVAL);
|
|
}
|
|
} else {
|
|
edid = ERR_PTR(-ENOENT);
|
|
}
|
|
lvds_connector->base.edid = edid;
|
|
|
|
if (IS_ERR_OR_NULL(edid)) {
|
|
/* Didn't get an EDID, so
|
|
* Set wide sync ranges so we get all modes
|
|
* handed to valid_mode for checking
|
|
*/
|
|
connector->display_info.min_vfreq = 0;
|
|
connector->display_info.max_vfreq = 200;
|
|
connector->display_info.min_hfreq = 0;
|
|
connector->display_info.max_hfreq = 200;
|
|
}
|
|
|
|
list_for_each_entry(scan, &connector->probed_modes, head) {
|
|
if (scan->type & DRM_MODE_TYPE_PREFERRED) {
|
|
DRM_DEBUG_KMS("using preferred mode from EDID: ");
|
|
drm_mode_debug_printmodeline(scan);
|
|
|
|
fixed_mode = drm_mode_duplicate(dev, scan);
|
|
if (fixed_mode) {
|
|
downclock_mode =
|
|
intel_find_panel_downclock(dev,
|
|
fixed_mode, connector);
|
|
if (downclock_mode != NULL &&
|
|
i915.lvds_downclock) {
|
|
/* We found the downclock for LVDS. */
|
|
dev_priv->lvds_downclock_avail = true;
|
|
dev_priv->lvds_downclock =
|
|
downclock_mode->clock;
|
|
DRM_DEBUG_KMS("LVDS downclock is found"
|
|
" in EDID. Normal clock %dKhz, "
|
|
"downclock %dKhz\n",
|
|
fixed_mode->clock,
|
|
dev_priv->lvds_downclock);
|
|
}
|
|
goto out;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Failed to get EDID, what about VBT? */
|
|
if (dev_priv->vbt.lfp_lvds_vbt_mode) {
|
|
DRM_DEBUG_KMS("using mode from VBT: ");
|
|
drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
|
|
|
|
fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
|
|
if (fixed_mode) {
|
|
fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* If we didn't get EDID, try checking if the panel is already turned
|
|
* on. If so, assume that whatever is currently programmed is the
|
|
* correct mode.
|
|
*/
|
|
|
|
/* Ironlake: FIXME if still fail, not try pipe mode now */
|
|
if (HAS_PCH_SPLIT(dev))
|
|
goto failed;
|
|
|
|
lvds = I915_READ(LVDS);
|
|
pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
|
|
crtc = intel_get_crtc_for_pipe(dev, pipe);
|
|
|
|
if (crtc && (lvds & LVDS_PORT_EN)) {
|
|
fixed_mode = intel_crtc_mode_get(dev, crtc);
|
|
if (fixed_mode) {
|
|
DRM_DEBUG_KMS("using current (BIOS) mode: ");
|
|
drm_mode_debug_printmodeline(fixed_mode);
|
|
fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
/* If we still don't have a mode after all that, give up. */
|
|
if (!fixed_mode)
|
|
goto failed;
|
|
|
|
out:
|
|
mutex_unlock(&dev->mode_config.mutex);
|
|
|
|
lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
|
|
DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
|
|
lvds_encoder->is_dual_link ? "dual" : "single");
|
|
|
|
/*
|
|
* Unlock registers and just
|
|
* leave them unlocked
|
|
*/
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
I915_WRITE(PCH_PP_CONTROL,
|
|
I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
|
|
} else {
|
|
I915_WRITE(PP_CONTROL,
|
|
I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
|
|
}
|
|
lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
|
|
if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
|
|
DRM_DEBUG_KMS("lid notifier registration failed\n");
|
|
lvds_connector->lid_notifier.notifier_call = NULL;
|
|
}
|
|
drm_sysfs_connector_add(connector);
|
|
|
|
intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
|
|
intel_panel_setup_backlight(connector);
|
|
|
|
return;
|
|
|
|
failed:
|
|
mutex_unlock(&dev->mode_config.mutex);
|
|
|
|
DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
|
|
drm_connector_cleanup(connector);
|
|
drm_encoder_cleanup(encoder);
|
|
kfree(lvds_encoder);
|
|
kfree(lvds_connector);
|
|
return;
|
|
}
|