mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
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682b7c1c8e
Pull drm updates from Dave Airlie:
"This is the main drm merge window pull request, changes all over the
place, mostly normal levels of churn.
Highlights:
Core drm:
More cleanups, fix race on connector/encoder naming, docs updates,
object locking rework in prep for atomic modeset
i915:
mipi DSI support, valleyview power fixes, cursor size fixes,
execlist refactoring, vblank improvements, userptr support, OOM
handling improvements
radeon:
GPUVM tuning and large page size support, gart fixes, deep color
HDMI support, HDMI audio cleanups
nouveau:
- displayport rework should fix lots of issues
- initial gk20a support
- gk110b support
- gk208 fixes
exynos:
probe order fixes, HDMI changes, IPP consolidation
msm:
debugfs updates, misc fixes
ast:
ast2400 support, sync with UMS driver
tegra:
cleanups, hdmi + hw cursor for Tegra 124.
panel:
fixes existing panels add some new ones.
ipuv3:
moved from staging to drivers/gpu"
* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (761 commits)
drm/nouveau/disp/dp: fix tmds passthrough on dp connector
drm/nouveau/dp: probe dpcd to determine connectedness
drm/nv50-: trigger update after all connectors disabled
drm/nv50-: prepare for attaching a SOR to multiple heads
drm/gf119-/disp: fix debug output on update failure
drm/nouveau/disp/dp: make use of postcursor when its available
drm/g94-/disp/dp: take max pullup value across all lanes
drm/nouveau/bios/dp: parse lane postcursor data
drm/nouveau/dp: fix support for dpms
drm/nouveau: register a drm_dp_aux channel for each dp connector
drm/g94-/disp: add method to power-off dp lanes
drm/nouveau/disp/dp: maintain link in response to hpd signal
drm/g94-/disp: bash and wait for something after changing lane power regs
drm/nouveau/disp/dp: split link config/power into two steps
drm/nv50/disp: train PIOR-attached DP from second supervisor
drm/nouveau/disp/dp: make use of existing output data for link training
drm/gf119/disp: start removing direct vbios parsing from supervisor
drm/nv50/disp: start removing direct vbios parsing from supervisor
drm/nouveau/disp/dp: maintain receiver caps in response to hpd signal
drm/nouveau/disp/dp: create subclass for dp outputs
...
348 lines
11 KiB
C
348 lines
11 KiB
C
/*
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* Copyright 2005-2009 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU Lesser General
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* Public License. You may obtain a copy of the GNU Lesser General
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* Public License Version 2.1 or later at the following locations:
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*
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* http://www.opensource.org/licenses/lgpl-license.html
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* http://www.gnu.org/copyleft/lgpl.html
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*/
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#ifndef __DRM_IPU_H__
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#define __DRM_IPU_H__
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#include <linux/types.h>
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#include <linux/videodev2.h>
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#include <linux/bitmap.h>
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#include <linux/fb.h>
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struct ipu_soc;
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enum ipuv3_type {
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IPUV3EX,
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IPUV3M,
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IPUV3H,
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};
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#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
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/*
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* Bitfield of Display Interface signal polarities.
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*/
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struct ipu_di_signal_cfg {
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unsigned datamask_en:1;
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unsigned interlaced:1;
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unsigned odd_field_first:1;
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unsigned clksel_en:1;
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unsigned clkidle_en:1;
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unsigned data_pol:1; /* true = inverted */
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unsigned clk_pol:1; /* true = rising edge */
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unsigned enable_pol:1;
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unsigned Hsync_pol:1; /* true = active high */
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unsigned Vsync_pol:1;
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u16 width;
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u16 height;
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u32 pixel_fmt;
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u16 h_start_width;
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u16 h_sync_width;
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u16 h_end_width;
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u16 v_start_width;
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u16 v_sync_width;
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u16 v_end_width;
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u32 v_to_h_sync;
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unsigned long pixelclock;
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#define IPU_DI_CLKMODE_SYNC (1 << 0)
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#define IPU_DI_CLKMODE_EXT (1 << 1)
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unsigned long clkflags;
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u8 hsync_pin;
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u8 vsync_pin;
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};
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enum ipu_color_space {
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IPUV3_COLORSPACE_RGB,
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IPUV3_COLORSPACE_YUV,
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IPUV3_COLORSPACE_UNKNOWN,
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};
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struct ipuv3_channel;
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enum ipu_channel_irq {
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IPU_IRQ_EOF = 0,
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IPU_IRQ_NFACK = 64,
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IPU_IRQ_NFB4EOF = 128,
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IPU_IRQ_EOS = 192,
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};
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int ipu_map_irq(struct ipu_soc *ipu, int irq);
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int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
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enum ipu_channel_irq irq);
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#define IPU_IRQ_DP_SF_START (448 + 2)
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#define IPU_IRQ_DP_SF_END (448 + 3)
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#define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
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#define IPU_IRQ_DC_FC_0 (448 + 8)
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#define IPU_IRQ_DC_FC_1 (448 + 9)
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#define IPU_IRQ_DC_FC_2 (448 + 10)
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#define IPU_IRQ_DC_FC_3 (448 + 11)
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#define IPU_IRQ_DC_FC_4 (448 + 12)
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#define IPU_IRQ_DC_FC_6 (448 + 13)
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#define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
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#define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
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/*
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* IPU Image DMA Controller (idmac) functions
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*/
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struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
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void ipu_idmac_put(struct ipuv3_channel *);
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int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
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int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
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int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
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void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
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bool doublebuffer);
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int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
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void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
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/*
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* IPU Display Controller (dc) functions
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*/
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struct ipu_dc;
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struct ipu_di;
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struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
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void ipu_dc_put(struct ipu_dc *dc);
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int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
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u32 pixel_fmt, u32 width);
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void ipu_dc_enable(struct ipu_soc *ipu);
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void ipu_dc_enable_channel(struct ipu_dc *dc);
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void ipu_dc_disable_channel(struct ipu_dc *dc);
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void ipu_dc_disable(struct ipu_soc *ipu);
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/*
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* IPU Display Interface (di) functions
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*/
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struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
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void ipu_di_put(struct ipu_di *);
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int ipu_di_disable(struct ipu_di *);
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int ipu_di_enable(struct ipu_di *);
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int ipu_di_get_num(struct ipu_di *);
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int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
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/*
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* IPU Display Multi FIFO Controller (dmfc) functions
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*/
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struct dmfc_channel;
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int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
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void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
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int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
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unsigned long bandwidth_mbs, int burstsize);
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void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc);
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int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width);
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struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
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void ipu_dmfc_put(struct dmfc_channel *dmfc);
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/*
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* IPU Display Processor (dp) functions
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*/
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#define IPU_DP_FLOW_SYNC_BG 0
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#define IPU_DP_FLOW_SYNC_FG 1
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#define IPU_DP_FLOW_ASYNC0_BG 2
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#define IPU_DP_FLOW_ASYNC0_FG 3
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#define IPU_DP_FLOW_ASYNC1_BG 4
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#define IPU_DP_FLOW_ASYNC1_FG 5
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struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
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void ipu_dp_put(struct ipu_dp *);
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int ipu_dp_enable(struct ipu_soc *ipu);
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int ipu_dp_enable_channel(struct ipu_dp *dp);
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void ipu_dp_disable_channel(struct ipu_dp *dp);
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void ipu_dp_disable(struct ipu_soc *ipu);
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int ipu_dp_setup_channel(struct ipu_dp *dp,
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enum ipu_color_space in, enum ipu_color_space out);
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int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
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int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
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bool bg_chan);
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/*
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* IPU CMOS Sensor Interface (csi) functions
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*/
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int ipu_csi_enable(struct ipu_soc *ipu, int csi);
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int ipu_csi_disable(struct ipu_soc *ipu, int csi);
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/*
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* IPU Sensor Multiple FIFO Controller (SMFC) functions
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*/
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int ipu_smfc_enable(struct ipu_soc *ipu);
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int ipu_smfc_disable(struct ipu_soc *ipu);
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int ipu_smfc_map_channel(struct ipu_soc *ipu, int channel, int csi_id, int mipi_id);
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int ipu_smfc_set_burstsize(struct ipu_soc *ipu, int channel, int burstsize);
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#define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size))
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#define IPU_FIELD_UBO IPU_CPMEM_WORD(0, 46, 22)
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#define IPU_FIELD_VBO IPU_CPMEM_WORD(0, 68, 22)
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#define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4)
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#define IPU_FIELD_RDRW IPU_CPMEM_WORD(0, 94, 1)
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#define IPU_FIELD_SO IPU_CPMEM_WORD(0, 113, 1)
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#define IPU_FIELD_SLY IPU_CPMEM_WORD(1, 102, 14)
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#define IPU_FIELD_SLUV IPU_CPMEM_WORD(1, 128, 14)
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#define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10)
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#define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 9)
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#define IPU_FIELD_XB IPU_CPMEM_WORD(0, 19, 13)
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#define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12)
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#define IPU_FIELD_NSB_B IPU_CPMEM_WORD(0, 44, 1)
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#define IPU_FIELD_CF IPU_CPMEM_WORD(0, 45, 1)
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#define IPU_FIELD_SX IPU_CPMEM_WORD(0, 46, 12)
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#define IPU_FIELD_SY IPU_CPMEM_WORD(0, 58, 11)
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#define IPU_FIELD_NS IPU_CPMEM_WORD(0, 69, 10)
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#define IPU_FIELD_SDX IPU_CPMEM_WORD(0, 79, 7)
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#define IPU_FIELD_SM IPU_CPMEM_WORD(0, 86, 10)
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#define IPU_FIELD_SCC IPU_CPMEM_WORD(0, 96, 1)
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#define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 97, 1)
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#define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 7)
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#define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 105, 1)
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#define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 106, 1)
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#define IPU_FIELD_BPP IPU_CPMEM_WORD(0, 107, 3)
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#define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(0, 110, 2)
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#define IPU_FIELD_DIM IPU_CPMEM_WORD(0, 112, 1)
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#define IPU_FIELD_BNDM IPU_CPMEM_WORD(0, 114, 3)
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#define IPU_FIELD_BM IPU_CPMEM_WORD(0, 117, 2)
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#define IPU_FIELD_ROT IPU_CPMEM_WORD(0, 119, 1)
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#define IPU_FIELD_HF IPU_CPMEM_WORD(0, 120, 1)
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#define IPU_FIELD_VF IPU_CPMEM_WORD(0, 121, 1)
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#define IPU_FIELD_THE IPU_CPMEM_WORD(0, 122, 1)
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#define IPU_FIELD_CAP IPU_CPMEM_WORD(0, 123, 1)
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#define IPU_FIELD_CAE IPU_CPMEM_WORD(0, 124, 1)
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#define IPU_FIELD_FW IPU_CPMEM_WORD(0, 125, 13)
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#define IPU_FIELD_FH IPU_CPMEM_WORD(0, 138, 12)
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#define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 29)
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#define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 29, 29)
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#define IPU_FIELD_ILO IPU_CPMEM_WORD(1, 58, 20)
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#define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 78, 7)
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#define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4)
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#define IPU_FIELD_ALU IPU_CPMEM_WORD(1, 89, 1)
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#define IPU_FIELD_ALBM IPU_CPMEM_WORD(1, 90, 3)
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#define IPU_FIELD_ID IPU_CPMEM_WORD(1, 93, 2)
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#define IPU_FIELD_TH IPU_CPMEM_WORD(1, 95, 7)
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#define IPU_FIELD_SL IPU_CPMEM_WORD(1, 102, 14)
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#define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 116, 3)
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#define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 119, 3)
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#define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 122, 3)
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#define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 125, 3)
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#define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 128, 5)
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#define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 133, 5)
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#define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 138, 5)
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#define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 143, 5)
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#define IPU_FIELD_SXYS IPU_CPMEM_WORD(1, 148, 1)
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#define IPU_FIELD_CRE IPU_CPMEM_WORD(1, 149, 1)
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#define IPU_FIELD_DEC_SEL2 IPU_CPMEM_WORD(1, 150, 1)
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struct ipu_cpmem_word {
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u32 data[5];
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u32 res[3];
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};
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struct ipu_ch_param {
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struct ipu_cpmem_word word[2];
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};
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void ipu_ch_param_write_field(struct ipu_ch_param __iomem *base, u32 wbs, u32 v);
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u32 ipu_ch_param_read_field(struct ipu_ch_param __iomem *base, u32 wbs);
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struct ipu_ch_param __iomem *ipu_get_cpmem(struct ipuv3_channel *channel);
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void ipu_ch_param_dump(struct ipu_ch_param __iomem *p);
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static inline void ipu_ch_param_zero(struct ipu_ch_param __iomem *p)
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{
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int i;
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void __iomem *base = p;
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for (i = 0; i < sizeof(*p) / sizeof(u32); i++)
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writel(0, base + i * sizeof(u32));
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}
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static inline void ipu_cpmem_set_buffer(struct ipu_ch_param __iomem *p,
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int bufnum, dma_addr_t buf)
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{
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if (bufnum)
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ipu_ch_param_write_field(p, IPU_FIELD_EBA1, buf >> 3);
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else
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ipu_ch_param_write_field(p, IPU_FIELD_EBA0, buf >> 3);
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}
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static inline void ipu_cpmem_set_resolution(struct ipu_ch_param __iomem *p,
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int xres, int yres)
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{
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ipu_ch_param_write_field(p, IPU_FIELD_FW, xres - 1);
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ipu_ch_param_write_field(p, IPU_FIELD_FH, yres - 1);
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}
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static inline void ipu_cpmem_set_stride(struct ipu_ch_param __iomem *p,
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int stride)
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{
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ipu_ch_param_write_field(p, IPU_FIELD_SLY, stride - 1);
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}
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void ipu_cpmem_set_high_priority(struct ipuv3_channel *channel);
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struct ipu_rgb {
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struct fb_bitfield red;
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struct fb_bitfield green;
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struct fb_bitfield blue;
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struct fb_bitfield transp;
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int bits_per_pixel;
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};
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struct ipu_image {
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struct v4l2_pix_format pix;
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struct v4l2_rect rect;
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dma_addr_t phys;
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};
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int ipu_cpmem_set_format_passthrough(struct ipu_ch_param __iomem *p,
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int width);
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int ipu_cpmem_set_format_rgb(struct ipu_ch_param __iomem *,
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const struct ipu_rgb *rgb);
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static inline void ipu_cpmem_interlaced_scan(struct ipu_ch_param *p,
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int stride)
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{
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ipu_ch_param_write_field(p, IPU_FIELD_SO, 1);
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ipu_ch_param_write_field(p, IPU_FIELD_ILO, stride / 8);
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ipu_ch_param_write_field(p, IPU_FIELD_SLY, (stride * 2) - 1);
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};
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void ipu_cpmem_set_yuv_planar(struct ipu_ch_param __iomem *p, u32 pixel_format,
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int stride, int height);
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void ipu_cpmem_set_yuv_interleaved(struct ipu_ch_param __iomem *p,
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u32 pixel_format);
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void ipu_cpmem_set_yuv_planar_full(struct ipu_ch_param __iomem *p,
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u32 pixel_format, int stride, int u_offset, int v_offset);
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int ipu_cpmem_set_fmt(struct ipu_ch_param __iomem *cpmem, u32 pixelformat);
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int ipu_cpmem_set_image(struct ipu_ch_param __iomem *cpmem,
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struct ipu_image *image);
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enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
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enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
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static inline void ipu_cpmem_set_burstsize(struct ipu_ch_param __iomem *p,
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int burstsize)
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{
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ipu_ch_param_write_field(p, IPU_FIELD_NPB, burstsize - 1);
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};
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struct ipu_client_platformdata {
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int csi;
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int di;
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int dc;
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int dp;
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int dmfc;
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int dma[2];
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};
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#endif /* __DRM_IPU_H__ */
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