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The driver is for amplifiers aw88081 of Awinic Technology Corporation. The awinic AW88081 is an I2S/TDM input, high efficiency digital Smart K audio amplifier Signed-off-by: Weidong Wang <wangweidong.a@awinic.com> Reviewed-by: anish kumar <yesanishhere@gmail.com> Link: https://patch.msgid.link/20241024090324.131731-3-wangweidong.a@awinic.com Signed-off-by: Mark Brown <broonie@kernel.org>
287 lines
8.4 KiB
C
287 lines
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// aw88081.h -- AW88081 ALSA SoC Audio driver
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//
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// Copyright (c) 2024 awinic Technology CO., LTD
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//
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// Author: Weidong Wang <wangweidong.a@awinic.com>
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//
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#ifndef __AW88081_H__
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#define __AW88081_H__
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#define AW88081_ID_REG (0x00)
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#define AW88081_SYSST_REG (0x01)
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#define AW88081_SYSINT_REG (0x02)
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#define AW88081_SYSINTM_REG (0x03)
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#define AW88081_SYSCTRL_REG (0x04)
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#define AW88081_SYSCTRL2_REG (0x05)
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#define AW88081_I2SCTRL1_REG (0x06)
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#define AW88081_I2SCTRL2_REG (0x07)
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#define AW88081_I2SCTRL3_REG (0x08)
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#define AW88081_DACCFG1_REG (0x09)
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#define AW88081_DACCFG2_REG (0x0A)
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#define AW88081_DACCFG3_REG (0x0B)
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#define AW88081_DACCFG4_REG (0x0C)
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#define AW88081_DACCFG5_REG (0x0D)
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#define AW88081_DACCFG6_REG (0x0E)
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#define AW88081_DACCFG7_REG (0x11)
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#define AW88081_PWMCTRL1_REG (0x13)
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#define AW88081_PWMCTRL2_REG (0x14)
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#define AW88081_PWMCTRL3_REG (0x15)
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#define AW88081_PWMCTRL4_REG (0x16)
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#define AW88081_I2SCFG1_REG (0x17)
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#define AW88081_DBGCTRL_REG (0x18)
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#define AW88081_PDMCTRL_REG (0x19)
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#define AW88081_DACST_REG (0x20)
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#define AW88081_PATTERNST_REG (0x21)
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#define AW88081_I2SINT_REG (0x26)
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#define AW88081_I2SCAPCNT_REG (0x27)
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#define AW88081_ANASTA1_REG (0x28)
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#define AW88081_ANASTA2_REG (0x29)
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#define AW88081_ANASTA3_REG (0x2A)
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#define AW88081_VBAT_REG (0x21)
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#define AW88081_TEMP_REG (0x22)
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#define AW88081_PVDD_REG (0x23)
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#define AW88081_ISNDAT_REG (0x24)
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#define AW88081_VSNDAT_REG (0x25)
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#define AW88081_DSMCFG1_REG (0x30)
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#define AW88081_DSMCFG2_REG (0x31)
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#define AW88081_DSMCFG3_REG (0x32)
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#define AW88081_DSMCFG4_REG (0x33)
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#define AW88081_DSMCFG5_REG (0x34)
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#define AW88081_DSMCFG6_REG (0x35)
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#define AW88081_DSMCFG7_REG (0x36)
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#define AW88081_DSMCFG8_REG (0x37)
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#define AW88081_TESTIN_REG (0x38)
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#define AW88081_TESTOUT_REG (0x39)
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#define AW88081_BOPCTRL1_REG (0x40)
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#define AW88081_BOPCTRL2_REG (0x41)
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#define AW88081_BOPCTRL3_REG (0x42)
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#define AW88081_BOPSTA_REG (0x43)
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#define AW88081_PLLCTRL1_REG (0x54)
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#define AW88081_PLLCTRL2_REG (0x55)
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#define AW88081_PLLCTRL3_REG (0x56)
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#define AW88081_CDACTRL1_REG (0x57)
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#define AW88081_CDACTRL2_REG (0x58)
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#define AW88081_CDACTRL3_REG (0x59)
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#define AW88081_DITHERCFG1_REG (0x5A)
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#define AW88081_DITHERCFG2_REG (0x5B)
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#define AW88081_DITHERCFG3_REG (0x5C)
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#define AW88081_TM_REG (0x6E)
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#define AW88081_TM2_REG (0x6F)
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#define AW88081_TESTCTRL1_REG (0x70)
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#define AW88081_TESTCTRL2_REG (0x71)
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#define AW88081_REG_MAX (0x72)
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#define AW88081_UVLS_START_BIT (14)
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#define AW88081_UVLS_UVLO (1)
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#define AW88081_UVLS_UVLO_VALUE \
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(AW88081_UVLS_UVLO << AW88081_UVLS_START_BIT)
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#define AW88081_SWS_START_BIT (8)
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#define AW88081_SWS_SWITCHING (1)
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#define AW88081_SWS_SWITCHING_VALUE \
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(AW88081_SWS_SWITCHING << AW88081_SWS_START_BIT)
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#define AW88081_NOCLKS_START_BIT (5)
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#define AW88081_NOCLKS_NO_CLOCK (1)
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#define AW88081_NOCLKS_NO_CLOCK_VALUE \
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(AW88081_NOCLKS_NO_CLOCK << AW88081_NOCLKS_START_BIT)
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#define AW88081_CLKS_START_BIT (4)
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#define AW88081_CLKS_STABLE (1)
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#define AW88081_CLKS_STABLE_VALUE \
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(AW88081_CLKS_STABLE << AW88081_CLKS_START_BIT)
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#define AW88081_OCDS_START_BIT (3)
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#define AW88081_OCDS_OC (1)
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#define AW88081_OCDS_OC_VALUE \
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(AW88081_OCDS_OC << AW88081_OCDS_START_BIT)
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#define AW88081_OTHS_START_BIT (1)
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#define AW88081_OTHS_OT (1)
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#define AW88081_OTHS_OT_VALUE \
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(AW88081_OTHS_OT << AW88081_OTHS_START_BIT)
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#define AW88081_PLLS_START_BIT (0)
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#define AW88081_PLLS_LOCKED (1)
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#define AW88081_PLLS_LOCKED_VALUE \
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(AW88081_PLLS_LOCKED << AW88081_PLLS_START_BIT)
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#define AW88081_BIT_PLL_CHECK \
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(AW88081_CLKS_STABLE_VALUE | \
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AW88081_PLLS_LOCKED_VALUE)
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#define AW88081_BIT_SYSST_CHECK_MASK \
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(~(AW88081_UVLS_UVLO_VALUE | \
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AW88081_SWS_SWITCHING_VALUE | \
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AW88081_NOCLKS_NO_CLOCK_VALUE | \
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AW88081_CLKS_STABLE_VALUE | \
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AW88081_OCDS_OC_VALUE | \
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AW88081_OTHS_OT_VALUE | \
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AW88081_PLLS_LOCKED_VALUE))
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#define AW88081_NO_SWS_SYSST_CHECK \
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(AW88081_CLKS_STABLE_VALUE | \
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AW88081_PLLS_LOCKED_VALUE)
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#define AW88081_SWS_SYSST_CHECK \
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(AW88081_SWS_SWITCHING_VALUE | \
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AW88081_CLKS_STABLE_VALUE | \
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AW88081_PLLS_LOCKED_VALUE)
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#define AW88081_ULS_HMUTE_START_BIT (14)
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#define AW88081_ULS_HMUTE_BITS_LEN (1)
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#define AW88081_ULS_HMUTE_MASK \
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(~(((1<<AW88081_ULS_HMUTE_BITS_LEN)-1) << AW88081_ULS_HMUTE_START_BIT))
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#define AW88081_ULS_HMUTE_DISABLE (0)
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#define AW88081_ULS_HMUTE_DISABLE_VALUE \
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(AW88081_ULS_HMUTE_DISABLE << AW88081_ULS_HMUTE_START_BIT)
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#define AW88081_ULS_HMUTE_ENABLE (1)
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#define AW88081_ULS_HMUTE_ENABLE_VALUE \
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(AW88081_ULS_HMUTE_ENABLE << AW88081_ULS_HMUTE_START_BIT)
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#define AW88081_HMUTE_START_BIT (8)
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#define AW88081_HMUTE_BITS_LEN (1)
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#define AW88081_HMUTE_MASK \
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(~(((1<<AW88081_HMUTE_BITS_LEN)-1) << AW88081_HMUTE_START_BIT))
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#define AW88081_HMUTE_DISABLE (0)
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#define AW88081_HMUTE_DISABLE_VALUE \
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(AW88081_HMUTE_DISABLE << AW88081_HMUTE_START_BIT)
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#define AW88081_HMUTE_ENABLE (1)
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#define AW88081_HMUTE_ENABLE_VALUE \
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(AW88081_HMUTE_ENABLE << AW88081_HMUTE_START_BIT)
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#define AW88081_EN_PA_START_BIT (1)
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#define AW88081_EN_PA_BITS_LEN (1)
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#define AW88081_EN_PA_MASK \
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(~(((1<<AW88081_EN_PA_BITS_LEN)-1) << AW88081_EN_PA_START_BIT))
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#define AW88081_EN_PA_WORKING (1)
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#define AW88081_EN_PA_WORKING_VALUE \
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(AW88081_EN_PA_WORKING << AW88081_EN_PA_START_BIT)
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#define AW88081_EN_PA_POWER_DOWN (0)
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#define AW88081_EN_PA_POWER_DOWN_VALUE \
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(AW88081_EN_PA_POWER_DOWN << AW88081_EN_PA_START_BIT)
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#define AW88081_PWDN_START_BIT (0)
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#define AW88081_PWDN_BITS_LEN (1)
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#define AW88081_PWDN_MASK \
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(~(((1<<AW88081_PWDN_BITS_LEN)-1) << AW88081_PWDN_START_BIT))
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#define AW88081_PWDN_WORKING (0)
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#define AW88081_PWDN_WORKING_VALUE \
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(AW88081_PWDN_WORKING << AW88081_PWDN_START_BIT)
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#define AW88081_PWDN_POWER_DOWN (1)
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#define AW88081_PWDN_POWER_DOWN_VALUE \
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(AW88081_PWDN_POWER_DOWN << AW88081_PWDN_START_BIT)
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#define AW88081_VOL_START_BIT (0)
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#define AW88081_VOL_BITS_LEN (10)
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#define AW88081_VOL_MASK \
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(~(((1<<AW88081_VOL_BITS_LEN)-1) << AW88081_VOL_START_BIT))
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#define AW88081_VOLUME_STEP_DB (64)
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#define AW88081_MUTE_VOL (1023)
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#define AW88081_I2STXEN_START_BIT (6)
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#define AW88081_I2STXEN_BITS_LEN (1)
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#define AW88081_I2STXEN_MASK \
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(~(((1<<AW88081_I2STXEN_BITS_LEN)-1) << AW88081_I2STXEN_START_BIT))
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#define AW88081_I2STXEN_DISABLE (0)
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#define AW88081_I2STXEN_DISABLE_VALUE \
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(AW88081_I2STXEN_DISABLE << AW88081_I2STXEN_START_BIT)
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#define AW88081_I2STXEN_ENABLE (1)
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#define AW88081_I2STXEN_ENABLE_VALUE \
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(AW88081_I2STXEN_ENABLE << AW88081_I2STXEN_START_BIT)
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#define AW88081_NOISE_GATE_EN_START_BIT (13)
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#define AW88081_NOISE_GATE_EN_BITS_LEN (1)
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#define AW88081_NOISE_GATE_EN_MASK \
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(~(((1<<AW88081_NOISE_GATE_EN_BITS_LEN)-1) << AW88081_NOISE_GATE_EN_START_BIT))
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#define AW88081_NOISE_GATE_EN_DISABLE (0)
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#define AW88081_NOISE_GATE_EN_DISABLE_VALUE \
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(AW88081_NOISE_GATE_EN_DISABLE << AW88081_NOISE_GATE_EN_START_BIT)
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#define AW88081_NOISE_GATE_EN_ENABLE (1)
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#define AW88081_NOISE_GATE_EN_ENABLE_VALUE \
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(AW88081_NOISE_GATE_EN_ENABLE << AW88081_NOISE_GATE_EN_START_BIT)
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#define AW88081_CCO_MUX_START_BIT (13)
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#define AW88081_CCO_MUX_BITS_LEN (1)
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#define AW88081_CCO_MUX_MASK \
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(~(((1<<AW88081_CCO_MUX_BITS_LEN)-1) << AW88081_CCO_MUX_START_BIT))
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#define AW88081_CCO_MUX_DIVIDED (0)
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#define AW88081_CCO_MUX_DIVIDED_VALUE \
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(AW88081_CCO_MUX_DIVIDED << AW88081_CCO_MUX_START_BIT)
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#define AW88081_CCO_MUX_BYPASS (1)
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#define AW88081_CCO_MUX_BYPASS_VALUE \
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(AW88081_CCO_MUX_BYPASS << AW88081_CCO_MUX_START_BIT)
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#define AW88081_START_RETRIES (5)
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#define AW88081_START_WORK_DELAY_MS (0)
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#define AW88081_I2C_NAME "aw88081"
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#define AW88081_CHIP_ID 0x2116
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#define AW88081_RATES (SNDRV_PCM_RATE_8000_48000 | \
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SNDRV_PCM_RATE_96000)
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#define AW88081_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S24_LE | \
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SNDRV_PCM_FMTBIT_S32_LE)
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#define FADE_TIME_MAX 100000
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#define AW88081_DEV_DEFAULT_CH (0)
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#define AW88081_ACF_FILE "aw88081_acf.bin"
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#define AW88081_DEV_SYSST_CHECK_MAX (10)
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#define AW88081_SOFT_RESET_VALUE (0x55aa)
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#define AW88081_INIT_PROFILE (0)
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#define AW88081_PROFILE_EXT(xname, profile_info, profile_get, profile_set) \
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{ \
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.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
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.name = xname, \
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.info = profile_info, \
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.get = profile_get, \
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.put = profile_set, \
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}
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enum {
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AW88081_SYNC_START = 0,
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AW88081_ASYNC_START,
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};
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enum {
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AW88081_500_US = 500,
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AW88081_1000_US = 1000,
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AW88081_2000_US = 2000,
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AW88081_5000_US = 5000,
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};
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enum {
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AW88081_DEV_PW_OFF = 0,
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AW88081_DEV_PW_ON,
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};
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enum {
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AW88081_DEV_FW_FAILED = 0,
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AW88081_DEV_FW_OK,
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};
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#endif
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