mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-11 04:18:39 +08:00
6c17c7d593
PCI ATS has a global Smallest Translation Unit field that is located in the PF but shared by all of the VFs. The expectation is that the STU will be set to the root port's global STU capability which is driven by the IO page table configuration of the iommu HW. Today it becomes set when the iommu driver first enables ATS. Thus, to enable ATS on the VF, the PF must have already had the correct STU programmed, even if ATS is off on the PF. Unfortunately the PF only programs the STU when the PF enables ATS. The iommu drivers tend to leave ATS disabled when IDENTITY translation is being used. Thus we can get into a state where the PF is setup to use IDENTITY with the DMA API while the VF would like to use VFIO with a PAGING domain and have ATS turned on. This fails because the PF never loaded a PAGING domain and so it never setup the STU, and the VF can't do it. The simplest solution is to have the iommu driver set the ATS STU when it probes the device. This way the ATS STU is loaded immediately at boot time to all PFs and there is no issue when a VF comes to use it. Add a new call pci_prepare_ats() which should be called by iommu drivers in their probe_device() op for every PCI device if the iommu driver supports ATS. This will setup the STU based on whatever page size capability the iommu HW has. Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Link: https://lore.kernel.org/r/0-v1-0fb4d2ab6770+7e706-ats_vf_jgg@nvidia.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
56 lines
1.9 KiB
C
56 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
#ifndef LINUX_PCI_ATS_H
|
|
#define LINUX_PCI_ATS_H
|
|
|
|
#include <linux/pci.h>
|
|
|
|
#ifdef CONFIG_PCI_ATS
|
|
/* Address Translation Service */
|
|
bool pci_ats_supported(struct pci_dev *dev);
|
|
int pci_enable_ats(struct pci_dev *dev, int ps);
|
|
int pci_prepare_ats(struct pci_dev *dev, int ps);
|
|
void pci_disable_ats(struct pci_dev *dev);
|
|
int pci_ats_queue_depth(struct pci_dev *dev);
|
|
int pci_ats_page_aligned(struct pci_dev *dev);
|
|
#else /* CONFIG_PCI_ATS */
|
|
static inline bool pci_ats_supported(struct pci_dev *d)
|
|
{ return false; }
|
|
static inline int pci_enable_ats(struct pci_dev *d, int ps)
|
|
{ return -ENODEV; }
|
|
static inline int pci_prepare_ats(struct pci_dev *dev, int ps)
|
|
{ return -ENODEV; }
|
|
static inline void pci_disable_ats(struct pci_dev *d) { }
|
|
static inline int pci_ats_queue_depth(struct pci_dev *d)
|
|
{ return -ENODEV; }
|
|
static inline int pci_ats_page_aligned(struct pci_dev *dev)
|
|
{ return 0; }
|
|
#endif /* CONFIG_PCI_ATS */
|
|
|
|
#ifdef CONFIG_PCI_PRI
|
|
int pci_enable_pri(struct pci_dev *pdev, u32 reqs);
|
|
void pci_disable_pri(struct pci_dev *pdev);
|
|
int pci_reset_pri(struct pci_dev *pdev);
|
|
int pci_prg_resp_pasid_required(struct pci_dev *pdev);
|
|
bool pci_pri_supported(struct pci_dev *pdev);
|
|
#else
|
|
static inline bool pci_pri_supported(struct pci_dev *pdev)
|
|
{ return false; }
|
|
#endif /* CONFIG_PCI_PRI */
|
|
|
|
#ifdef CONFIG_PCI_PASID
|
|
int pci_enable_pasid(struct pci_dev *pdev, int features);
|
|
void pci_disable_pasid(struct pci_dev *pdev);
|
|
int pci_pasid_features(struct pci_dev *pdev);
|
|
int pci_max_pasids(struct pci_dev *pdev);
|
|
#else /* CONFIG_PCI_PASID */
|
|
static inline int pci_enable_pasid(struct pci_dev *pdev, int features)
|
|
{ return -EINVAL; }
|
|
static inline void pci_disable_pasid(struct pci_dev *pdev) { }
|
|
static inline int pci_pasid_features(struct pci_dev *pdev)
|
|
{ return -EINVAL; }
|
|
static inline int pci_max_pasids(struct pci_dev *pdev)
|
|
{ return -EINVAL; }
|
|
#endif /* CONFIG_PCI_PASID */
|
|
|
|
#endif /* LINUX_PCI_ATS_H */
|