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4e197ee880
Add ethernet refclock mux support and set it to internal clock by
default. This configuration will not affect existing boards.
clock tree before this patch:
fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-,
|- pll6_enet
fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´
after this patch:
fec1 <- enet1_ref_sel(mux) <- enet1_ref_125m (gate) <- ...
`--<> enet1_ref_pad |- pll6_enet
fec2 <- enet2_ref_sel(mux) <- enet2_ref_125m (gate) <- ...
`--<> enet2_ref_pad
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Acked-by: Lee Jones <lee@kernel.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230131084642.709385-17-o.rempel@pengutronix.de
268 lines
8.4 KiB
C
268 lines
8.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H
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#define __DT_BINDINGS_CLOCK_IMX6UL_H
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#define IMX6UL_CLK_DUMMY 0
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#define IMX6UL_CLK_CKIL 1
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#define IMX6UL_CLK_CKIH 2
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#define IMX6UL_CLK_OSC 3
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#define IMX6UL_PLL1_BYPASS_SRC 4
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#define IMX6UL_PLL2_BYPASS_SRC 5
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#define IMX6UL_PLL3_BYPASS_SRC 6
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#define IMX6UL_PLL4_BYPASS_SRC 7
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#define IMX6UL_PLL5_BYPASS_SRC 8
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#define IMX6UL_PLL6_BYPASS_SRC 9
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#define IMX6UL_PLL7_BYPASS_SRC 10
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#define IMX6UL_CLK_PLL1 11
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#define IMX6UL_CLK_PLL2 12
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#define IMX6UL_CLK_PLL3 13
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#define IMX6UL_CLK_PLL4 14
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#define IMX6UL_CLK_PLL5 15
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#define IMX6UL_CLK_PLL6 16
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#define IMX6UL_CLK_PLL7 17
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#define IMX6UL_PLL1_BYPASS 18
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#define IMX6UL_PLL2_BYPASS 19
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#define IMX6UL_PLL3_BYPASS 20
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#define IMX6UL_PLL4_BYPASS 21
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#define IMX6UL_PLL5_BYPASS 22
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#define IMX6UL_PLL6_BYPASS 23
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#define IMX6UL_PLL7_BYPASS 24
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#define IMX6UL_CLK_PLL1_SYS 25
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#define IMX6UL_CLK_PLL2_BUS 26
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#define IMX6UL_CLK_PLL3_USB_OTG 27
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#define IMX6UL_CLK_PLL4_AUDIO 28
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#define IMX6UL_CLK_PLL5_VIDEO 29
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#define IMX6UL_CLK_PLL6_ENET 30
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#define IMX6UL_CLK_PLL7_USB_HOST 31
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#define IMX6UL_CLK_USBPHY1 32
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#define IMX6UL_CLK_USBPHY2 33
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#define IMX6UL_CLK_USBPHY1_GATE 34
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#define IMX6UL_CLK_USBPHY2_GATE 35
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#define IMX6UL_CLK_PLL2_PFD0 36
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#define IMX6UL_CLK_PLL2_PFD1 37
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#define IMX6UL_CLK_PLL2_PFD2 38
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#define IMX6UL_CLK_PLL2_PFD3 39
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#define IMX6UL_CLK_PLL3_PFD0 40
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#define IMX6UL_CLK_PLL3_PFD1 41
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#define IMX6UL_CLK_PLL3_PFD2 42
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#define IMX6UL_CLK_PLL3_PFD3 43
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#define IMX6UL_CLK_ENET_REF 44
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#define IMX6UL_CLK_ENET2_REF 45
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#define IMX6UL_CLK_ENET2_REF_125M 46
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#define IMX6UL_CLK_ENET_PTP_REF 47
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#define IMX6UL_CLK_ENET_PTP 48
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#define IMX6UL_CLK_PLL4_POST_DIV 49
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#define IMX6UL_CLK_PLL4_AUDIO_DIV 50
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#define IMX6UL_CLK_PLL5_POST_DIV 51
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#define IMX6UL_CLK_PLL5_VIDEO_DIV 52
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#define IMX6UL_CLK_PLL2_198M 53
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#define IMX6UL_CLK_PLL3_80M 54
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#define IMX6UL_CLK_PLL3_60M 55
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#define IMX6UL_CLK_STEP 56
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#define IMX6UL_CLK_PLL1_SW 57
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#define IMX6UL_CLK_AXI_ALT_SEL 58
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#define IMX6UL_CLK_AXI_SEL 59
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#define IMX6UL_CLK_PERIPH_PRE 60
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#define IMX6UL_CLK_PERIPH2_PRE 61
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#define IMX6UL_CLK_PERIPH_CLK2_SEL 62
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#define IMX6UL_CLK_PERIPH2_CLK2_SEL 63
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#define IMX6UL_CLK_USDHC1_SEL 64
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#define IMX6UL_CLK_USDHC2_SEL 65
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#define IMX6UL_CLK_BCH_SEL 66
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#define IMX6UL_CLK_GPMI_SEL 67
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#define IMX6UL_CLK_EIM_SLOW_SEL 68
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#define IMX6UL_CLK_SPDIF_SEL 69
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#define IMX6UL_CLK_SAI1_SEL 70
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#define IMX6UL_CLK_SAI2_SEL 71
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#define IMX6UL_CLK_SAI3_SEL 72
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#define IMX6UL_CLK_LCDIF_PRE_SEL 73
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#define IMX6UL_CLK_SIM_PRE_SEL 74
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#define IMX6UL_CLK_LDB_DI0_SEL 75
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#define IMX6UL_CLK_LDB_DI1_SEL 76
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#define IMX6UL_CLK_ENFC_SEL 77
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#define IMX6UL_CLK_CAN_SEL 78
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#define IMX6UL_CLK_ECSPI_SEL 79
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#define IMX6UL_CLK_UART_SEL 80
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#define IMX6UL_CLK_QSPI1_SEL 81
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#define IMX6UL_CLK_PERCLK_SEL 82
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#define IMX6UL_CLK_LCDIF_SEL 83
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#define IMX6UL_CLK_SIM_SEL 84
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#define IMX6UL_CLK_PERIPH 85
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#define IMX6UL_CLK_PERIPH2 86
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#define IMX6UL_CLK_LDB_DI0_DIV_3_5 87
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#define IMX6UL_CLK_LDB_DI0_DIV_7 88
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#define IMX6UL_CLK_LDB_DI1_DIV_3_5 89
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#define IMX6UL_CLK_LDB_DI1_DIV_7 90
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#define IMX6UL_CLK_LDB_DI0_DIV_SEL 91
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#define IMX6UL_CLK_LDB_DI1_DIV_SEL 92
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#define IMX6UL_CLK_ARM 93
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#define IMX6UL_CLK_PERIPH_CLK2 94
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#define IMX6UL_CLK_PERIPH2_CLK2 95
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#define IMX6UL_CLK_AHB 96
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#define IMX6UL_CLK_MMDC_PODF 97
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#define IMX6UL_CLK_AXI_PODF 98
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#define IMX6UL_CLK_PERCLK 99
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#define IMX6UL_CLK_IPG 100
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#define IMX6UL_CLK_USDHC1_PODF 101
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#define IMX6UL_CLK_USDHC2_PODF 102
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#define IMX6UL_CLK_BCH_PODF 103
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#define IMX6UL_CLK_GPMI_PODF 104
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#define IMX6UL_CLK_EIM_SLOW_PODF 105
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#define IMX6UL_CLK_SPDIF_PRED 106
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#define IMX6UL_CLK_SPDIF_PODF 107
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#define IMX6UL_CLK_SAI1_PRED 108
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#define IMX6UL_CLK_SAI1_PODF 109
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#define IMX6UL_CLK_SAI2_PRED 110
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#define IMX6UL_CLK_SAI2_PODF 111
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#define IMX6UL_CLK_SAI3_PRED 112
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#define IMX6UL_CLK_SAI3_PODF 113
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#define IMX6UL_CLK_LCDIF_PRED 114
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#define IMX6UL_CLK_LCDIF_PODF 115
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#define IMX6UL_CLK_SIM_PODF 116
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#define IMX6UL_CLK_QSPI1_PDOF 117
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#define IMX6UL_CLK_ENFC_PRED 118
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#define IMX6UL_CLK_ENFC_PODF 119
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#define IMX6UL_CLK_CAN_PODF 120
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#define IMX6UL_CLK_ECSPI_PODF 121
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#define IMX6UL_CLK_UART_PODF 122
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#define IMX6UL_CLK_ADC1 123
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#define IMX6UL_CLK_ADC2 124
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#define IMX6UL_CLK_AIPSTZ1 125
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#define IMX6UL_CLK_AIPSTZ2 126
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#define IMX6UL_CLK_AIPSTZ3 127
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#define IMX6UL_CLK_APBHDMA 128
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#define IMX6UL_CLK_ASRC_IPG 129
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#define IMX6UL_CLK_ASRC_MEM 130
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#define IMX6UL_CLK_GPMI_BCH_APB 131
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#define IMX6UL_CLK_GPMI_BCH 132
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#define IMX6UL_CLK_GPMI_IO 133
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#define IMX6UL_CLK_GPMI_APB 134
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#define IMX6UL_CLK_CAAM_MEM 135
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#define IMX6UL_CLK_CAAM_ACLK 136
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#define IMX6UL_CLK_CAAM_IPG 137
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#define IMX6UL_CLK_CSI 138
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#define IMX6UL_CLK_ECSPI1 139
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#define IMX6UL_CLK_ECSPI2 140
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#define IMX6UL_CLK_ECSPI3 141
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#define IMX6UL_CLK_ECSPI4 142
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#define IMX6UL_CLK_EIM 143
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#define IMX6UL_CLK_ENET 144
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#define IMX6UL_CLK_ENET_AHB 145
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#define IMX6UL_CLK_EPIT1 146
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#define IMX6UL_CLK_EPIT2 147
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#define IMX6UL_CLK_CAN1_IPG 148
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#define IMX6UL_CLK_CAN1_SERIAL 149
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#define IMX6UL_CLK_CAN2_IPG 150
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#define IMX6UL_CLK_CAN2_SERIAL 151
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#define IMX6UL_CLK_GPT1_BUS 152
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#define IMX6UL_CLK_GPT1_SERIAL 153
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#define IMX6UL_CLK_GPT2_BUS 154
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#define IMX6UL_CLK_GPT2_SERIAL 155
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#define IMX6UL_CLK_I2C1 156
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#define IMX6UL_CLK_I2C2 157
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#define IMX6UL_CLK_I2C3 158
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#define IMX6UL_CLK_I2C4 159
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#define IMX6UL_CLK_IOMUXC 160
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#define IMX6UL_CLK_LCDIF_APB 161
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#define IMX6UL_CLK_LCDIF_PIX 162
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#define IMX6UL_CLK_MMDC_P0_FAST 163
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#define IMX6UL_CLK_MMDC_P0_IPG 164
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#define IMX6UL_CLK_OCOTP 165
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#define IMX6UL_CLK_OCRAM 166
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#define IMX6UL_CLK_PWM1 167
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#define IMX6UL_CLK_PWM2 168
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#define IMX6UL_CLK_PWM3 169
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#define IMX6UL_CLK_PWM4 170
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#define IMX6UL_CLK_PWM5 171
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#define IMX6UL_CLK_PWM6 172
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#define IMX6UL_CLK_PWM7 173
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#define IMX6UL_CLK_PWM8 174
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#define IMX6UL_CLK_PXP 175
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#define IMX6UL_CLK_QSPI 176
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#define IMX6UL_CLK_ROM 177
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#define IMX6UL_CLK_SAI1 178
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#define IMX6UL_CLK_SAI1_IPG 179
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#define IMX6UL_CLK_SAI2 180
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#define IMX6UL_CLK_SAI2_IPG 181
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#define IMX6UL_CLK_SAI3 182
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#define IMX6UL_CLK_SAI3_IPG 183
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#define IMX6UL_CLK_SDMA 184
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#define IMX6UL_CLK_SIM 185
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#define IMX6UL_CLK_SIM_S 186
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#define IMX6UL_CLK_SPBA 187
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#define IMX6UL_CLK_SPDIF 188
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#define IMX6UL_CLK_UART1_IPG 189
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#define IMX6UL_CLK_UART1_SERIAL 190
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#define IMX6UL_CLK_UART2_IPG 191
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#define IMX6UL_CLK_UART2_SERIAL 192
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#define IMX6UL_CLK_UART3_IPG 193
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#define IMX6UL_CLK_UART3_SERIAL 194
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#define IMX6UL_CLK_UART4_IPG 195
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#define IMX6UL_CLK_UART4_SERIAL 196
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#define IMX6UL_CLK_UART5_IPG 197
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#define IMX6UL_CLK_UART5_SERIAL 198
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#define IMX6UL_CLK_UART6_IPG 199
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#define IMX6UL_CLK_UART6_SERIAL 200
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#define IMX6UL_CLK_UART7_IPG 201
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#define IMX6UL_CLK_UART7_SERIAL 202
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#define IMX6UL_CLK_UART8_IPG 203
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#define IMX6UL_CLK_UART8_SERIAL 204
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#define IMX6UL_CLK_USBOH3 205
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#define IMX6UL_CLK_USDHC1 206
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#define IMX6UL_CLK_USDHC2 207
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#define IMX6UL_CLK_WDOG1 208
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#define IMX6UL_CLK_WDOG2 209
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#define IMX6UL_CLK_WDOG3 210
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#define IMX6UL_CLK_LDB_DI0 211
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#define IMX6UL_CLK_AXI 212
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#define IMX6UL_CLK_SPDIF_GCLK 213
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#define IMX6UL_CLK_GPT_3M 214
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#define IMX6UL_CLK_SIM2 215
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#define IMX6UL_CLK_SIM1 216
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#define IMX6UL_CLK_IPP_DI0 217
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#define IMX6UL_CLK_IPP_DI1 218
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#define IMX6UL_CA7_SECONDARY_SEL 219
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#define IMX6UL_CLK_PER_BCH 220
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#define IMX6UL_CLK_CSI_SEL 221
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#define IMX6UL_CLK_CSI_PODF 222
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#define IMX6UL_CLK_PLL3_120M 223
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#define IMX6UL_CLK_KPP 224
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#define IMX6ULL_CLK_ESAI_PRED 225
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#define IMX6ULL_CLK_ESAI_PODF 226
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#define IMX6ULL_CLK_ESAI_EXTAL 227
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#define IMX6ULL_CLK_ESAI_MEM 228
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#define IMX6ULL_CLK_ESAI_IPG 229
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#define IMX6ULL_CLK_DCP_CLK 230
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#define IMX6ULL_CLK_EPDC_PRE_SEL 231
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#define IMX6ULL_CLK_EPDC_SEL 232
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#define IMX6ULL_CLK_EPDC_PODF 233
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#define IMX6ULL_CLK_EPDC_ACLK 234
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#define IMX6ULL_CLK_EPDC_PIX 235
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#define IMX6ULL_CLK_ESAI_SEL 236
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#define IMX6UL_CLK_CKO1_SEL 237
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#define IMX6UL_CLK_CKO1_PODF 238
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#define IMX6UL_CLK_CKO1 239
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#define IMX6UL_CLK_CKO2_SEL 240
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#define IMX6UL_CLK_CKO2_PODF 241
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#define IMX6UL_CLK_CKO2 242
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#define IMX6UL_CLK_CKO 243
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#define IMX6UL_CLK_GPIO1 244
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#define IMX6UL_CLK_GPIO2 245
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#define IMX6UL_CLK_GPIO3 246
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#define IMX6UL_CLK_GPIO4 247
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#define IMX6UL_CLK_GPIO5 248
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#define IMX6UL_CLK_MMDC_P1_IPG 249
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#define IMX6UL_CLK_ENET1_REF_125M 250
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#define IMX6UL_CLK_ENET1_REF_SEL 251
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#define IMX6UL_CLK_ENET1_REF_PAD 252
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#define IMX6UL_CLK_ENET2_REF_SEL 253
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#define IMX6UL_CLK_ENET2_REF_PAD 254
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#define IMX6UL_CLK_END 255
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#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
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