mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-11 04:18:39 +08:00
b24413180f
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
243 lines
8.5 KiB
C
243 lines
8.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
#ifndef __HD64570_H
|
|
#define __HD64570_H
|
|
|
|
/* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
|
|
and 1 (64180 MPU). For modes 2 and 3, XOR the address with 0x01.
|
|
|
|
Source: HD64570 SCA User's Manual
|
|
*/
|
|
|
|
|
|
|
|
/* SCA Control Registers */
|
|
#define LPR 0x00 /* Low Power */
|
|
|
|
/* Wait controller registers */
|
|
#define PABR0 0x02 /* Physical Address Boundary 0 */
|
|
#define PABR1 0x03 /* Physical Address Boundary 1 */
|
|
#define WCRL 0x04 /* Wait Control L */
|
|
#define WCRM 0x05 /* Wait Control M */
|
|
#define WCRH 0x06 /* Wait Control H */
|
|
|
|
#define PCR 0x08 /* DMA Priority Control */
|
|
#define DMER 0x09 /* DMA Master Enable */
|
|
|
|
|
|
/* Interrupt registers */
|
|
#define ISR0 0x10 /* Interrupt Status 0 */
|
|
#define ISR1 0x11 /* Interrupt Status 1 */
|
|
#define ISR2 0x12 /* Interrupt Status 2 */
|
|
|
|
#define IER0 0x14 /* Interrupt Enable 0 */
|
|
#define IER1 0x15 /* Interrupt Enable 1 */
|
|
#define IER2 0x16 /* Interrupt Enable 2 */
|
|
|
|
#define ITCR 0x18 /* Interrupt Control */
|
|
#define IVR 0x1A /* Interrupt Vector */
|
|
#define IMVR 0x1C /* Interrupt Modified Vector */
|
|
|
|
|
|
|
|
/* MSCI channel (port) 0 registers - offset 0x20
|
|
MSCI channel (port) 1 registers - offset 0x40 */
|
|
|
|
#define MSCI0_OFFSET 0x20
|
|
#define MSCI1_OFFSET 0x40
|
|
|
|
#define TRBL 0x00 /* TX/RX buffer L */
|
|
#define TRBH 0x01 /* TX/RX buffer H */
|
|
#define ST0 0x02 /* Status 0 */
|
|
#define ST1 0x03 /* Status 1 */
|
|
#define ST2 0x04 /* Status 2 */
|
|
#define ST3 0x05 /* Status 3 */
|
|
#define FST 0x06 /* Frame Status */
|
|
#define IE0 0x08 /* Interrupt Enable 0 */
|
|
#define IE1 0x09 /* Interrupt Enable 1 */
|
|
#define IE2 0x0A /* Interrupt Enable 2 */
|
|
#define FIE 0x0B /* Frame Interrupt Enable */
|
|
#define CMD 0x0C /* Command */
|
|
#define MD0 0x0E /* Mode 0 */
|
|
#define MD1 0x0F /* Mode 1 */
|
|
#define MD2 0x10 /* Mode 2 */
|
|
#define CTL 0x11 /* Control */
|
|
#define SA0 0x12 /* Sync/Address 0 */
|
|
#define SA1 0x13 /* Sync/Address 1 */
|
|
#define IDL 0x14 /* Idle Pattern */
|
|
#define TMC 0x15 /* Time Constant */
|
|
#define RXS 0x16 /* RX Clock Source */
|
|
#define TXS 0x17 /* TX Clock Source */
|
|
#define TRC0 0x18 /* TX Ready Control 0 */
|
|
#define TRC1 0x19 /* TX Ready Control 1 */
|
|
#define RRC 0x1A /* RX Ready Control */
|
|
#define CST0 0x1C /* Current Status 0 */
|
|
#define CST1 0x1D /* Current Status 1 */
|
|
|
|
|
|
/* Timer channel 0 (port 0 RX) registers - offset 0x60
|
|
Timer channel 1 (port 0 TX) registers - offset 0x68
|
|
Timer channel 2 (port 1 RX) registers - offset 0x70
|
|
Timer channel 3 (port 1 TX) registers - offset 0x78
|
|
*/
|
|
|
|
#define TIMER0RX_OFFSET 0x60
|
|
#define TIMER0TX_OFFSET 0x68
|
|
#define TIMER1RX_OFFSET 0x70
|
|
#define TIMER1TX_OFFSET 0x78
|
|
|
|
#define TCNTL 0x00 /* Up-counter L */
|
|
#define TCNTH 0x01 /* Up-counter H */
|
|
#define TCONRL 0x02 /* Constant L */
|
|
#define TCONRH 0x03 /* Constant H */
|
|
#define TCSR 0x04 /* Control/Status */
|
|
#define TEPR 0x05 /* Expand Prescale */
|
|
|
|
|
|
|
|
/* DMA channel 0 (port 0 RX) registers - offset 0x80
|
|
DMA channel 1 (port 0 TX) registers - offset 0xA0
|
|
DMA channel 2 (port 1 RX) registers - offset 0xC0
|
|
DMA channel 3 (port 1 TX) registers - offset 0xE0
|
|
*/
|
|
|
|
#define DMAC0RX_OFFSET 0x80
|
|
#define DMAC0TX_OFFSET 0xA0
|
|
#define DMAC1RX_OFFSET 0xC0
|
|
#define DMAC1TX_OFFSET 0xE0
|
|
|
|
#define BARL 0x00 /* Buffer Address L (chained block) */
|
|
#define BARH 0x01 /* Buffer Address H (chained block) */
|
|
#define BARB 0x02 /* Buffer Address B (chained block) */
|
|
|
|
#define DARL 0x00 /* RX Destination Addr L (single block) */
|
|
#define DARH 0x01 /* RX Destination Addr H (single block) */
|
|
#define DARB 0x02 /* RX Destination Addr B (single block) */
|
|
|
|
#define SARL 0x04 /* TX Source Address L (single block) */
|
|
#define SARH 0x05 /* TX Source Address H (single block) */
|
|
#define SARB 0x06 /* TX Source Address B (single block) */
|
|
|
|
#define CPB 0x06 /* Chain Pointer Base (chained block) */
|
|
|
|
#define CDAL 0x08 /* Current Descriptor Addr L (chained block) */
|
|
#define CDAH 0x09 /* Current Descriptor Addr H (chained block) */
|
|
#define EDAL 0x0A /* Error Descriptor Addr L (chained block) */
|
|
#define EDAH 0x0B /* Error Descriptor Addr H (chained block) */
|
|
#define BFLL 0x0C /* RX Receive Buffer Length L (chained block)*/
|
|
#define BFLH 0x0D /* RX Receive Buffer Length H (chained block)*/
|
|
#define BCRL 0x0E /* Byte Count L */
|
|
#define BCRH 0x0F /* Byte Count H */
|
|
#define DSR 0x10 /* DMA Status */
|
|
#define DSR_RX(node) (DSR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
|
|
#define DSR_TX(node) (DSR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
|
|
#define DMR 0x11 /* DMA Mode */
|
|
#define DMR_RX(node) (DMR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
|
|
#define DMR_TX(node) (DMR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
|
|
#define FCT 0x13 /* Frame End Interrupt Counter */
|
|
#define FCT_RX(node) (FCT + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
|
|
#define FCT_TX(node) (FCT + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
|
|
#define DIR 0x14 /* DMA Interrupt Enable */
|
|
#define DIR_RX(node) (DIR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
|
|
#define DIR_TX(node) (DIR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
|
|
#define DCR 0x15 /* DMA Command */
|
|
#define DCR_RX(node) (DCR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
|
|
#define DCR_TX(node) (DCR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
|
|
|
|
|
|
|
|
|
|
/* Descriptor Structure */
|
|
|
|
typedef struct {
|
|
u16 cp; /* Chain Pointer */
|
|
u32 bp; /* Buffer Pointer (24 bits) */
|
|
u16 len; /* Data Length */
|
|
u8 stat; /* Status */
|
|
u8 unused; /* pads to 2-byte boundary */
|
|
}__packed pkt_desc;
|
|
|
|
|
|
/* Packet Descriptor Status bits */
|
|
|
|
#define ST_TX_EOM 0x80 /* End of frame */
|
|
#define ST_TX_EOT 0x01 /* End of transmission */
|
|
|
|
#define ST_RX_EOM 0x80 /* End of frame */
|
|
#define ST_RX_SHORT 0x40 /* Short frame */
|
|
#define ST_RX_ABORT 0x20 /* Abort */
|
|
#define ST_RX_RESBIT 0x10 /* Residual bit */
|
|
#define ST_RX_OVERRUN 0x08 /* Overrun */
|
|
#define ST_RX_CRC 0x04 /* CRC */
|
|
|
|
#define ST_ERROR_MASK 0x7C
|
|
|
|
#define DIR_EOTE 0x80 /* Transfer completed */
|
|
#define DIR_EOME 0x40 /* Frame Transfer Completed (chained-block) */
|
|
#define DIR_BOFE 0x20 /* Buffer Overflow/Underflow (chained-block)*/
|
|
#define DIR_COFE 0x10 /* Counter Overflow (chained-block) */
|
|
|
|
|
|
#define DSR_EOT 0x80 /* Transfer completed */
|
|
#define DSR_EOM 0x40 /* Frame Transfer Completed (chained-block) */
|
|
#define DSR_BOF 0x20 /* Buffer Overflow/Underflow (chained-block)*/
|
|
#define DSR_COF 0x10 /* Counter Overflow (chained-block) */
|
|
#define DSR_DE 0x02 /* DMA Enable */
|
|
#define DSR_DWE 0x01 /* DMA Write Disable */
|
|
|
|
/* DMA Master Enable Register (DMER) bits */
|
|
#define DMER_DME 0x80 /* DMA Master Enable */
|
|
|
|
|
|
#define CMD_RESET 0x21 /* Reset Channel */
|
|
#define CMD_TX_ENABLE 0x02 /* Start transmitter */
|
|
#define CMD_RX_ENABLE 0x12 /* Start receiver */
|
|
|
|
#define MD0_HDLC 0x80 /* Bit-sync HDLC mode */
|
|
#define MD0_CRC_ENA 0x04 /* Enable CRC code calculation */
|
|
#define MD0_CRC_CCITT 0x02 /* CCITT CRC instead of CRC-16 */
|
|
#define MD0_CRC_PR1 0x01 /* Initial all-ones instead of all-zeros */
|
|
|
|
#define MD0_CRC_NONE 0x00
|
|
#define MD0_CRC_16_0 0x04
|
|
#define MD0_CRC_16 0x05
|
|
#define MD0_CRC_ITU_0 0x06
|
|
#define MD0_CRC_ITU 0x07
|
|
|
|
#define MD2_NRZ 0x00
|
|
#define MD2_NRZI 0x20
|
|
#define MD2_MANCHESTER 0x80
|
|
#define MD2_FM_MARK 0xA0
|
|
#define MD2_FM_SPACE 0xC0
|
|
#define MD2_LOOPBACK 0x03 /* Local data Loopback */
|
|
|
|
#define CTL_NORTS 0x01
|
|
#define CTL_IDLE 0x10 /* Transmit an idle pattern */
|
|
#define CTL_UDRNC 0x20 /* Idle after CRC or FCS+flag transmission */
|
|
|
|
#define ST0_TXRDY 0x02 /* TX ready */
|
|
#define ST0_RXRDY 0x01 /* RX ready */
|
|
|
|
#define ST1_UDRN 0x80 /* MSCI TX underrun */
|
|
#define ST1_CDCD 0x04 /* DCD level changed */
|
|
|
|
#define ST3_CTS 0x08 /* modem input - /CTS */
|
|
#define ST3_DCD 0x04 /* modem input - /DCD */
|
|
|
|
#define IE0_TXINT 0x80 /* TX INT MSCI interrupt enable */
|
|
#define IE0_RXINTA 0x40 /* RX INT A MSCI interrupt enable */
|
|
#define IE1_UDRN 0x80 /* TX underrun MSCI interrupt enable */
|
|
#define IE1_CDCD 0x04 /* DCD level changed */
|
|
|
|
#define DCR_ABORT 0x01 /* Software abort command */
|
|
#define DCR_CLEAR_EOF 0x02 /* Clear EOF interrupt */
|
|
|
|
/* TX and RX Clock Source - RXS and TXS */
|
|
#define CLK_BRG_MASK 0x0F
|
|
#define CLK_LINE_RX 0x00 /* TX/RX clock line input */
|
|
#define CLK_LINE_TX 0x00 /* TX/RX line input */
|
|
#define CLK_BRG_RX 0x40 /* internal baud rate generator */
|
|
#define CLK_BRG_TX 0x40 /* internal baud rate generator */
|
|
#define CLK_RXCLK_TX 0x60 /* TX clock from RX clock */
|
|
|
|
#endif
|