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3b42450ce1
The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used
by the RTC. The input to the VBATTB could be a 32KHz crystal
or an external clock device.
The HW block diagram for the clock generator is as follows:
+----------+ XC `\
RTXIN --->| |----->| \ +----+ VBATTCLK
| 32K clock| | |----->|gate|----------->
| osc | XBYP | | +----+
RTXOUT --->| |----->| /
+----------+ ,
After discussions w/ Stephen Boyd the clock tree associated with this
hardware block was exported in Linux as:
vbattb-xtal
xbyp
xc
mux
vbattbclk
where:
- input-xtal is the input clock (connected to RTXIN, RTXOUT pins)
- xc, xbyp are mux inputs
- mux is the internal mux
- vbattclk is the gate clock that feeds in the end the RTC
to allow selecting the input of the MUX though assigned-clock DT
properties, using the already existing clock drivers and avoid adding
other DT properties. If the crystal is connected on RTXIN,
RTXOUT pins the XC will be selected as mux input. If an external clock
device is connected on RTXIN, RTXOUT pins the XBYP will be selected as
mux input.
The load capacitance of the internal crystal can be configured
with renesas,vbattb-load-nanofarads DT property.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20241101095720.2247815-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
57 lines
2.4 KiB
Makefile
57 lines
2.4 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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# SoC
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obj-$(CONFIG_CLK_EMEV2) += clk-emev2.o
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obj-$(CONFIG_CLK_RZA1) += clk-rz.o
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obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
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obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
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obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A774E1) += r8a774e1-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o
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obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o
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obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77960) += r8a7796-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77961) += r8a7796-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A779H0) += r8a779h0-cpg-mssr.o
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obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
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obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o
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obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
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obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
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obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o
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obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
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# Family
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obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
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obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o
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obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o
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obj-$(CONFIG_CLK_RCAR_GEN4_CPG) += rcar-gen4-cpg.o
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obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o
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obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o
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obj-$(CONFIG_CLK_RZV2H) += rzv2h-cpg.o
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# Generic
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obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o
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obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) += clk-mstp.o
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obj-$(CONFIG_CLK_RENESAS_DIV6) += clk-div6.o
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obj-$(CONFIG_CLK_RENESAS_VBATTB) += clk-vbattb.o
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