linux/arch/csky/kernel/head.S
Guo Ren 0c8a32eed1 csky: Add memory layout 2.5G(user):1.5G(kernel)
There are two ways for translating va to pa for csky:
 - Use TLB(Translate Lookup Buffer) and PTW (Page Table Walk)
 - Use SSEG0/1 (Simple Segment Mapping)

We use tlb mapping 0-2G and 3G-4G virtual address area and SSEG0/1
are for 2G-2.5G and 2.5G-3G translation. We could disable SSEG0
to use 2G-2.5G as TLB user mapping.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
2021-01-12 09:52:40 +08:00

43 lines
686 B
ArmAsm

/* SPDX-License-Identifier: GPL-2.0 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/page.h>
#include <abi/entry.h>
__HEAD
ENTRY(_start)
SETUP_MMU
/* set stack point */
lrw r6, init_thread_union + THREAD_SIZE
mov sp, r6
jmpi csky_start
END(_start)
#ifdef CONFIG_SMP
.align 10
ENTRY(_start_smp_secondary)
SETUP_MMU
#ifdef CONFIG_PAGE_OFFSET_80000000
lrw r6, secondary_msa1
ld.w r6, (r6, 0)
mtcr r6, cr<31, 15>
#endif
lrw r6, secondary_pgd
ld.w r6, (r6, 0)
mtcr r6, cr<28, 15>
mtcr r6, cr<29, 15>
/* set stack point */
lrw r6, secondary_stack
ld.w r6, (r6, 0)
mov sp, r6
jmpi csky_start_secondary
END(_start_smp_secondary)
#endif