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2c50a570e9
This patch was triggered by a remark from Russell that
introducing a call to the waituart (needed to fix debug prints
on the Qualcomm platforms) was dangerous because in some cases
this will involve waiting for a modem CTS (clear to send)
signal, and debug messages would maybe not work on platforms
with no modem connected to the UART port: they will just
hang waiting for the modem to assert CTS and this might never
happen.
Looking through all UART debug drivers implementing the waituart
macro I discovered that all users except two actually use this
macro to check if the UART is ready for TX, let's call this
TXRDY.
Only two debug UART drivers actually check for CTS:
- arch/arm/include/debug/8250.S
- arch/arm/include/debug/tegra.S
The former is very significant since the 8250 is possibly
the most common UART on the planet.
We have the following problem: the semantics of waituart are
ambiguous making it dangerous to introduce the macro to debug
code fixing debug prints for Qualcomm. To start to pry this
problem apart, this patch does the following:
- Convert all debug UART drivers to define two macros:
- waituartcts with the clear semantic to wait for CTS
to be asserted
- waituarttxrdy with the clear semantic to wait for the TX
capability of the UART to be ready
- When doing this take care to assign the right function to
each drivers macro, so they now do exactly the above.
- Update the three sites in the kernel invoking the waituart
macro to call waituartcts/waituarttxrdy in sequence, so that
the functional impact on the kernel should be zero.
After this we can start to change the code sites using this
code to do the right thing.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
68 lines
1.6 KiB
ArmAsm
68 lines
1.6 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/* arch/arm/include/debug/sa1100.S
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*
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* Debugging macro include header
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*
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* Copyright (C) 1994-1999 Russell King
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* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
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*/
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#define UTCR3 0x0c
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#define UTDR 0x14
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#define UTSR1 0x20
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#define UTCR3_TXE 0x00000002 /* Transmit Enable */
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#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
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#define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
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.macro addruart, rp, rv, tmp
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mrc p15, 0, \rp, c1, c0
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tst \rp, #1 @ MMU enabled?
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moveq \rp, #0x80000000 @ physical base address
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movne \rp, #0xf8000000 @ virtual address
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@ We probe for the active serial port here, coherently with
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@ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h.
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@ We assume r1 can be clobbered.
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@ see if Ser3 is active
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add \rp, \rp, #0x00050000
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ldr \rv, [\rp, #UTCR3]
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tst \rv, #UTCR3_TXE
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@ if Ser3 is inactive, then try Ser1
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addeq \rp, \rp, #(0x00010000 - 0x00050000)
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ldreq \rv, [\rp, #UTCR3]
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tsteq \rv, #UTCR3_TXE
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@ if Ser1 is inactive, then try Ser2
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addeq \rp, \rp, #(0x00030000 - 0x00010000)
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ldreq \rv, [\rp, #UTCR3]
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tsteq \rv, #UTCR3_TXE
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@ clear top bits, and generate both phys and virt addresses
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lsl \rp, \rp, #8
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lsr \rp, \rp, #8
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orr \rv, \rp, #0xf8000000 @ virtual
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orr \rp, \rp, #0x80000000 @ physical
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.endm
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.macro senduart,rd,rx
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str \rd, [\rx, #UTDR]
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.endm
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.macro waituartcts,rd,rx
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.endm
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.macro waituarttxrdy,rd,rx
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1001: ldr \rd, [\rx, #UTSR1]
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tst \rd, #UTSR1_TNF
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beq 1001b
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.endm
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.macro busyuart,rd,rx
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1001: ldr \rd, [\rx, #UTSR1]
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tst \rd, #UTSR1_TBY
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bne 1001b
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.endm
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