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Create a kernel documentation to describe how the CXL shared upstream link bandwidth is calculated. Suggested-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Acked-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20240904001316.1688225-4-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
92 lines
4.4 KiB
ReStructuredText
92 lines
4.4 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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.. include:: <isonum.txt>
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==================================
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CXL Access Coordinates Computation
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==================================
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Shared Upstream Link Calculation
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================================
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For certain CXL region construction with endpoints behind CXL switches (SW) or
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Root Ports (RP), there is the possibility of the total bandwidth for all
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the endpoints behind a switch being more than the switch upstream link.
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A similar situation can occur within the host, upstream of the root ports.
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The CXL driver performs an additional pass after all the targets have
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arrived for a region in order to recalculate the bandwidths with possible
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upstream link being a limiting factor in mind.
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The algorithm assumes the configuration is a symmetric topology as that
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maximizes performance. When asymmetric topology is detected, the calculation
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is aborted. An asymmetric topology is detected during topology walk where the
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number of RPs detected as a grandparent is not equal to the number of devices
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iterated in the same iteration loop. The assumption is made that subtle
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asymmetry in properties does not happen and all paths to EPs are equal.
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There can be multiple switches under an RP. There can be multiple RPs under
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a CXL Host Bridge (HB). There can be multiple HBs under a CXL Fixed Memory
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Window Structure (CFMWS).
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An example hierarchy:
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> CFMWS 0
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> |
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> _________|_________
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> | |
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> ACPI0017-0 ACPI0017-1
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> GP0/HB0/ACPI0016-0 GP1/HB1/ACPI0016-1
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> | | | |
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> RP0 RP1 RP2 RP3
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> | | | |
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> SW 0 SW 1 SW 2 SW 3
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> | | | | | | | |
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> EP0 EP1 EP2 EP3 EP4 EP5 EP6 EP7
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Computation for the example hierarchy:
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Min (GP0 to CPU BW,
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Min(SW 0 Upstream Link to RP0 BW,
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Min(SW0SSLBIS for SW0DSP0 (EP0), EP0 DSLBIS, EP0 Upstream Link) +
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Min(SW0SSLBIS for SW0DSP1 (EP1), EP1 DSLBIS, EP1 Upstream link)) +
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Min(SW 1 Upstream Link to RP1 BW,
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Min(SW1SSLBIS for SW1DSP0 (EP2), EP2 DSLBIS, EP2 Upstream Link) +
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Min(SW1SSLBIS for SW1DSP1 (EP3), EP3 DSLBIS, EP3 Upstream link))) +
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Min (GP1 to CPU BW,
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Min(SW 2 Upstream Link to RP2 BW,
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Min(SW2SSLBIS for SW2DSP0 (EP4), EP4 DSLBIS, EP4 Upstream Link) +
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Min(SW2SSLBIS for SW2DSP1 (EP5), EP5 DSLBIS, EP5 Upstream link)) +
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Min(SW 3 Upstream Link to RP3 BW,
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Min(SW3SSLBIS for SW3DSP0 (EP6), EP6 DSLBIS, EP6 Upstream Link) +
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Min(SW3SSLBIS for SW3DSP1 (EP7), EP7 DSLBIS, EP7 Upstream link))))
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The calculation starts at cxl_region_shared_upstream_perf_update(). A xarray
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is created to collect all the endpoint bandwidths via the
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cxl_endpoint_gather_bandwidth() function. The min() of bandwidth from the
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endpoint CDAT and the upstream link bandwidth is calculated. If the endpoint
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has a CXL switch as a parent, then min() of calculated bandwidth and the
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bandwidth from the SSLBIS for the switch downstream port that is associated
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with the endpoint is calculated. The final bandwidth is stored in a
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'struct cxl_perf_ctx' in the xarray indexed by a device pointer. If the
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endpoint is direct attached to a root port (RP), the device pointer would be an
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RP device. If the endpoint is behind a switch, the device pointer would be the
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upstream device of the parent switch.
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At the next stage, the code walks through one or more switches if they exist
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in the topology. For endpoints directly attached to RPs, this step is skipped.
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If there is another switch upstream, the code takes the min() of the current
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gathered bandwidth and the upstream link bandwidth. If there's a switch
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upstream, then the SSLBIS of the upstream switch.
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Once the topology walk reaches the RP, whether it's direct attached endpoints
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or walking through the switch(es), cxl_rp_gather_bandwidth() is called. At
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this point all the bandwidths are aggregated per each host bridge, which is
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also the index for the resulting xarray.
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The next step is to take the min() of the per host bridge bandwidth and the
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bandwidth from the Generic Port (GP). The bandwidths for the GP is retrieved
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via ACPI tables SRAT/HMAT. The min bandwidth are aggregated under the same
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ACPI0017 device to form a new xarray.
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Finally, the cxl_region_update_bandwidth() is called and the aggregated
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bandwidth from all the members of the last xarray is updated for the
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access coordinates residing in the cxl region (cxlr) context.
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