Jay Buddhabhatti 37b6748060 drivers: clk: zynqmp: update divider round rate logic ... [ Upstream commit 1fe15be1fb ] Currently zynqmp divider round rate is considering single parent and calculating rate and parent rate accordingly. But if divider clock flag is set to SET_RATE_PARENT then its not trying to traverse through all parent rate and not selecting best parent rate from that. So use common divider_round_rate() which is traversing through all clock parents and its rate and calculating proper parent rate. Fixes: 3fde0e16d0 ("drivers: clk: Add ZynqMP clock driver") Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Link: https://lore.kernel.org/r/20231129112916.23125-3-jay.buddhabhatti@amd.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>		2024-01-25 15:35:37 -08:00
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clk-gate-zynqmp.c	clk: zynqmp: replace warn_once with pr_debug for failed clock ops	2022-01-24 17:18:23 -08:00
clk-mux-zynqmp.c	drivers: clk: zynqmp: calculate closest mux rate	2024-01-25 15:35:37 -08:00
clk-zynqmp.h	clk: zynqmp: fix kernel doc	2021-08-28 21:19:02 -07:00
clkc.c	clk: Explicitly include correct DT includes	2023-07-19 13:13:16 -07:00
divider.c	drivers: clk: zynqmp: update divider round rate logic	2024-01-25 15:35:37 -08:00
Kconfig	clk: zynqmp: Drop dependency on ARCH_ZYNQMP	2021-04-07 17:26:09 -07:00
Makefile
pll.c	clk: zynqmp: pll: Remove the limit	2023-03-27 12:08:28 -07:00