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eaab31dceb
[ Upstream commit7e52b1164a
] Increase the size of temporary print buffer on stack to fix the following warnings reported by LKP. Since all the input parameters of snprintf() are under control of this driver, it is not possible to trigger and overflow here, but since the print buffer is on stack and discarded once driver probe() finishes, it is not an issue to increase it by 10 bytes and fix the warning in the process. Make it so. " drivers/clk/clk-si521xx.c: In function 'si521xx_probe': >> drivers/clk/clk-si521xx.c:318:26: warning: '%d' directive output may be truncated writing between 1 and 10 bytes into a region of size 2 [-Wformat-truncation=] snprintf(name, 6, "DIFF%d", i); ^~ drivers/clk/clk-si521xx.c:318:21: note: directive argument in the range [0, 2147483647] snprintf(name, 6, "DIFF%d", i); ^~~~~~~~ drivers/clk/clk-si521xx.c:318:3: note: 'snprintf' output between 6 and 15 bytes into a destination of size 6 snprintf(name, 6, "DIFF%d", i); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ " Fixes:edc12763a3
("clk: si521xx: Clock driver for Skyworks Si521xx I2C PCIe clock generators") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202310260412.AGASjFN4-lkp@intel.com/ Signed-off-by: Marek Vasut <marex@denx.de> Link: https://lore.kernel.org/r/20231027085840.30098-1-marex@denx.de Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
397 lines
10 KiB
C
397 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Driver for Skyworks Si521xx PCIe clock generator driver
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*
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* The following series can be supported:
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* - Si52144 - 4x DIFF
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* - Si52146 - 6x DIFF
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* - Si52147 - 9x DIFF
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* Currently tested:
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* - Si52144
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*
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* Copyright (C) 2022 Marek Vasut <marex@denx.de>
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*/
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#include <linux/bitfield.h>
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#include <linux/bitrev.h>
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#include <linux/clk-provider.h>
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#include <linux/i2c.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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/* OE1 and OE2 register */
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#define SI521XX_REG_OE(n) (((n) & 0x1) + 1)
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#define SI521XX_REG_ID 0x3
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#define SI521XX_REG_ID_PROG GENMASK(7, 4)
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#define SI521XX_REG_ID_VENDOR GENMASK(3, 0)
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#define SI521XX_REG_BC 0x4
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#define SI521XX_REG_DA 0x5
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#define SI521XX_REG_DA_AMP_SEL BIT(7)
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#define SI521XX_REG_DA_AMP_MASK GENMASK(6, 4)
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#define SI521XX_REG_DA_AMP_MIN 300000
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#define SI521XX_REG_DA_AMP_DEFAULT 800000
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#define SI521XX_REG_DA_AMP_MAX 1000000
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#define SI521XX_REG_DA_AMP_STEP 100000
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#define SI521XX_REG_DA_AMP(UV) \
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FIELD_PREP(SI521XX_REG_DA_AMP_MASK, \
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((UV) - SI521XX_REG_DA_AMP_MIN) / SI521XX_REG_DA_AMP_STEP)
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#define SI521XX_REG_DA_UNKNOWN BIT(3) /* Always set */
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/* Count of populated OE bits in control register ref, 1 and 2 */
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#define SI521XX_OE_MAP(cr1, cr2) (((cr2) << 8) | (cr1))
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#define SI521XX_OE_MAP_GET_OE(oe, map) (((map) >> (((oe) - 1) * 8)) & 0xff)
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#define SI521XX_DIFF_MULT 4
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#define SI521XX_DIFF_DIV 1
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/* Supported Skyworks Si521xx models. */
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enum si521xx_model {
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SI52144 = 0x44,
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SI52146 = 0x46,
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SI52147 = 0x47,
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};
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struct si521xx;
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struct si_clk {
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struct clk_hw hw;
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struct si521xx *si;
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u8 reg;
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u8 bit;
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};
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struct si521xx {
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struct i2c_client *client;
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struct regmap *regmap;
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struct si_clk clk_dif[9];
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u16 chip_info;
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u8 pll_amplitude;
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};
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/*
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* Si521xx i2c regmap
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*/
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static const struct regmap_range si521xx_readable_ranges[] = {
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regmap_reg_range(SI521XX_REG_OE(0), SI521XX_REG_DA),
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};
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static const struct regmap_access_table si521xx_readable_table = {
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.yes_ranges = si521xx_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(si521xx_readable_ranges),
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};
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static const struct regmap_range si521xx_writeable_ranges[] = {
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regmap_reg_range(SI521XX_REG_OE(0), SI521XX_REG_OE(1)),
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regmap_reg_range(SI521XX_REG_BC, SI521XX_REG_DA),
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};
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static const struct regmap_access_table si521xx_writeable_table = {
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.yes_ranges = si521xx_writeable_ranges,
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.n_yes_ranges = ARRAY_SIZE(si521xx_writeable_ranges),
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};
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static int si521xx_regmap_i2c_write(void *context, unsigned int reg,
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unsigned int val)
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{
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struct i2c_client *i2c = context;
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const u8 data[2] = { reg, val };
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const int count = ARRAY_SIZE(data);
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int ret;
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ret = i2c_master_send(i2c, data, count);
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if (ret == count)
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return 0;
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else if (ret < 0)
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return ret;
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else
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return -EIO;
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}
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static int si521xx_regmap_i2c_read(void *context, unsigned int reg,
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unsigned int *val)
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{
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struct i2c_client *i2c = context;
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struct i2c_msg xfer[2];
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u8 txdata = reg;
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u8 rxdata[2];
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int ret;
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xfer[0].addr = i2c->addr;
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xfer[0].flags = 0;
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xfer[0].len = 1;
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xfer[0].buf = (void *)&txdata;
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xfer[1].addr = i2c->addr;
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xfer[1].flags = I2C_M_RD;
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xfer[1].len = 2;
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xfer[1].buf = (void *)rxdata;
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ret = i2c_transfer(i2c->adapter, xfer, 2);
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if (ret < 0)
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return ret;
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if (ret != 2)
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return -EIO;
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/*
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* Byte 0 is transfer length, which is always 1 due
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* to BCP register programming to 1 in si521xx_probe(),
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* ignore it and use data from Byte 1.
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*/
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*val = rxdata[1];
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return 0;
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}
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static const struct regmap_config si521xx_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.cache_type = REGCACHE_FLAT,
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.max_register = SI521XX_REG_DA,
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.rd_table = &si521xx_readable_table,
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.wr_table = &si521xx_writeable_table,
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.reg_write = si521xx_regmap_i2c_write,
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.reg_read = si521xx_regmap_i2c_read,
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};
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static unsigned long si521xx_diff_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long long rate;
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rate = (unsigned long long)parent_rate * SI521XX_DIFF_MULT;
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do_div(rate, SI521XX_DIFF_DIV);
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return (unsigned long)rate;
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}
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static long si521xx_diff_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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unsigned long best_parent;
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best_parent = (rate / SI521XX_DIFF_MULT) * SI521XX_DIFF_DIV;
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*prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
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return (*prate / SI521XX_DIFF_DIV) * SI521XX_DIFF_MULT;
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}
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static int si521xx_diff_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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/*
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* We must report success but we can do so unconditionally because
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* si521xx_diff_round_rate returns values that ensure this call is a
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* nop.
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*/
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return 0;
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}
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#define to_si521xx_clk(_hw) container_of(_hw, struct si_clk, hw)
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static int si521xx_diff_prepare(struct clk_hw *hw)
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{
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struct si_clk *si_clk = to_si521xx_clk(hw);
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struct si521xx *si = si_clk->si;
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regmap_set_bits(si->regmap, SI521XX_REG_OE(si_clk->reg), si_clk->bit);
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return 0;
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}
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static void si521xx_diff_unprepare(struct clk_hw *hw)
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{
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struct si_clk *si_clk = to_si521xx_clk(hw);
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struct si521xx *si = si_clk->si;
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regmap_clear_bits(si->regmap, SI521XX_REG_OE(si_clk->reg), si_clk->bit);
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}
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static const struct clk_ops si521xx_diff_clk_ops = {
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.round_rate = si521xx_diff_round_rate,
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.set_rate = si521xx_diff_set_rate,
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.recalc_rate = si521xx_diff_recalc_rate,
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.prepare = si521xx_diff_prepare,
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.unprepare = si521xx_diff_unprepare,
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};
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static int si521xx_get_common_config(struct si521xx *si)
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{
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struct i2c_client *client = si->client;
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struct device_node *np = client->dev.of_node;
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unsigned int amp;
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int ret;
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/* Set defaults */
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si->pll_amplitude = SI521XX_REG_DA_AMP(SI521XX_REG_DA_AMP_DEFAULT);
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/* Output clock amplitude */
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ret = of_property_read_u32(np, "skyworks,out-amplitude-microvolt",
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&);
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if (!ret) {
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if (amp < SI521XX_REG_DA_AMP_MIN || amp > SI521XX_REG_DA_AMP_MAX ||
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amp % SI521XX_REG_DA_AMP_STEP) {
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return dev_err_probe(&client->dev, -EINVAL,
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"Invalid skyworks,out-amplitude-microvolt value\n");
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}
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si->pll_amplitude = SI521XX_REG_DA_AMP(amp);
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}
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return 0;
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}
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static void si521xx_update_config(struct si521xx *si)
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{
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/* If amplitude is non-default, update it. */
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if (si->pll_amplitude == SI521XX_REG_DA_AMP(SI521XX_REG_DA_AMP_DEFAULT))
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return;
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regmap_update_bits(si->regmap, SI521XX_REG_DA,
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SI521XX_REG_DA_AMP_MASK, si->pll_amplitude);
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}
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static void si521xx_diff_idx_to_reg_bit(const u16 chip_info, const int idx,
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struct si_clk *clk)
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{
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unsigned long mask;
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int oe, b, ctr = 0;
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for (oe = 1; oe <= 2; oe++) {
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mask = bitrev8(SI521XX_OE_MAP_GET_OE(oe, chip_info));
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for_each_set_bit(b, &mask, 8) {
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if (ctr++ != idx)
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continue;
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clk->reg = SI521XX_REG_OE(oe);
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clk->bit = 7 - b;
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return;
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}
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}
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}
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static struct clk_hw *
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si521xx_of_clk_get(struct of_phandle_args *clkspec, void *data)
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{
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struct si521xx *si = data;
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unsigned int idx = clkspec->args[0];
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return &si->clk_dif[idx].hw;
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}
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static int si521xx_probe(struct i2c_client *client)
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{
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const u16 chip_info = (u16)(uintptr_t)device_get_match_data(&client->dev);
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const struct clk_parent_data clk_parent_data = { .index = 0 };
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const u8 data[3] = { SI521XX_REG_BC, 1, 1 };
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unsigned char name[16] = "DIFF0";
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struct clk_init_data init = {};
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struct si521xx *si;
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int i, ret;
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if (!chip_info)
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return -EINVAL;
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si = devm_kzalloc(&client->dev, sizeof(*si), GFP_KERNEL);
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if (!si)
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return -ENOMEM;
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i2c_set_clientdata(client, si);
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si->client = client;
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/* Fetch common configuration from DT (if specified) */
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ret = si521xx_get_common_config(si);
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if (ret)
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return ret;
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si->regmap = devm_regmap_init(&client->dev, NULL, client,
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&si521xx_regmap_config);
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if (IS_ERR(si->regmap))
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return dev_err_probe(&client->dev, PTR_ERR(si->regmap),
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"Failed to allocate register map\n");
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/* Always read back 1 Byte via I2C */
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ret = i2c_master_send(client, data, ARRAY_SIZE(data));
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if (ret < 0)
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return ret;
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/* Register clock */
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for (i = 0; i < hweight16(chip_info); i++) {
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memset(&init, 0, sizeof(init));
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snprintf(name, sizeof(name), "DIFF%d", i);
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init.name = name;
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init.ops = &si521xx_diff_clk_ops;
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init.parent_data = &clk_parent_data;
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init.num_parents = 1;
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init.flags = CLK_SET_RATE_PARENT;
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si->clk_dif[i].hw.init = &init;
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si->clk_dif[i].si = si;
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si521xx_diff_idx_to_reg_bit(chip_info, i, &si->clk_dif[i]);
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ret = devm_clk_hw_register(&client->dev, &si->clk_dif[i].hw);
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if (ret)
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return ret;
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}
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ret = devm_of_clk_add_hw_provider(&client->dev, si521xx_of_clk_get, si);
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if (!ret)
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si521xx_update_config(si);
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return ret;
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}
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static int __maybe_unused si521xx_suspend(struct device *dev)
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{
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struct si521xx *si = dev_get_drvdata(dev);
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regcache_cache_only(si->regmap, true);
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regcache_mark_dirty(si->regmap);
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return 0;
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}
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static int __maybe_unused si521xx_resume(struct device *dev)
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{
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struct si521xx *si = dev_get_drvdata(dev);
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int ret;
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regcache_cache_only(si->regmap, false);
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ret = regcache_sync(si->regmap);
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if (ret)
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dev_err(dev, "Failed to restore register map: %d\n", ret);
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return ret;
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}
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static const struct i2c_device_id si521xx_id[] = {
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{ "si52144", .driver_data = SI521XX_OE_MAP(0x5, 0xc0) },
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{ "si52146", .driver_data = SI521XX_OE_MAP(0x15, 0xe0) },
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{ "si52147", .driver_data = SI521XX_OE_MAP(0x17, 0xf8) },
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{ }
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};
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MODULE_DEVICE_TABLE(i2c, si521xx_id);
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static const struct of_device_id clk_si521xx_of_match[] = {
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{ .compatible = "skyworks,si52144", .data = (void *)SI521XX_OE_MAP(0x5, 0xc0) },
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{ .compatible = "skyworks,si52146", .data = (void *)SI521XX_OE_MAP(0x15, 0xe0) },
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{ .compatible = "skyworks,si52147", .data = (void *)SI521XX_OE_MAP(0x15, 0xf8) },
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{ }
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};
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MODULE_DEVICE_TABLE(of, clk_si521xx_of_match);
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static SIMPLE_DEV_PM_OPS(si521xx_pm_ops, si521xx_suspend, si521xx_resume);
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static struct i2c_driver si521xx_driver = {
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.driver = {
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.name = "clk-si521xx",
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.pm = &si521xx_pm_ops,
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.of_match_table = clk_si521xx_of_match,
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},
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.probe = si521xx_probe,
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.id_table = si521xx_id,
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};
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module_i2c_driver(si521xx_driver);
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MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
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MODULE_DESCRIPTION("Skyworks Si521xx PCIe clock generator driver");
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MODULE_LICENSE("GPL");
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