// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2017 MediaTek Inc.
 * Author: John Crispin <john@phrozen.org>
 *	   Sean Wang <sean.wang@mediatek.com>
 *
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt2701-clk.h>
#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/mt2701-resets.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "mediatek,mt7623";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpu_opp_table: opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-98000000 {
			opp-hz = /bits/ 64 <98000000>;
			opp-microvolt = <1050000>;
		};

		opp-198000000 {
			opp-hz = /bits/ 64 <198000000>;
			opp-microvolt = <1050000>;
		};

		opp-398000000 {
			opp-hz = /bits/ 64 <398000000>;
			opp-microvolt = <1050000>;
		};

		opp-598000000 {
			opp-hz = /bits/ 64 <598000000>;
			opp-microvolt = <1050000>;
		};

		opp-747500000 {
			opp-hz = /bits/ 64 <747500000>;
			opp-microvolt = <1050000>;
		};

		opp-1040000000 {
			opp-hz = /bits/ 64 <1040000000>;
			opp-microvolt = <1150000>;
		};

		opp-1196000000 {
			opp-hz = /bits/ 64 <1196000000>;
			opp-microvolt = <1200000>;
		};

		opp-1300000000 {
			opp-hz = /bits/ 64 <1300000000>;
			opp-microvolt = <1300000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "mediatek,mt6589-smp";

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			clocks = <&infracfg CLK_INFRA_CPUSEL>,
				 <&apmixedsys CLK_APMIXED_MAINPLL>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>;
			clock-frequency = <1300000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
			clocks = <&infracfg CLK_INFRA_CPUSEL>,
				 <&apmixedsys CLK_APMIXED_MAINPLL>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cpu_opp_table>;
			clock-frequency = <1300000000>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x2>;
			clocks = <&infracfg CLK_INFRA_CPUSEL>,
				 <&apmixedsys CLK_APMIXED_MAINPLL>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cpu_opp_table>;
			clock-frequency = <1300000000>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x3>;
			clocks = <&infracfg CLK_INFRA_CPUSEL>,
				 <&apmixedsys CLK_APMIXED_MAINPLL>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cpu_opp_table>;
			clock-frequency = <1300000000>;
		};
	};

	system_clk: dummy13m {
		compatible = "fixed-clock";
		clock-frequency = <13000000>;
		#clock-cells = <0>;
	};

	rtc32k: oscillator-1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32000>;
		clock-output-names = "rtc32k";
	};

	clk26m: oscillator-0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	thermal-zones {
			cpu_thermal: cpu-thermal {
				polling-delay-passive = <1000>;
				polling-delay = <1000>;

				thermal-sensors = <&thermal 0>;

				trips {
					cpu_passive: cpu-passive {
						temperature = <47000>;
						hysteresis = <2000>;
						type = "passive";
					};

					cpu_active: cpu-active {
						temperature = <67000>;
						hysteresis = <2000>;
						type = "active";
					};

					cpu_hot: cpu-hot {
						temperature = <87000>;
						hysteresis = <2000>;
						type = "hot";
					};

					cpu-crit {
						temperature = <107000>;
						hysteresis = <2000>;
						type = "critical";
					};
				};

			cooling-maps {
				map0 {
					trip = <&cpu_passive>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};

				map1 {
					trip = <&cpu_active>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};

				map2 {
					trip = <&cpu_hot>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		clock-frequency = <13000000>;
		arm,cpu-registers-not-fw-configured;
	};

	topckgen: syscon@10000000 {
		compatible = "mediatek,mt7623-topckgen",
			     "mediatek,mt2701-topckgen",
			     "syscon";
		reg = <0 0x10000000 0 0x1000>;
		#clock-cells = <1>;
	};

	infracfg: syscon@10001000 {
		compatible = "mediatek,mt7623-infracfg",
			     "mediatek,mt2701-infracfg",
			     "syscon";
		reg = <0 0x10001000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pericfg: syscon@10003000 {
		compatible =  "mediatek,mt7623-pericfg",
			      "mediatek,mt2701-pericfg",
			      "syscon";
		reg = <0 0x10003000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pio: pinctrl@10005000 {
		compatible = "mediatek,mt7623-pinctrl";
		reg = <0 0x1000b000 0 0x1000>;
		mediatek,pctl-regmap = <&syscfg_pctl_a>;
		pins-are-numbered;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		interrupt-parent = <&gic>;
		#interrupt-cells = <2>;
		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	};

	syscfg_pctl_a: syscfg@10005000 {
		compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
		reg = <0 0x10005000 0 0x1000>;
	};

	scpsys: scpsys@10006000 {
		compatible = "mediatek,mt7623-scpsys",
			     "mediatek,mt2701-scpsys",
			     "syscon";
		#power-domain-cells = <1>;
		reg = <0 0x10006000 0 0x1000>;
		infracfg = <&infracfg>;
		clocks = <&topckgen CLK_TOP_MM_SEL>,
			 <&topckgen CLK_TOP_MFG_SEL>,
			 <&topckgen CLK_TOP_ETHIF_SEL>;
		clock-names = "mm", "mfg", "ethif";
	};

	watchdog: watchdog@10007000 {
		compatible = "mediatek,mt7623-wdt",
			     "mediatek,mt6589-wdt";
		reg = <0 0x10007000 0 0x100>;
	};

	timer: timer@10008000 {
		compatible = "mediatek,mt7623-timer",
			     "mediatek,mt6577-timer";
		reg = <0 0x10008000 0 0x80>;
		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&system_clk>, <&rtc32k>;
		clock-names = "system-clk", "rtc-clk";
	};

	pwrap: pwrap@1000d000 {
		compatible = "mediatek,mt7623-pwrap",
			     "mediatek,mt2701-pwrap";
		reg = <0 0x1000d000 0 0x1000>;
		reg-names = "pwrap";
		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
		resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
		reset-names = "pwrap";
		clocks = <&infracfg CLK_INFRA_PMICSPI>,
			 <&infracfg CLK_INFRA_PMICWRAP>;
		clock-names = "spi", "wrap";
	};

	cir: cir@10013000 {
		compatible = "mediatek,mt7623-cir";
		reg = <0 0x10013000 0 0x1000>;
		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg CLK_INFRA_IRRX>;
		clock-names = "clk";
		status = "disabled";
	};

	sysirq: interrupt-controller@10200100 {
		compatible = "mediatek,mt7623-sysirq",
			     "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10200100 0 0x1c>;
	};

	efuse: efuse@10206000 {
		compatible = "mediatek,mt7623-efuse",
			     "mediatek,mt8173-efuse";
		reg = <0 0x10206000 0 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;
		thermal_calibration_data: calib@424 {
			reg = <0x424 0xc>;
		};
	};

	apmixedsys: syscon@10209000 {
		compatible = "mediatek,mt7623-apmixedsys",
			     "mediatek,mt2701-apmixedsys",
			     "syscon";
		reg = <0 0x10209000 0 0x1000>;
		#clock-cells = <1>;
	};

	rng: rng@1020f000 {
		compatible = "mediatek,mt7623-rng";
		reg = <0 0x1020f000 0 0x1000>;
		clocks = <&infracfg CLK_INFRA_TRNG>;
		clock-names = "rng";
	};

	gic: interrupt-controller@10211000 {
		compatible = "arm,cortex-a7-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10211000 0 0x1000>,
		      <0 0x10212000 0 0x2000>,
		      <0 0x10214000 0 0x2000>,
		      <0 0x10216000 0 0x2000>;
	};

	auxadc: adc@11001000 {
		compatible = "mediatek,mt7623-auxadc",
			     "mediatek,mt2701-auxadc";
		reg = <0 0x11001000 0 0x1000>;
		clocks = <&pericfg CLK_PERI_AUXADC>;
		clock-names = "main";
		#io-channel-cells = <1>;
	};

	uart0: serial@11002000 {
		compatible = "mediatek,mt7623-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11002000 0 0x400>;
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART0_SEL>,
			 <&pericfg CLK_PERI_UART0>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart1: serial@11003000 {
		compatible = "mediatek,mt7623-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11003000 0 0x400>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART1_SEL>,
			 <&pericfg CLK_PERI_UART1>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart2: serial@11004000 {
		compatible = "mediatek,mt7623-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11004000 0 0x400>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART2_SEL>,
			 <&pericfg CLK_PERI_UART2>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart3: serial@11005000 {
		compatible = "mediatek,mt7623-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11005000 0 0x400>;
		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART3_SEL>,
			 <&pericfg CLK_PERI_UART3>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	pwm: pwm@11006000 {
		compatible = "mediatek,mt7623-pwm";
		reg = <0 0x11006000 0 0x1000>;
		#pwm-cells = <2>;
		clocks = <&topckgen CLK_TOP_PWM_SEL>,
			 <&pericfg CLK_PERI_PWM>,
			 <&pericfg CLK_PERI_PWM1>,
			 <&pericfg CLK_PERI_PWM2>,
			 <&pericfg CLK_PERI_PWM3>,
			 <&pericfg CLK_PERI_PWM4>,
			 <&pericfg CLK_PERI_PWM5>;
		clock-names = "top", "main", "pwm1", "pwm2",
			      "pwm3", "pwm4", "pwm5";
		status = "disabled";
	};

	i2c0: i2c@11007000 {
		compatible = "mediatek,mt7623-i2c",
			     "mediatek,mt6577-i2c";
		reg = <0 0x11007000 0 0x70>,
		      <0 0x11000200 0 0x80>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
		clock-div = <16>;
		clocks = <&pericfg CLK_PERI_I2C0>,
			 <&pericfg CLK_PERI_AP_DMA>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c1: i2c@11008000 {
		compatible = "mediatek,mt7623-i2c",
			     "mediatek,mt6577-i2c";
		reg = <0 0x11008000 0 0x70>,
		      <0 0x11000280 0 0x80>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
		clock-div = <16>;
		clocks = <&pericfg CLK_PERI_I2C1>,
			 <&pericfg CLK_PERI_AP_DMA>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c2: i2c@11009000 {
		compatible = "mediatek,mt7623-i2c",
			     "mediatek,mt6577-i2c";
		reg = <0 0x11009000 0 0x70>,
		      <0 0x11000300 0 0x80>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
		clock-div = <16>;
		clocks = <&pericfg CLK_PERI_I2C2>,
			 <&pericfg CLK_PERI_AP_DMA>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi0: spi@1100a000 {
		compatible = "mediatek,mt7623-spi",
			     "mediatek,mt2701-spi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0x1100a000 0 0x100>;
		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI0_SEL>,
			 <&pericfg CLK_PERI_SPI0>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
		status = "disabled";
	};

	thermal: thermal@1100b000 {
		#thermal-sensor-cells = <1>;
		compatible = "mediatek,mt7623-thermal",
			     "mediatek,mt2701-thermal";
		reg = <0 0x1100b000 0 0x1000>;
		interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
		clock-names = "therm", "auxadc";
		resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
		reset-names = "therm";
		mediatek,auxadc = <&auxadc>;
		mediatek,apmixedsys = <&apmixedsys>;
		nvmem-cells = <&thermal_calibration_data>;
		nvmem-cell-names = "calibration-data";
	};

	nandc: nfi@1100d000 {
		compatible = "mediatek,mt7623-nfc",
			     "mediatek,mt2701-nfc";
		reg = <0 0x1100d000 0 0x1000>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
		clocks = <&pericfg CLK_PERI_NFI>,
			 <&pericfg CLK_PERI_NFI_PAD>;
		clock-names = "nfi_clk", "pad_clk";
		status = "disabled";
		ecc-engine = <&bch>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	bch: ecc@1100e000 {
		compatible = "mediatek,mt7623-ecc",
			     "mediatek,mt2701-ecc";
		reg = <0 0x1100e000 0 0x1000>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_NFI_ECC>;
		clock-names = "nfiecc_clk";
		status = "disabled";
	};

	spi1: spi@11016000 {
		compatible = "mediatek,mt7623-spi",
			     "mediatek,mt2701-spi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0x11016000 0 0x100>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI1_SEL>,
			 <&pericfg CLK_PERI_SPI1>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
		status = "disabled";
	};

	spi2: spi@11017000 {
		compatible = "mediatek,mt7623-spi",
			     "mediatek,mt2701-spi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0x11017000 0 0x1000>;
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI2_SEL>,
			 <&pericfg CLK_PERI_SPI2>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
		status = "disabled";
	};

	audsys: clock-controller@11220000 {
		compatible = "mediatek,mt7623-audsys",
			     "mediatek,mt2701-audsys",
			     "syscon";
		reg = <0 0x11220000 0 0x2000>;
		#clock-cells = <1>;

		afe: audio-controller {
			compatible = "mediatek,mt7623-audio",
				     "mediatek,mt2701-audio";
			interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
				      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
			interrupt-names	= "afe", "asys";
			power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;

			clocks = <&infracfg CLK_INFRA_AUDIO>,
				 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
				 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
				 <&topckgen CLK_TOP_AUD_48K_TIMING>,
				 <&topckgen CLK_TOP_AUD_44K_TIMING>,
				 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
				 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
				 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
				 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
				 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
				 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
				 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
				 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
				 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
				 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
				 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
				 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
				 <&audsys CLK_AUD_I2SO1>,
				 <&audsys CLK_AUD_I2SO2>,
				 <&audsys CLK_AUD_I2SO3>,
				 <&audsys CLK_AUD_I2SO4>,
				 <&audsys CLK_AUD_I2SIN1>,
				 <&audsys CLK_AUD_I2SIN2>,
				 <&audsys CLK_AUD_I2SIN3>,
				 <&audsys CLK_AUD_I2SIN4>,
				 <&audsys CLK_AUD_ASRCO1>,
				 <&audsys CLK_AUD_ASRCO2>,
				 <&audsys CLK_AUD_ASRCO3>,
				 <&audsys CLK_AUD_ASRCO4>,
				 <&audsys CLK_AUD_AFE>,
				 <&audsys CLK_AUD_AFE_CONN>,
				 <&audsys CLK_AUD_A1SYS>,
				 <&audsys CLK_AUD_A2SYS>,
				 <&audsys CLK_AUD_AFE_MRGIF>;

			clock-names = "infra_sys_audio_clk",
				      "top_audio_mux1_sel",
				      "top_audio_mux2_sel",
				      "top_audio_a1sys_hp",
				      "top_audio_a2sys_hp",
				      "i2s0_src_sel",
				      "i2s1_src_sel",
				      "i2s2_src_sel",
				      "i2s3_src_sel",
				      "i2s0_src_div",
				      "i2s1_src_div",
				      "i2s2_src_div",
				      "i2s3_src_div",
				      "i2s0_mclk_en",
				      "i2s1_mclk_en",
				      "i2s2_mclk_en",
				      "i2s3_mclk_en",
				      "i2so0_hop_ck",
				      "i2so1_hop_ck",
				      "i2so2_hop_ck",
				      "i2so3_hop_ck",
				      "i2si0_hop_ck",
				      "i2si1_hop_ck",
				      "i2si2_hop_ck",
				      "i2si3_hop_ck",
				      "asrc0_out_ck",
				      "asrc1_out_ck",
				      "asrc2_out_ck",
				      "asrc3_out_ck",
				      "audio_afe_pd",
				      "audio_afe_conn_pd",
				      "audio_a1sys_pd",
				      "audio_a2sys_pd",
				      "audio_mrgif_pd";

			assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
					  <&topckgen CLK_TOP_AUD_MUX2_SEL>,
					  <&topckgen CLK_TOP_AUD_MUX1_DIV>,
					  <&topckgen CLK_TOP_AUD_MUX2_DIV>;
			assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
						 <&topckgen CLK_TOP_AUD2PLL_90M>;
			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
		};
	};

	mmc0: mmc@11230000 {
		compatible = "mediatek,mt7623-mmc",
			     "mediatek,mt2701-mmc";
		reg = <0 0x11230000 0 0x1000>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_MSDC30_0>,
			 <&topckgen CLK_TOP_MSDC30_0_SEL>;
		clock-names = "source", "hclk";
		status = "disabled";
	};

	mmc1: mmc@11240000 {
		compatible = "mediatek,mt7623-mmc",
			     "mediatek,mt2701-mmc";
		reg = <0 0x11240000 0 0x1000>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_MSDC30_1>,
			 <&topckgen CLK_TOP_MSDC30_1_SEL>;
		clock-names = "source", "hclk";
		status = "disabled";
	};

	hifsys: syscon@1a000000 {
		compatible = "mediatek,mt7623-hifsys",
			     "mediatek,mt2701-hifsys",
			     "syscon";
		reg = <0 0x1a000000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pcie: pcie@1a140000 {
		compatible = "mediatek,mt7623-pcie";
		device_type = "pci";
		reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
		      <0 0x1a142000 0 0x1000>, /* Port0 registers */
		      <0 0x1a143000 0 0x1000>, /* Port1 registers */
		      <0 0x1a144000 0 0x1000>; /* Port2 registers */
		reg-names = "subsys", "port0", "port1", "port2";
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xf800 0 0 0>;
		interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
				<0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
				<0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
			 <&hifsys CLK_HIFSYS_PCIE0>,
			 <&hifsys CLK_HIFSYS_PCIE1>,
			 <&hifsys CLK_HIFSYS_PCIE2>;
		clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
		resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
			 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
			 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
		reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
		phys = <&pcie0_port PHY_TYPE_PCIE>,
		       <&pcie1_port PHY_TYPE_PCIE>,
		       <&u3port1 PHY_TYPE_PCIE>;
		phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
		bus-range = <0x00 0xff>;
		status = "disabled";
		ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
			  0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;

		pcie@0,0 {
			reg = <0x0000 0 0 0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
			ranges;
			num-lanes = <1>;
			status = "disabled";
		};

		pcie@1,0 {
			reg = <0x0800 0 0 0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
			ranges;
			num-lanes = <1>;
			status = "disabled";
		};

		pcie@2,0 {
			reg = <0x1000 0 0 0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
			ranges;
			num-lanes = <1>;
			status = "disabled";
		};
	};

	pcie0_phy: pcie-phy@1a149000 {
		compatible = "mediatek,generic-tphy-v1";
		reg = <0 0x1a149000 0 0x0700>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		pcie0_port: pcie-phy@1a149900 {
			reg = <0 0x1a149900 0 0x0700>;
			clocks = <&clk26m>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};
	};

	pcie1_phy: pcie-phy@1a14a000 {
		compatible = "mediatek,generic-tphy-v1";
		reg = <0 0x1a14a000 0 0x0700>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		pcie1_port: pcie-phy@1a14a900 {
			reg = <0 0x1a14a900 0 0x0700>;
			clocks = <&clk26m>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};
	};

	usb1: usb@1a1c0000 {
		compatible = "mediatek,mt7623-xhci",
			     "mediatek,mt8173-xhci";
		reg = <0 0x1a1c0000 0 0x1000>,
		      <0 0x1a1c4700 0 0x0100>;
		reg-names = "mac", "ippc";
		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
			 <&topckgen CLK_TOP_ETHIF_SEL>;
		clock-names = "sys_ck", "ref_ck";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
		phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
		status = "disabled";
	};

	u3phy1: usb-phy@1a1c4000 {
		compatible = "mediatek,mt7623-u3phy",
			     "mediatek,mt2701-u3phy";
		reg = <0 0x1a1c4000 0 0x0700>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		u2port0: usb-phy@1a1c4800 {
			reg = <0 0x1a1c4800 0 0x0100>;
			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};

		u3port0: usb-phy@1a1c4900 {
			reg = <0 0x1a1c4900 0 0x0700>;
			clocks = <&clk26m>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};
	};

	usb2: usb@1a240000 {
		compatible = "mediatek,mt7623-xhci",
			     "mediatek,mt8173-xhci";
		reg = <0 0x1a240000 0 0x1000>,
		      <0 0x1a244700 0 0x0100>;
		reg-names = "mac", "ippc";
		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
			 <&topckgen CLK_TOP_ETHIF_SEL>;
		clock-names = "sys_ck", "ref_ck";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
		phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
		status = "disabled";
	};

	u3phy2: usb-phy@1a244000 {
		compatible = "mediatek,mt7623-u3phy",
			     "mediatek,mt2701-u3phy";
		reg = <0 0x1a244000 0 0x0700>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		u2port1: usb-phy@1a244800 {
			reg = <0 0x1a244800 0 0x0100>;
			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};

		u3port1: usb-phy@1a244900 {
			reg = <0 0x1a244900 0 0x0700>;
			clocks = <&clk26m>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};
	};

	ethsys: syscon@1b000000 {
		compatible = "mediatek,mt7623-ethsys",
			     "mediatek,mt2701-ethsys",
			     "syscon";
		reg = <0 0x1b000000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	eth: ethernet@1b100000 {
		compatible = "mediatek,mt7623-eth",
			     "mediatek,mt2701-eth",
			     "syscon";
		reg = <0 0x1b100000 0 0x20000>;
		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
			 <&ethsys CLK_ETHSYS_ESW>,
			 <&ethsys CLK_ETHSYS_GP1>,
			 <&ethsys CLK_ETHSYS_GP2>,
			 <&apmixedsys CLK_APMIXED_TRGPLL>;
		clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
		resets = <&ethsys MT2701_ETHSYS_FE_RST>,
			 <&ethsys MT2701_ETHSYS_GMAC_RST>,
			 <&ethsys MT2701_ETHSYS_PPE_RST>;
		reset-names = "fe", "gmac", "ppe";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
		mediatek,ethsys = <&ethsys>;
		mediatek,pctl = <&syscfg_pctl_a>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	crypto: crypto@1b240000 {
		compatible = "mediatek,eip97-crypto";
		reg = <0 0x1b240000 0 0x20000>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
		clock-names = "cryp";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
		status = "disabled";
	};
};