Move the soc revision parsing to the initial probe, saving the driver
from parsing the register multiple times.
Use this variable to select the correct divisor table for the AHB clock.
Before this fix the A2 would have used the A0 table.
Fixes: 2d491066cc ("clk: ast2600: Fix AHB clock divider for A1")
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20210922235449.213631-1-joel@jms.id.au
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
During commit 6594988fd6 ("clk: composite: Use rate_ops.determine_rate
when also a mux is available") setting req->best_parent_hw got lost,
so best_parent_hw stays NULL during switch to the same parent. This
results in the (debug) message:
clk_calc_new_rates: lcdif_pixel not gated but wants to reparent
and the following rate change is dropped.
Fixes: 6594988fd6 ("clk: composite: Use rate_ops.determine_rate when also a mux is available")
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Link: https://lore.kernel.org/r/20211103122441.3208576-1-alexander.stein@ew.tq-group.com
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Both of these drivers were converted to real drivers and got a tristate
build option. But them being builtin_platform_drivers, they only ever
should be build-in - as the name suggests.
So adapt the Kconfig symbol and drop the MODULE_* parts from the drivers.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20211027132616.1039814-3-heiko@sntech.de
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This reverts commit 1da80da028.
Reading recent discussions [0] [1], I realized this change introduces
a number of problems:
- only converting to module_platform_driver creates the issue
with the existing __init and __initdata attributes.
When the driver would've been built as a module, all the missing
clock-definitions (all are initdata) should've turned up as error
in testing suggesting that the change wasn't at all
- a clock driver is a very core component of soc bringup and making
this able to be built as a module solely for enabling the soc vendor
to add out of tree changes for Android implementations is not in our
interest and also everything except a ramdisk won't probe without a
clock controller.
This is especially true when the changes aren't really tested and
are merely added to move the mainline driver "out of the way".
[0] https://lwn.net/Articles/872209/
[1] https://lore.kernel.org/all/163529604399.15791.378104318036812951@swboyd.mtv.corp.google.com/
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20211027132616.1039814-2-heiko@sntech.de
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
'dt-bindings/clock/mt8195-clk.h' included in
'/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c' is duplicated.It is
also included on the 13 line.
Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: Ran Jianping <ran.jianping@zte.com.cn>
Link: https://lore.kernel.org/r/20211019062939.979660-1-ran.jianping@zte.com.cn
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The SiFive FU740 Power Reset Clock Interrupt Controller is a reset line
provider so add respective reset-cells property to fix:
arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dt.yaml: clock-controller@10000000:
'#reset-cells' does not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210920144944.162431-1-krzysztof.kozlowski@canonical.com
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add basic clock data for UniPhier NX1 SoC.
This includes PLL and clock division data for cpufreq support.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1634000035-3114-4-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Silicon Labs is now part of Skyworks Inc. so update the URLs to the
datasheet and application note.
Signed-off-by: Jens Renner <renner@efe-gmbh.de>
Link: https://lore.kernel.org/r/20210913074823.115212-1-renner@efe-gmbh.de
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
owl-factor.c hasn't use any macro or function declared in linux/slab.h.
Thus, these files can be removed from owl-factor.c safely without
affecting the compilation of the ./drivers/clk module
Signed-off-by: Mianhan Liu <liumh1@shanghaitech.edu.cn>
Link: https://lore.kernel.org/r/20210929065824.23691-1-liumh1@shanghaitech.edu.cn
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Two fixes in one:
- In the "impose hardware constraints" block, the "logical" divider
value (aka. not translated to the hardware) was clamped to fit in the
register area, but this totally ignored the fact that the divider
value can itself have a fixed divider.
- The code that made sure that the divider value returned by the
function was a multiple of its own fixed divider could result in a
wrong value being calculated, because it was rounded down instead of
rounded up.
Fixes: 4afe2d1a6e ("clk: ingenic: Allow divider value to be divided")
Co-developed-by: Artur Rojek <contact@artur-rojek.eu>
Signed-off-by: Artur Rojek <contact@artur-rojek.eu>
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20211001172033.122329-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk-composite-determine-fix:
clk: composite: Use rate_ops.determine_rate when also a mux is available
clk: composite: Also consider .determine_rate for rate + mux composites
* clk-allwinner:
clk: sunxi: sun8i-apb0: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi: sun6i-ar100: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi: sun6i-apb0-gates: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi: sun6i-apb0: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun9i-a80-usb: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun9i-a80-de: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun9i-a80: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun8i-r40: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun8i-de2: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun8i-a83t: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun50i-h6: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun50i-a64: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi: clk-mod0: Make use of the helper function devm_platform_ioremap_resource()
dt-bindings: clocks: Fix typo in the H6 compatible
clk: sunxi-ng: Use a separate lock for each CCU instance
clk: sunxi-ng: Prevent unbinding CCUs via sysfs
clk: sunxi-ng: Unregister clocks/resets when unbinding
clk: sunxi-ng: Add machine dependency to A83T CCU
clk: sunxi-ng: mux: Remove unused 'reg' field
* clk-amlogic:
clk: meson: meson8b: Make the video clock trees mutable
clk: meson: meson8b: Initialize the HDMI PLL registers
clk: meson: meson8b: Add the HDMI PLL M/N parameters
clk: meson: meson8b: Add the vid_pll_lvds_en gate clock
clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel
clk: meson: meson8b: Export the video clocks
* clk-samsung:
clk: samsung: describe drivers in Kconfig
clk: samsung: exynos5433: update apollo and atlas clock probing
clk: samsung: add support for CPU clocks
clk: samsung: Introduce Exynos850 clock driver
dt-bindings: clock: Document Exynos850 CMU bindings
dt-bindings: clock: Add bindings definitions for Exynos850 CMU
clk: samsung: clk-pll: Implement pll0831x PLL type
clk: samsung: clk-pll: Implement pll0822x PLL type
clk: samsung: s5pv210-audss: Make use of devm_platform_ioremap_resource()
clk: samsung: exynos5433: Make use of devm_platform_ioremap_resource()
clk: samsung: exynos4412-isp: Make use of devm_platform_ioremap_resource()
clk: samsung: exynos-audss: Make use of devm_platform_ioremap_resource()
* clk-imx: (21 commits)
clk: imx: Make CLK_IMX8ULP select MXC_CLK
clk: imx: imx6ul: Fix csi clk gate register
clk: imx: imx6ul: Move csi_sel mux to correct base register
clk: imx: Fix the build break when clk-imx8ulp build as module
clk: imx: Add the pcc reset controller support on imx8ulp
clk: imx: Add clock driver for imx8ulp
clk: imx: Update the pfdv2 for 8ulp specific support
clk: imx: disable the pfd when set pfdv2 clock rate
clk: imx: Add 'CLK_SET_RATE_NO_REPARENT' for composite-7ulp
clk: imx: disable i.mx7ulp composite clock during initialization
clk: imx: Update the compsite driver to support imx8ulp
clk: imx: Update the pllv4 to support imx8ulp
dt-bindings: clock: Add imx8ulp clock support
clk: imx: Rework imx_clk_hw_pll14xx wrapper
clk: imx: Rework all imx_clk_hw_composite wrappers
clk: imx: Rework all clk_hw_register_divider wrappers
clk: imx: Rework all clk_hw_register_mux wrappers
clk: imx: Rework all clk_hw_register_gate2 wrappers
clk: imx: Rework all clk_hw_register_gate wrappers
clk: imx: Make mux/mux2 clk based helpers use clk_hw based ones
...
* clk-ux500:
clk: ux500: Add driver for the reset portions of PRCC
dt-bindings: clock: u8500: Rewrite in YAML and extend
* clk-debugfs:
clk: use clk_core_get_rate_recalc() in clk_rate_get()
- Clock power management for new SAMA7G5 SoC
- Updates to the master clock driver and sam9x60-pll to be able to use
cpufreq-dt driver and avoid overclocking of CPU and MCK0 domains while
changing the frequency via DVFS
- Power management refinement with the use of save_context()/restore_context()
on each clock driver to specify their use in case of Backup mode only
* clk-leak:
clk: mvebu: ap-cpu-clk: Fix a memory leak in error handling paths
* clk-rockchip:
clk: rockchip: use module_platform_driver_probe
clk: rockchip: rk3399: expose PCLK_COREDBG_{B,L}
clk: rockchip: rk3399: make CPU clocks critical
* clk-renesas:
clk: renesas: r8a779[56]x: Add MLP clocks
clk: renesas: r9a07g044: Add SDHI clock and reset entries
clk: renesas: rzg2l: Add SDHI clk mux support
clk: renesas: r8a779a0: Add RPC support
clk: renesas: cpg-lib: Move RPC clock registration to the library
clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller
clk: renesas: r8a779a0: Add Z0 and Z1 clock support
clk: renesas: r9a07g044: Add GbEthernet clock/reset
clk: renesas: rzg2l: Add support to handle coupled clocks
clk: renesas: r9a07g044: Add ethernet clock sources
clk: renesas: rzg2l: Add support to handle MUX clocks
clk: renesas: r8a779a0: Add TPU clock
clk: renesas: rzg2l: Fix clk status function
clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical
* clk-at91:
clk: at91: sama7g5: set low limit for mck0 at 32KHz
clk: at91: sama7g5: remove prescaler part of master clock
clk: at91: clk-master: add notifier for divider
clk: at91: clk-sam9x60-pll: add notifier for div part of PLL
clk: at91: clk-master: fix prescaler logic
clk: at91: clk-master: mask mckr against layout->mask
clk: at91: clk-master: check if div or pres is zero
clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL
clk: at91: pmc: add sama7g5 to the list of available pmcs
clk: at91: clk-master: improve readability by using local variables
clk: at91: clk-master: add register definition for sama7g5's master clock
clk: at91: sama7g5: add securam's peripheral clock
clk: at91: pmc: execute suspend/resume only for backup mode
clk: at91: re-factor clocks suspend/resume
clk: at91: check pmc node status before registering syscore ops
In case clock flags contains CLK_GET_RATE_NOCACHE the clk_rate_get()
will return the cached rate. Thus, use clk_core_get_rate_recalc() which
takes proper action when clock flags contains CLK_GET_RATE_NOCACHE.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-16-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
[sboyd@kernel.org: Grab prepare lock around operation]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
On SAMA7G5 the prescaler part of master clock has been implemented as a
changeable one. Everytime the prescaler is changed the PMC_SR.MCKRDY bit
must be polled. Value 1 for PMC_SR.MCKRDY means the prescaler update is
done. Driver polls for this bit until it becomes 1. On SAMA7G5 it has
been discovered that in some conditions the PMC_SR.MCKRDY is not rising
but the rate it provides it's stable. The workaround is to add a timeout
when polling for PMC_SR.MCKRDY. At the moment, for SAMA7G5, the prescaler
will be removed from Linux clock tree as all the frequencies for CPU could
be obtained from PLL and also there will be less overhead when changing
frequency via DVFS.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-14-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
SAMA7G5 supports DVFS by changing cpuck. On SAMA7G5 mck0 shares the same
parent with cpuck as seen in the following clock tree:
+----------> cpuck
|
FRAC PLL ---> DIV PLL -+-> DIV ---> mck0
mck0 could go b/w 32KHz and 200MHz on SAMA7G5. To avoid mck0 overclocking
while changing FRAC PLL or DIV PLL the commit implements a notifier for
mck0 which applies a safe divider to register (maximum value of the divider
which is 5) on PRE_RATE_CHANGE events (such that changes on PLL to not
overclock mck0) and sets the maximum allowed rate on POST_RATE_CHANGE
events.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-13-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
SAM9X60's PLL which is also part of SAMA7G5 is composed of 2 parts:
one fractional part and one divider. On SAMA7G5 the CPU PLL could be
changed at run-time to implement DVFS. The hardware clock tree on
SAMA7G5 for CPU PLL is as follows:
+---- div1 ----------------> cpuck
|
FRAC PLL ---> DIV PLL -+-> prescaler ---> div0 ---> mck0
The div1 block is not implemented in Linux; on prescaler block it has
been discovered a bug on some scenarios and will be removed from Linux
in next commits. Thus, the final clock tree that will be used in Linux
will be as follows:
+-----------> cpuck
|
FRAC PLL ---> DIV PLL -+-> div0 ---> mck0
It has been proposed in [1] to not introduce a new CPUFreq driver but
to overload the proper clock drivers with proper operation such that
cpufreq-dt to be used. To accomplish this DIV PLL and div0 implement
clock notifiers which applies safe dividers before FRAC PLL is changed.
The current commit treats only the DIV PLL by adding a notifier that
sets a safe divider on PRE_RATE_CHANGE events. The safe divider is
provided by initialization clock code (sama7g5.c). The div0 is treated
in next commits (to keep the changes as clean as possible).
[1] https://lore.kernel.org/lkml/20210105104426.4tmgc2l3vyicwedd@vireshk-i7/
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-12-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
When prescaler value read from register is MASTER_PRES_MAX it means
that the input clock will be divided by 3. Fix the code to reflect
this.
Fixes: 7a110b9107 ("clk: at91: clk-master: re-factor master clock")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-11-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Mask values read/written from/to MCKR against layout->mask as this
mask may be different b/w PMC versions.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-10-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Check if div or pres is zero before using it as argument for ffs().
In case div is zero ffs() will return 0 and thus substracting from
zero will lead to invalid values to be setup in registers.
Fixes: 7a110b9107 ("clk: at91: clk-master: re-factor master clock")
Fixes: 75c88143f3 ("clk: at91: clk-master: add master clock support for SAMA7G5")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-9-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Use DIV_ROUND_CLOSEST_ULL() to avoid any inconsistency b/w the rate
computed in sam9x60_frac_pll_recalc_rate() and the one computed in
sam9x60_frac_pll_compute_mul_frac().
Fixes: 43b1bb4a9b ("clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-8-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add SAMA7G5 to the list of available PMCs such that the suspend/resume
code for clocks to be used on backup mode.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-7-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Improve readability in clk_sama7g5_master_set() by using local
variables.
Suggested-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-6-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
SAMA7G5 has 4 master clocks (MCK1..4) which are controlled though the
register at offset 0x30 (relative to PMC). In the last/first phase of
suspend/resume procedure (which is architecture specific) the parent
of master clocks are changed (via assembly code) for more power saving
(see file arch/arm/mach-at91/pm_suspend.S, macros at91_mckx_ps_enable
and at91_mckx_ps_restore). Thus the macros corresponding to register
at offset 0x30 need to be shared b/w clk-master.c and pm_suspend.S.
commit ec03f18cc2 ("clk: at91: add register definition for sama7g5's
master clock") introduced the proper macros but didn't adapted the
clk-master.c as well. Thus, this commit adapt the clk-master.c to use
the macros introduced in commit ec03f18cc2 ("clk: at91: add register
definition for sama7g5's master clock").
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-5-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Before going to backup mode architecture specific PM code sets the first
word in securam (file arch/arm/mach-at91/pm.c, function at91_pm_begin()).
Thus take this into account when suspending/resuming clocks. This will
avoid executing unnecessary instructions when suspending to non backup
modes.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-3-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
SAMA5D2 and SAMA7G5 have a special power saving mode (backup mode) where
most of the SoC's components are powered off (including PMC). Resuming
from this mode is done with the help of bootloader. Peripherals are not
aware of the power saving mode thus most of them are disabling clocks in
proper suspend API and re-enable them in resume API without taking into
account the previously setup rate. Moreover some of the peripherals are
acting as wakeup sources and are not disabling the clocks in this
scenario, when suspending. Since backup mode cuts the power for
peripherals, in resume part these clocks needs to be re-configured.
The initial PMC suspend/resume code was designed only for SAMA5D2's PMC
(as it was the only one supporting backup mode). SAMA7G supports also
backup mode and its PMC is different (few new functionalities, different
registers offsets, different offsets in registers for each
functionalities). To address both SAMA5D2 and SAMA7G5 PMC add
.save_context()/.resume_context() support to each clocks driver and call
this from PMC driver.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-2-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The Ux500 PRCC (peripheral reset and clock controller) can also
control reset of the IP blocks, not just clocks. As the PRCC is probed
as a clock controller and we have other platforms implementing combined
clock and reset controllers, follow this pattern and implement the PRCC
rest controller as part of the clock driver.
The reset controller needs to be selected from the machine as Ux500 has
traditionally selected its mandatory subsystem prerequisites from there.
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20210921184803.1757916-2-linus.walleij@linaro.org
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
[sboyd@kernel.org: Dropped allocation error message]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This rewrites the ux500/u8500 clock bindings in YAML schema and extends them
with the PRCC reset controller.
The bindings are a bit idiomatic but it just reflects their age, the ux500
platform was used as guinea pig for early device tree conversion of platforms
in 2015. The new subnode for the reset controller follows the pattern of the
old bindings and adds a node with reset-cells for this.
Cc: devicetree@vger.kernel.org
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20210921184803.1757916-1-linus.walleij@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
- Initial clock driver for the Exynos850 SoC
- Refactoring of the CPU clock code and conversion of Exynos5433
CPU clock driver to the platform driver
- A few conversions to devm_platform_ioremap_resource()
- Updates of the Kconfig help text
-----BEGIN PGP SIGNATURE-----
iQJLBAABCAA1FiEEujTcHEnaPOkZ6f78TVsgp4CceosFAmFtzN4XHHMubmF3cm9j
a2lAc2Ftc3VuZy5jb20ACgkQTVsgp4CceosTsQ//Z3xm7iDhI8z5hTrUJb9udp/i
ZWxLxlkq6QevBlVBps85yPhrbKy8UG0ml8Ejt1eVRSvJPdoDhlBJYieVQh7fjHI+
+gApO+VTkr5A9LvpEPUKmn/ybwKrvXRVkgVmjzIigKqRFkOEZU+h8NnhKbwdpK1F
chRqJ3pLEtSewXjyHfi6Kto/jXXcWWnYudXgr+zkFW1tWwJn3h+RH+grH+o30u+X
Qy7MIpnB12BZlFEmnd0Y2mcGnNsSTE1gWaqFds/ZhpYwcehzBoQnOnME6FNBs63S
rRSIUdMH4b+o4waPXkTkj4fu2lRsqPuof6w29KRelBmr+tM5zptMXwTjBA9sn96O
ic4x1eAuetiiAYTqDXIkxRirYmvU2kLfY07xh8x67FEWtkiosYV780wrCrXXPlc1
ebv8uRhFCyrrclUgE0sJTW6zJRNqCB81MbUyXfxOe7Z0Qt128Iec3Nmw8yWCqkIM
zlbGJ+roTdL5GJ6UF4bSHYsY/cvSQdTtTncQ0WY6/zXl19qt3Px0Qe9vW1BEq6G9
sUq1RjeBoyqcYEXGQ/u/f6b45oAW7BadM94S7fRFXkWLBSVpW8toGvRHONEOgSQm
UDmRnDCM5kfelis0OTVOsdgDQdrfIDv7fMTQrmDr22DEjhsqrFlFyudqwCfiT21W
IYJupFi4nJiaI/f6ges=
=uBdF
-----END PGP SIGNATURE-----
Merge tag 'clk-v5.16-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung
Pull Samsung clk driver updates from Sylwester Nawrocki:
- Initial clock driver for the Exynos850 SoC
- Refactoring of the CPU clock code and conversion of Exynos5433
CPU clock driver to the platform driver
- A few conversions to devm_platform_ioremap_resource()
- Updates of the Samsung Kconfig help text
* tag 'clk-v5.16-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: describe drivers in Kconfig
clk: samsung: exynos5433: update apollo and atlas clock probing
clk: samsung: add support for CPU clocks
clk: samsung: Introduce Exynos850 clock driver
dt-bindings: clock: Document Exynos850 CMU bindings
dt-bindings: clock: Add bindings definitions for Exynos850 CMU
clk: samsung: clk-pll: Implement pll0831x PLL type
clk: samsung: clk-pll: Implement pll0822x PLL type
clk: samsung: s5pv210-audss: Make use of devm_platform_ioremap_resource()
clk: samsung: exynos5433: Make use of devm_platform_ioremap_resource()
clk: samsung: exynos4412-isp: Make use of devm_platform_ioremap_resource()
clk: samsung: exynos-audss: Make use of devm_platform_ioremap_resource()
* Update video path realted clocks for meson8
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAmFtXPsACgkQ5vwPHDfy
2oVhsQ/+NsgslSzFF67IDK8l9VX8nn7gLS6cu2MrvKxl45fAds8N++nHtCnYldSE
1Io3sxEnjSZok3bOypJ1ZtcTtl1QdVVEe042l3rs7etGOi8mxFDlcGDnUlIgwgmE
VlTXLEeolw/y2jBz/2KeNrrq170tHSCGqXChiG58cTH7CgK/ZSY1nIRrRtRR6Z0Q
i0JdPONwXc9iGDBCMrGGhQIgobyfRYx7iQvAhLwl62gpLjCuqFjuUzjkQo4BhUi4
FwRWD1evH272FdijYa9s9Wdu6UeT2zen5aQwDxbcItj7H6BxjRVZomSpND7ylH0N
Faidyd/mU1P4ZWqrEh9n2p9qKn0lA1tVDralv3tucubhgxQlT/3TvQ+1LSnVme2n
Vymm+HTpJF22CZ0R7/TjJ5UV3JRlDu7+giR/AJg2UQ4G9NGea9ATp8+Mcy5Pe86k
qX4Wcde16tiXc7Pnr4i8RdRWYLCNOArUNCeEYzjq6eKLko52rISxrenz1/aa1r9k
VCLWceu6b8ru3n8Ms2QR05X0YBaUdIz3Bey4vg1XcSHcYAP6x1yLQjVOKGcSSed8
2o/HEOtDvAk5nZPqkzqptLhjDtTW2e7XA+ODihabV41xE9o99DNgRAUy/bCn/1UP
6KRdLaQ2gg74nxl+7pe84otX/DK5J2C0iMstR7hDXf81WZchrIk=
=kzH8
-----END PGP SIGNATURE-----
Merge tag 'clk-meson-v5.16-1' of https://github.com/BayLibre/clk-meson into clk-amlogic
Pull Amlogic clock driver updates from Jerome Brunet:
- Update video path realted clocks for meson8
* tag 'clk-meson-v5.16-1' of https://github.com/BayLibre/clk-meson:
clk: meson: meson8b: Make the video clock trees mutable
clk: meson: meson8b: Initialize the HDMI PLL registers
clk: meson: meson8b: Add the HDMI PLL M/N parameters
clk: meson: meson8b: Add the vid_pll_lvds_en gate clock
clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel
clk: meson: meson8b: Export the video clocks
support and converting to more helpers.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCYW0qDAAKCRDj7w1vZxhR
xTKDAP9Zxk9u3/DgpxtxbXKSj9qvW0SsWfvXTgRLdLB4ZqTlwQD/e2knKBmkC4vr
AeIsbZLrAhhFAFH36jfWO3maBl2FGwA=
=hAY5
-----END PGP SIGNATURE-----
Merge tag 'sunxi-clk-for-5.16-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clk driver updates from Maxime Ripard:
Our usual PR for the Allwinner SoCs, this time improving the module
support and converting to more helpers.
* tag 'sunxi-clk-for-5.16-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi: sun8i-apb0: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi: sun6i-ar100: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi: sun6i-apb0-gates: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi: sun6i-apb0: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun9i-a80-usb: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun9i-a80-de: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun9i-a80: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun8i-r40: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun8i-de2: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun8i-a83t: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun50i-h6: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun50i-a64: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi: clk-mod0: Make use of the helper function devm_platform_ioremap_resource()
dt-bindings: clocks: Fix typo in the H6 compatible
clk: sunxi-ng: Use a separate lock for each CCU instance
clk: sunxi-ng: Prevent unbinding CCUs via sysfs
clk: sunxi-ng: Unregister clocks/resets when unbinding
clk: sunxi-ng: Add machine dependency to A83T CCU
clk: sunxi-ng: mux: Remove unused 'reg' field
Update clk_composite_determine_rate() to use rate_ops.determine_rate
when available in combination with a mux. So far clk_divider_ops provide
both, .round_rate and .determine_rate. Removing the former would make
clk-composite fail silently for example on Rockchip platforms (which
heavily use composite clocks).
Add support for using rate_ops.determine_rate when either
rate_ops.round_rate is not available or both (.round_rate and
.determine_rate) are provided.
Suggested-by: Alex Bee <knaerzche@gmail.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20211016105022.303413-3-martin.blumenstingl@googlemail.com
Tested-by: Alex Bee <knaerzche@gmail.com>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Commit 69a00fb3d6 ("clk: divider: Implement and wire up
.determine_rate by default") switches clk_divider_ops to implement
.determine_rate by default. This breaks composite clocks with multiple
parents because clk-composite.c does not use the special handling for
mux + divider combinations anymore (that was restricted to rate clocks
which only implement .round_rate, but not .determine_rate).
Alex reports:
This breaks lot of clocks for Rockchip which intensively uses
composites, i.e. those clocks will always stay at the initial parent,
which in some cases is the XTAL clock and I strongly guess it is the
same for other platforms, which use composite clocks having more than
one parent (e.g. mediatek, ti ...)
Example (RK3399)
clk_sdio is set (initialized) with XTAL (24 MHz) as parent in u-boot.
It will always stay at this parent, even if the mmc driver sets a rate
of 200 MHz (fails, as the nature of things), which should switch it
to any of its possible parent PLLs defined in
mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p (see clk-rk3399.c) - which
never happens.
Restore the original behavior by changing the priority of the conditions
inside clk-composite.c. Now the special rate + mux case (with rate_ops
having a .round_rate - which is still the case for the default
clk_divider_ops) is preferred over rate_ops which have .determine_rate
defined (and not further considering the mux).
Fixes: 69a00fb3d6 ("clk: divider: Implement and wire up .determine_rate by default")
Reported-by: Alex Bee <knaerzche@gmail.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20211016105022.303413-2-martin.blumenstingl@googlemail.com
Tested-by: Alex Bee <knaerzche@gmail.com>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Describe better which driver applies to which SoC, to make configuring
kernel for Samsung SoC easier.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20210924133624.112593-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
- Add SPI Multi I/O Bus and SDHI clocks and resets on RZ/G2L,
- Add SPI Multi I/O Bus (RPC) clocks on R-Car V3U,
- Add MediaLB clocks on R-Car H3, M3-W/W+, and M3-N.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYWln3QAKCRCKwlD9ZEnx
cBVCAP9WgdRq0SWdQqGRwUAo9RTmPxy4YmlU9EWifI6qrVc8xgD/cZ2Luew7N6JF
n3jFh9gn8kKfV+gFRTgSGNVgGdOi8Ak=
=7pBq
-----END PGP SIGNATURE-----
Merge tag 'renesas-clk-for-v5.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add SPI Multi I/O Bus and SDHI clocks and resets on RZ/G2L
- Add SPI Multi I/O Bus (RPC) clocks on R-Car V3U
- Add MediaLB clocks on R-Car H3, M3-W/W+, and M3-N
* tag 'renesas-clk-for-v5.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a779[56]x: Add MLP clocks
clk: renesas: r9a07g044: Add SDHI clock and reset entries
clk: renesas: rzg2l: Add SDHI clk mux support
clk: renesas: r8a779a0: Add RPC support
clk: renesas: cpg-lib: Move RPC clock registration to the library
clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller
Use the samsung common clk driver to initialize the apollo and atlas
clocks. This removes their custom init functions and uses the
samsung_cmu_register_one() instead.
Signed-off-by: Will McVicker <willmcvicker@google.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20211014195347.3635601-3-willmcvicker@google.com
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Adds 'struct samsung_cpu_clock' and corresponding CPU clock registration
function to the samsung common clk driver. This allows samsung clock
drivers to register their CPU clocks with the samsung_cmu_register_one()
API.
Currently the exynos5433 apollo and atlas clks have their own custom
init functions to handle registering their CPU clocks. With this patch
we can drop their custom CLK_OF_DECLARE functions and directly call
samsung_cmu_register_one().
Signed-off-by: Will McVicker <willmcvicker@google.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20211014195347.3635601-2-willmcvicker@google.com
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This is the initial implementation adding only basic clocks like UART,
MMC, I2C and corresponding parent clocks. Design is influenced by
Exynos5433 clock driver.
Bus clock is enabled by default (in probe function) for all CMUs except
CMU_TOP, the reasoning is as follows. By default if bus clock has no
users its "enable count" value is 0. It might be actually running if
it's already enabled in bootloader, but then in some cases it can be
disabled by mistake. For example, such case was observed when
dw_mci_probe() enabled the bus clock, then failed to do something and
disabled that bus clock on error path. After that, even the attempt to
read the 'clk_summary' file in DebugFS freezed forever, as CMU bus clock
ended up being disabled and it wasn't possible to access CMU registers
anymore.
To avoid such cases, CMU driver must increment the ref count for that
bus clock by running clk_prepare_enable(). There is already existing
'.clk_name' field in struct samsung_cmu_info, exactly for that reason.
It was added in commit 523d3de41f ("clk: samsung: exynos5433: Add
support for runtime PM"), with next mentioning in commit message:
> Also for each CMU there is one special parent clock, which has to be
> enabled all the time when any access to CMU registers is being done.
But that clock is actually only enabled in Exynos5433 clock driver right
now. So the same code is added to exynos850_cmu_probe() function,
As was described above, it might be helpful not only for PM reasons, but
also to prevent possible erroneous clock gating on error paths.
Another way to workaround that issue would be to use CLOCK_IS_CRITICAL
flag for corresponding gate clocks. But that might be not very good
design decision, as we might still want to disable that bus clock, e.g.
on PM suspend.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20211008154352.19519-6-semen.protsenko@linaro.org
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Commit 419b3ab698 ("clk: versatile: remove dependency on ARCH_*")
made the whole menu of ARM reference clock drivers visible on all
architectures. I can't see how this is an improvement for non-ARM
users. Unless build-testing, there is no point on presenting
ARM-only clock drivers on other architectures.
Signed-off-by: Jean Delvare <jdelvare@suse.de>
Cc: Peter Collingbourne <pcc@google.com>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20210901180953.5bd2a994@endymion
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
For consistency, prefix the ICST config option with CLK as all other
clock source drivers have.
Signed-off-by: Jean Delvare <jdelvare@suse.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20210901180833.4558932d@endymion
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
