Commit Graph

5852 Commits

Author SHA1 Message Date
Andy Shevchenko
f23b373f30 pinctrl: mcp23s08: Drop assignment of default number of OF cells
The GPIO library code will assign default value for number of OF
cells, no need to repeat this in the driver.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220830175850.44770-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-09-03 00:17:35 +02:00
Francesco Dolcini
87c2a29a6b pinctrl: imx8m: kconfig: Depends on SOC_IMX8M
Change PINCTRL_IMX8M* dependency from just ARCH_MXC to SOC_IMX8M,
likewise is done for other PINCTRL_IMX* kconfig. This avoid polluting
the config when SOC_IMX8M is not enabled.

Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/20220830142727.313080-1-francesco.dolcini@toradex.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-31 15:41:21 +02:00
Basavaraj Natikar
3160b37e5c pinctrl: amd: change dev_warn to dev_dbg for additional feature support
Use dev_dbg instead of dev_warn for additional support of pinmux
feature.

Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Link: https://lore.kernel.org/r/20220830110525.1933198-1-Basavaraj.Natikar@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-31 15:38:26 +02:00
Billy Tsai
cf517fef60 pinctrl: aspeed: Force to disable the function's signal
When the driver want to disable the signal of the function, it doesn't
need to query the state of the mux function's signal on a pin. The
condition below will miss the disable of the signal:
Ball | Default | P0 Signal | P0 Expression               | Other
-----+---------+-----------+-----------------------------+----------
 E21   GPIOG0    SD2CLK      SCU4B4[16]=1 & SCU450[1]=1    GPIOG0
-----+---------+-----------+-----------------------------+----------
 B22   GPIOG1    SD2CMD      SCU4B4[17]=1 & SCU450[1]=1    GPIOG1
-----+---------+-----------+-----------------------------+----------
Assume the register status like below:
SCU4B4[16] == 1 & SCU4B4[17] == 1 & SCU450[1]==1
After the driver set the Ball E21 to the GPIOG0:
SCU4B4[16] == 0 & SCU4B4[17] == 1 & SCU450[1]==0
When the driver want to set the Ball B22 to the GPIOG1, the condition of
the SD2CMD will be false causing SCU4B4[17] not to be cleared.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20220818101839.28860-1-billy_tsai@aspeedtech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-31 14:14:31 +02:00
Jilin Yuan
1ebfe7e361 pinctrl: nuvoton: Use 'unsigned int' instead of just 'unsigned'.
'unsigned int' should be clearer than 'unsigned'.

Signed-off-by: Jilin Yuan <yuanjilin@cdjrlc.com>
Link: https://lore.kernel.org/r/20220825124134.30242-1-yuanjilin@cdjrlc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-26 15:46:20 +02:00
Mario Limonciello
76e55d938c pinctrl: amd: Pick some different unicode symbols
Feedback from Kent had showed some better selections for symbols to
use for pinctrl-amd debugfs output.  Adopt some of those instead.

Fixes: e8129a076a ("pinctrl: amd: Use unicode for debugfs output")
Suggested-by: Kent Gibson <warthog618@gmail.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20220823230753.14799-1-mario.limonciello@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-26 15:23:07 +02:00
Stephen Rothwell
bbe2a5d876 pinctrl: fixup for "i2c: Make remove callback return void"
Fix up the build.

Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Link: https://lore.kernel.org/r/20220826152650.2c55e482@canb.auug.org.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-26 15:16:56 +02:00
Hui.Liu
11b918d90a pinctrl: mediatek: add mt8188 driver
Add pinctrl driver support for MediaTek SoC mt8188.

Signed-off-by: Hui.Liu <hui.liu@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220818075012.20880-3-hui.liu@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-25 14:50:44 +02:00
Srinivas Kandagatla
67f40373ee pinctrl: qcom: Add sc8280xp lpass lpi pinctrl driver
Add pinctrl driver to support pin configuration for LPASS
(Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SC8280XP.

This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.

Hardware setup looks like:

    TLMM GPIO[189 - 207] --> LPASS LPI GPIO [0 - 18]

This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220817113747.9111-3-srinivas.kandagatla@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-25 14:32:04 +02:00
Srinivas Kandagatla
ec1652fc4d pinctrl: qcom: Add sm8450 lpass lpi pinctrl driver
Add pinctrl driver to support pin configuration for LPASS
(Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8450.

This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.

Hardware setup looks like:

    TLMM GPIO[165 - 187] --> LPASS LPI GPIO [0 - 22]

This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220817113833.9625-3-srinivas.kandagatla@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-25 14:29:56 +02:00
Andy Shevchenko
39b707fa7a pinctrl: nomadik: Convert drivers to use struct pingroup and PINCTRL_PINGROUP()
The pin control header provides struct pingroup and PINCTRL_PINGROUP() macro.
Utilize them instead of open coded variants in the driver.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220621112904.65674-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-25 13:58:38 +02:00
Andy Shevchenko
0e3db16300 pinctrl: bcm: Convert drivers to use struct pingroup and PINCTRL_PINGROUP()
The pin control header provides struct pingroup and PINCTRL_PINGROUP() macro.
Utilize them instead of open coded variants in the driver.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220620165053.74170-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-25 13:57:00 +02:00
Patrick Rudolph
e6cbbe4294 pinctrl: Add Cypress cy8c95x0 support
Add support for cypress I2C GPIO expanders cy8c9520, cy8c9540 and
cy8c9560. The GPIO expanders feature a PWM mode, thus add it as
pinctrl driver.

The chip features multiple drive modes for each pin when configured
as output and multiple bias settings when configured as input.

Tested all three components and verified that all functionality
is fully working.

Datasheet: https://www.cypress.com/file/37971/download
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Link: https://lore.kernel.org/r/20220816054917.7893-3-patrick.rudolph@9elements.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-25 00:24:32 +02:00
Pali Rohár
599e465d11 pinctrl: armada-37xx: Remove unused macro PIN_GRP()
Macro PIN_GRP() is not used, remove it.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20220805122202.23174-4-pali@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-22 10:46:25 +02:00
Pali Rohár
6b262b32fa pinctrl: armada-37xx: Checks for errors in gpio_request_enable callback
Now when all MPP pins are properly defined and every MPP pin has GPIO
function, always checks for errors in armada_37xx_gpio_request_enable()
function when calling armada_37xx_pmx_set_by_name(). Function
armada_37xx_pmx_set_by_name() should not return "not supported" error
anymore for any GPIO pin when requesting GPIO mode.

Fixes: 87466ccd94 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx")
Signed-off-by: Pali Rohár <pali@kernel.org>
Link: https://lore.kernel.org/r/20220805122202.23174-3-pali@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-22 10:46:25 +02:00
Pali Rohár
2fa9933d68 pinctrl: armada-37xx: Fix definitions for MPP pins 20-22
All 3 MPP pins (20, 21 and 22) can be configured individually and also can
be configured to GPIO functions. Fix definitions for these MPP pins in
existing pin groups. After this change GPIO function can be enabled just
for one of these 3 pins.

Fixes: 87466ccd94 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20220805122202.23174-2-pali@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-22 10:46:25 +02:00
Pali Rohár
0ca6e30e4d pinctrl: armada-37xx: Add missing GPIO-only pins
gpio1_5 and gpio2_2 are GPIO-only pins. Add them into MPP groups table
so they are properly exported as valid pin numbers.

Fixes: 87466ccd94 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20220805122202.23174-1-pali@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-22 10:46:25 +02:00
Jagan Teki
fd4ea48688 pinctrl: rockchip: Add RV1126 pinctrl support
RV1126 has five GPIOs groups - GPIO0 in PD_MMU and GPIO1-4
in PD_BUS.

In GPIO0, up to Lower C group GPIO0_C[3:0] is part of PMU
but rest of the groups from there are part of GRF.

Added pinctrl support for RV1126 and the pull, drv and schmitt
calculations are inferred from [1] authored by Jianqun Xu.

[1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/pinctrl/pinctrl-rockchip.c

Cc: linux-gpio@vger.kernel.org
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20220818124132.125304-8-jagan@edgeble.ai
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-22 09:51:08 +02:00
Linus Torvalds
5e2e7383b5 Pin control bulk changes for v6.0:
Core changes:
 
 - Add PINCTRL_PINGROUP() helper macro (and use it in the AMD driver).
 
 New drivers:
 
 - Intel Meteor Lake support.
 
 - Reneasas RZ/V2M and r8a779g0 (R-Car V4H).
 
 - AXP209 variants AXP221, AXP223 and AXP809.
 
 - Qualcomm MSM8909, PM8226, PMP8074 and SM6375.
 
 - Allwinner D1.
 
 Improvements:
 
 - Proper pin multiplexing in the AMD driver.
 
 - Mediatek MT8192 can use generic drive strength and pin
   bias, then fixes on top plus some I2C pin group fixes.
 
 - Have the Allwinner Sunplus SP7021 use the generic DT schema and
   make interrupts optional.
 
 - Handle Qualcomm SC7280 ADSP.
 
 - Handle Qualcomm MSM8916 CAMSS GP clock muxing.
 
 - High impedance bias on ZynqMP.
 
 - Serialize StarFive access to MMIO.
 
 - Immutable gpiochip for BCM2835, Ingenic, Qualcomm SPMI GPIO.
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Merge tag 'pinctrl-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "Outside the pinctrl driver and DT bindings we hit some Arm DT files,
  patched by the maintainers.

  Other than that it is business as usual.

  Core changes:

   - Add PINCTRL_PINGROUP() helper macro (and use it in the AMD driver).

  New drivers:

   - Intel Meteor Lake support.

   - Reneasas RZ/V2M and r8a779g0 (R-Car V4H).

   - AXP209 variants AXP221, AXP223 and AXP809.

   - Qualcomm MSM8909, PM8226, PMP8074 and SM6375.

   - Allwinner D1.

  Improvements:

   - Proper pin multiplexing in the AMD driver.

   - Mediatek MT8192 can use generic drive strength and pin bias, then
     fixes on top plus some I2C pin group fixes.

   - Have the Allwinner Sunplus SP7021 use the generic DT schema and
     make interrupts optional.

   - Handle Qualcomm SC7280 ADSP.

   - Handle Qualcomm MSM8916 CAMSS GP clock muxing.

   - High impedance bias on ZynqMP.

   - Serialize StarFive access to MMIO.

   - Immutable gpiochip for BCM2835, Ingenic, Qualcomm SPMI GPIO"

* tag 'pinctrl-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (117 commits)
  dt-bindings: pinctrl: qcom,pmic-gpio: add PM8226 constraints
  pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSM
  pinctrl: qcom: sm8250: Fix PDC map
  pinctrl: amd: Fix an unused variable
  dt-bindings: pinctrl: mt8186: Add and use drive-strength-microamp
  dt-bindings: pinctrl: mt8186: Add gpio-line-names property
  ARM: dts: imxrt1170-pinfunc: Add pinctrl binding header
  pinctrl: amd: Use unicode for debugfs output
  pinctrl: amd: Fix newline declaration in debugfs output
  pinctrl: at91: Fix typo 'the the' in comment
  dt-bindings: pinctrl: st,stm32: Correct 'resets' property name
  pinctrl: mvebu: Missing a blank line after declarations.
  pinctrl: qcom: Add SM6375 TLMM driver
  dt-bindings: pinctrl: Add DT schema for SM6375 TLMM
  dt-bindings: pinctrl: mt8195: Use drive-strength-microamp in examples
  Revert "pinctrl: qcom: spmi-gpio: make the irqchip immutable"
  pinctrl: imx93: Add MODULE_DEVICE_TABLE()
  pinctrl: sunxi: Add driver for Allwinner D1
  pinctrl: sunxi: Make some layout parameters dynamic
  pinctrl: sunxi: Refactor register/offset calculation
  ...
2022-08-10 11:01:44 -07:00
Linus Torvalds
5f0848190c platform-drivers-x86 for v6.0-1
Highlights:
  -  Microsoft Surface:
     - SSAM hot unplug support
     - Surface Pro 8 keyboard cover support
     - Tablet mode switch support for Surface Pro 8 and Surface Laptop Studio
  -  thinkpad_acpi: AMD Automatice Mode Transitions (AMT) support
  -  Mellanox:
     - Vulcan chassis COMe NVSwitch management support
     - XH3000 support
  - New generic/shared Intel P2SB (Primary to Sideband) support
  - Lots of small cleanups
  - Various small bugfixes
  - Various new hardware ids / quirks additions
 
 The following is an automated git shortlog grouped by driver:
 
 ACPI:
  -  video: Fix acpi_video_handles_brightness_key_presses()
  -  video: Change how we determine if brightness key-presses are handled
 
 Documentation/ABI:
  -  Add new attributes for mlxreg-io sysfs interfaces
  -  mlxreg-io: Fix contact info
 
 Drop the PMC_ATOM Kconfig option:
  - Drop the PMC_ATOM Kconfig option
 
 EDAC, pnd2:
  -  convert to use common P2SB accessor
  -  Use proper I/O accessors and address space annotation
 
 HID:
  -  surface-hid: Add support for hot-removal
 
 ISST:
  -  PUNIT device mapping with Sub-NUMA clustering
 
 Kconfig:
  -  Remove unnecessary "if X86"
 
 MAINTAINERS:
  -  repair file entry in MICROSOFT SURFACE AGGREGATOR TABLET-MODE SWITCH
 
 Merge tag 'ib-mfd-edac-i2c-leds-pinctrl-platform-watchdog-v5.20' into review-hans:
  - Merge tag 'ib-mfd-edac-i2c-leds-pinctrl-platform-watchdog-v5.20' into review-hans
 
 Move AMD platform drivers to separate directory:
  - Move AMD platform drivers to separate directory
 
 acer-wmi:
  -  Use backlight helper
 
 acer_wmi:
  -  Cleanup Kconfig selects
 
 apple-gmux:
  -  Use backlight helper
 
 asus-wmi:
  -  Add mic-mute LED classdev support
  -  Add key mappings
 
 compal-laptop:
  -  Use backlight helper
 
 efi:
  -  Fix efi_power_off() not being run before acpi_power_off() when necessary
 
 gigabyte-wmi:
  -  add support for B660I AORUS PRO DDR4
 
 hp-wmi:
  -  Ignore Sanitization Mode event
 
 i2c:
  -  i801: convert to use common P2SB accessor
 
 ideapad-laptop:
  -  Add Ideapad 5 15ITL05 to ideapad_dytc_v4_allow_table[]
  -  Add allow_v4_dytc module parameter
 
 intel/pmc:
  -  Add Alder Lake N support to PMC core driver
 
 intel_atomisp2_led:
  -  Also turn off the always-on camera LED on the Asus T100TAF
 
 leds:
  -  simatic-ipc-leds-gpio: Add GPIO version of Siemens driver
  -  simatic-ipc-leds: Convert to use P2SB accessor
 
 mfd:
  -  lpc_ich: Add support for pinctrl in non-ACPI system
  -  lpc_ich: Switch to generic p2sb_bar()
  -  lpc_ich: Factor out lpc_ich_enable_spi_write()
 
 mlx-platform:
  -  Add COME board revision register
  -  Add support for new system XH3000
  -  Introduce support for COMe NVSwitch management module for Vulcan chassis
  -  Add support for systems equipped with two ASICs
  -  Add cosmetic changes for alignment
  -  Make activation of some drivers conditional
 
 p2sb:
  -  Move out of X86_PLATFORM_DEVICES dependency
 
 panasonic-laptop:
  -  Use acpi_video_get_backlight_type()
  -  filter out duplicate volume up/down/mute keypresses
  -  don't report duplicate brightness key-presses
  -  revert "Resolve hotkey double trigger bug"
  -  sort includes alphabetically
  -  de-obfuscate button codes
 
 pinctrl:
  -  intel: Check against matching data instead of ACPI companion
 
 platform/mellanox:
  -  mlxreg-lc: Fix error flow and extend verbosity
  -  mlxreg-io: Add locking for io operations
  -  nvsw-sn2201: fix error code in nvsw_sn2201_create_static_devices()
 
 platform/olpc:
  -  Fix uninitialized data in debugfs write
 
 platform/surface:
  -  gpe: Add support for 13" Intel version of Surface Laptop 4
  -  tabletsw: Fix __le32 integer access
  -  Update copyright year of various drivers
  -  aggregator: Move subsystem hub drivers to their own module
  -  aggregator: Move device registry helper functions to core module
  -  aggregator_registry: Add support for tablet mode switch on Surface Laptop Studio
  -  aggregator_registry: Add support for tablet mode switch on Surface Pro 8
  -  Add KIP/POS tablet-mode switch driver
  -  aggregator: Add helper macros for requests with argument and return value
  -  aggregator: Reserve more event- and target-categories
  -  avoid flush_scheduled_work() usage
  -  aggregator_registry: Add support for keyboard cover on Surface Pro 8
  -  aggregator_registry: Add KIP device hub
  -  aggregator_registry: Change device ID for base hub
  -  aggregator_registry: Generify subsystem hub functionality
  -  aggregator: Add comment for KIP subsystem category
  -  aggregator_registry: Use client device wrappers for notifier registration
  -  aggregator: Allow notifiers to avoid communication on unregistering
  -  aggregator: Allow devices to be marked as hot-removed
  -  aggregator: Allow is_ssam_device() to be used when CONFIG_SURFACE_AGGREGATOR_BUS is disabled
 
 platform/x86/amd/pmc:
  -  Add new platform support
  -  Add new acpi id for PMC controller
 
 platform/x86/dell:
  -  Kconfig: Remove unnecessary "depends on X86_PLATFORM_DEVICES"
 
 platform/x86/intel:
  -  Add Primary to Sideband (P2SB) bridge support
 
 platform/x86/intel/ifs:
  -  Mark as BROKEN
 
 platform/x86/intel/pmt:
  -  telemetry: Fix fixed region handling
 
 platform/x86/intel/vsec:
  -  Fix wrong type for local status variables
  -  Add PCI error recovery support to Intel PMT
  -  Add support for Raptor Lake
  -  Rework early hardware code
 
 pmc_atom:
  -  Fix comment typo
  -  Match all Lex BayTrail boards with critclk_systems DMI table
 
 power/supply:
  -  surface_battery: Use client device wrappers for notifier registration
  -  surface_charger: Use client device wrappers for notifier registration
 
 serial-multi-instantiate:
  -  Sort ACPI IDs by HID
  -  Get rid of redundant 'else'
  -  Use while (i--) pattern to clean up
  -  Improve dev_err_probe() messaging
  -  Drop duplicate check
  -  Improve autodetection
 
 simatic-ipc:
  -  drop custom P2SB bar code
 
 sony-laptop:
  -  Remove useless comparisons in sony_pic_read_possible_resource()
 
 system76_acpi:
  -  Use dev_get_drvdata
 
 thinkpad_acpi:
  -  Enable AMT by default on supported systems
  -  Add support for hotkey 0x131a
  -  Add support for automatic mode transitions
  -  profile capabilities as integer
  -  do not use PSC mode on Intel platforms
  -  Fix a memory leak of EFCH MMIO resource
  -  Replace custom str_on_off() etc
  -  Sort headers for better maintenance
  -  Use backlight helper
 
 tools/power/x86/intel-speed-select:
  -  Remove unneeded semicolon
  -  Fix off by one check
 
 watchdog:
  -  simatic-ipc-wdt: convert to use P2SB accessor
 
 x86-android-tablets:
  -  Fix Lenovo Yoga Tablet 2 830/1050 poweroff again
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Merge tag 'platform-drivers-x86-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86

Pull x86 platform driver updates from Hans de Goede:

 - Microsoft Surface:
     - SSAM hot unplug support
     - Surface Pro 8 keyboard cover support
     - Tablet mode switch support for Surface Pro 8 and Surface Laptop
       Studio

 - thinkpad_acpi:
     - AMD Automatice Mode Transitions (AMT) support

 - Mellanox:
     - Vulcan chassis COMe NVSwitch management support
     - XH3000 support

 - New generic/shared Intel P2SB (Primary to Sideband) support

 - Lots of small cleanups

 - Various small bugfixes

 - Various new hardware ids / quirks additions

* tag 'platform-drivers-x86-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86: (105 commits)
  platform/x86/intel/vsec: Fix wrong type for local status variables
  platform/x86: p2sb: Move out of X86_PLATFORM_DEVICES dependency
  platform/x86: pmc_atom: Fix comment typo
  platform/surface: gpe: Add support for 13" Intel version of Surface Laptop 4
  platform/olpc: Fix uninitialized data in debugfs write
  platform/mellanox: mlxreg-lc: Fix error flow and extend verbosity
  platform/x86: pmc_atom: Match all Lex BayTrail boards with critclk_systems DMI table
  platform/x86: sony-laptop: Remove useless comparisons in sony_pic_read_possible_resource()
  tools/power/x86/intel-speed-select: Remove unneeded semicolon
  tools/power/x86/intel-speed-select: Fix off by one check
  platform/surface: tabletsw: Fix __le32 integer access
  Documentation/ABI: Add new attributes for mlxreg-io sysfs interfaces
  Documentation/ABI: mlxreg-io: Fix contact info
  platform/mellanox: mlxreg-io: Add locking for io operations
  platform/x86: mlx-platform: Add COME board revision register
  platform/x86: mlx-platform: Add support for new system XH3000
  platform/x86: mlx-platform: Introduce support for COMe NVSwitch management module for Vulcan chassis
  platform/x86: mlx-platform: Add support for systems equipped with two ASICs
  platform/x86: mlx-platform: Add cosmetic changes for alignment
  platform/x86: mlx-platform: Make activation of some drivers conditional
  ...
2022-08-04 18:19:14 -07:00
Linus Torvalds
c1c76700a0 SPDX changes for 6.0-rc1
Here is the set of SPDX comment updates for 6.0-rc1.
 
 Nothing huge here, just a number of updated SPDX license tags and
 cleanups based on the review of a number of common patterns in GPLv2
 boilerplate text.  Also included in here are a few other minor updates,
 2 USB files, and one Documentation file update to get the SPDX lines
 correct.
 
 All of these have been in the linux-next tree for a very long time.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'spdx-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx

Pull SPDX updates from Greg KH:
 "Here is the set of SPDX comment updates for 6.0-rc1.

  Nothing huge here, just a number of updated SPDX license tags and
  cleanups based on the review of a number of common patterns in GPLv2
  boilerplate text.

  Also included in here are a few other minor updates, two USB files,
  and one Documentation file update to get the SPDX lines correct.

  All of these have been in the linux-next tree for a very long time"

* tag 'spdx-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx: (28 commits)
  Documentation: samsung-s3c24xx: Add blank line after SPDX directive
  x86/crypto: Remove stray comment terminator
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_406.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_398.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_391.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_390.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_385.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_320.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_319.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_318.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_298.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_292.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_179.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_168.RULE (part 2)
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_168.RULE (part 1)
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_160.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_152.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_149.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_147.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_133.RULE
  ...
2022-08-04 12:12:54 -07:00
Linus Torvalds
cfeafd9466 Driver core / kernfs changes for 6.0-rc1
Here is the set of driver core and kernfs changes for 6.0-rc1.
 
 "biggest" thing in here is some scalability improvements for kernfs for
 large systems.  Other than that, included in here are:
 	- arch topology and cache info changes that have been reviewed
 	  and discussed a lot.
 	- potential error path cleanup fixes
 	- deferred driver probe cleanups
 	- firmware loader cleanups and tweaks
 	- documentation updates
 	- other small things
 
 All of these have been in the linux-next tree for a while with no
 reported problems.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'driver-core-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core

Pull driver core / kernfs updates from Greg KH:
 "Here is the set of driver core and kernfs changes for 6.0-rc1.

  The "biggest" thing in here is some scalability improvements for
  kernfs for large systems. Other than that, included in here are:

   - arch topology and cache info changes that have been reviewed and
     discussed a lot.

   - potential error path cleanup fixes

   - deferred driver probe cleanups

   - firmware loader cleanups and tweaks

   - documentation updates

   - other small things

  All of these have been in the linux-next tree for a while with no
  reported problems"

* tag 'driver-core-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (63 commits)
  docs: embargoed-hardware-issues: fix invalid AMD contact email
  firmware_loader: Replace kmap() with kmap_local_page()
  sysfs docs: ABI: Fix typo in comment
  kobject: fix Kconfig.debug "its" grammar
  kernfs: Fix typo 'the the' in comment
  docs: driver-api: firmware: add driver firmware guidelines. (v3)
  arch_topology: Fix cache attributes detection in the CPU hotplug path
  ACPI: PPTT: Leave the table mapped for the runtime usage
  cacheinfo: Use atomic allocation for percpu cache attributes
  drivers/base: fix userspace break from using bin_attributes for cpumap and cpulist
  MAINTAINERS: Change mentions of mpm to olivia
  docs: ABI: sysfs-devices-soc: Update Lee Jones' email address
  docs: ABI: sysfs-class-pwm: Update Lee Jones' email address
  Documentation/process: Add embargoed HW contact for LLVM
  Revert "kernfs: Change kernfs_notify_list to llist."
  ACPI: Remove the unused find_acpi_cpu_cache_topology()
  arch_topology: Warn that topology for nested clusters is not supported
  arch_topology: Add support for parsing sockets in /cpu-map
  arch_topology: Set cluster identifier in each core/thread from /cpu-map
  arch_topology: Limit span of cpu_clustergroup_mask()
  ...
2022-08-04 11:31:20 -07:00
John Garry
9a206bca23 pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSM
All the many other configs depend on config PINCTRL_MSM, yet for config
PINCTRL_SM8450 we select config PINCTRL_MSM. Make config PINCTRL_SM8450
depend on PINCTRL_MSM to be consistent with the rest.

Signed-off-by: John Garry <john.garry@huawei.com>
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/1658829764-124936-1-git-send-email-john.garry@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-03 20:31:14 +02:00
Jianhua Lu
4b759ca15a pinctrl: qcom: sm8250: Fix PDC map
Fix the PDC mapping for SM8250, gpio39 is mapped to irq73(not irq37).

Fixes: b41efeed507a("pinctrl: qcom: sm8250: Specify PDC map.")
Signed-off-by: Jianhua Lu <lujianhua000@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20220803015645.22388-1-lujianhua000@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-03 20:20:56 +02:00
Mario Limonciello
df91ffe8cb pinctrl: amd: Fix an unused variable
`char *output_enable` is no longer used once switching to unicode
output.

Fixes: e8129a076a ("pinctrl: amd: Use unicode for debugfs output")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20220801144952.141-1-mario.limonciello@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-03 20:14:52 +02:00
Linus Torvalds
9de1f9c8ca Updates for interrupt core and drivers:
core:
    - Fix a few inconsistencies between UP and SMP vs. interrupt affinities
    - Small updates and cleanups all over the place
 
  drivers:
    - New driver for the LoongArch interrupt controller
    - New driver for the Renesas RZ/G2L interrupt controller
 
    - Hotpath optimization for SiFive PLIC
    - Workaround for broken PLIC edge triggered interrupts
 
    - Simall cleanups and improvements as usual
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Merge tag 'irq-core-2022-08-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq updates from Thomas Gleixner:
 "Updates for interrupt core and drivers:

  Core:

   - Fix a few inconsistencies between UP and SMP vs interrupt
     affinities

   - Small updates and cleanups all over the place

  New drivers:

   - LoongArch interrupt controller

   - Renesas RZ/G2L interrupt controller

  Updates:

   - Hotpath optimization for SiFive PLIC

   - Workaround for broken PLIC edge triggered interrupts

   - Simall cleanups and improvements as usual"

* tag 'irq-core-2022-08-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (52 commits)
  irqchip/mmp: Declare init functions in common header file
  irqchip/mips-gic: Check the return value of ioremap() in gic_of_init()
  genirq: Use for_each_action_of_desc in actions_show()
  irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch
  irqchip: Add LoongArch CPU interrupt controller support
  irqchip: Add Loongson Extended I/O interrupt controller support
  irqchip/loongson-liointc: Add ACPI init support
  irqchip/loongson-pch-msi: Add ACPI init support
  irqchip/loongson-pch-pic: Add ACPI init support
  irqchip: Add Loongson PCH LPC controller support
  LoongArch: Prepare to support multiple pch-pic and pch-msi irqdomain
  LoongArch: Use ACPI_GENERIC_GSI for gsi handling
  genirq/generic_chip: Export irq_unmap_generic_chip
  ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback
  APCI: irq: Add support for multiple GSI domains
  LoongArch: Provisionally add ACPICA data structures
  irqdomain: Use hwirq_max instead of revmap_size for NOMAP domains
  irqdomain: Report irq number for NOMAP domains
  irqchip/gic-v3: Fix comment typo
  dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/V2L SoC
  ...
2022-08-01 12:48:15 -07:00
Mario Limonciello
e8129a076a pinctrl: amd: Use unicode for debugfs output
The output is currently split across two lines making it more
difficult to parse unless the newlines are removed between pins
or it's read in by a parser like Libreoffice Calc or Google docs.

To make it easier to follow to the naked eye in a terminal window:
* drop the newline in the middle of pin definitions
* shorten all output using unicode characters
* align all pipe delimitters
* output the same phrase even for disabled functions
  (but with a ∅ character)

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20220722220810.28894-2-mario.limonciello@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-26 09:57:24 +02:00
Mario Limonciello
dc24b7530d pinctrl: amd: Fix newline declaration in debugfs output
Currently the debugfs output for pinctrl-amd puts the first line
combined with "GPIO bank".  This makes it a little harder to process
as the file needs to be manually corrected for the mistake.

Change this to be a new line character instead.

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20220722220810.28894-1-mario.limonciello@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-26 09:57:24 +02:00
Slark Xiao
53dd4188a8 pinctrl: at91: Fix typo 'the the' in comment
Replace 'the the' with 'the' in the comment.

Signed-off-by: Slark Xiao <slark_xiao@163.com>
Link: https://lore.kernel.org/r/20220722092419.77052-1-slark_xiao@163.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-26 09:53:35 +02:00
Xin Gao
c3e4fa4b4e pinctrl: mvebu: Missing a blank line after declarations.
Missing a blank line after declarations.

Signed-off-by: Xin Gao <gaoxin@cdjrlc.com>
Link: https://lore.kernel.org/r/20220719182647.9038-1-gaoxin@cdjrlc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-26 09:37:53 +02:00
Konrad Dybcio
f1a5013f91 pinctrl: qcom: Add SM6375 TLMM driver
Add a driver to control the TLMM block on SM6375. This is an adapted
version of msm-5.4's pinctrl-blair driver.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20220716192900.454653-2-konrad.dybcio@somainline.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-26 09:28:53 +02:00
Marc Zyngier
2bd1753e8c Merge branch irq/misc-5.20 into irq/irqchip-next
* irq/misc-5.20:
  : .
  : Misc IRQ changes for 5.20:
  :
  : - Let irq_set_chip_handler_name_locked() take a const struct irq_chip *
  :
  : - Convert the ocelot irq_chip to being immutable (depends on the above)
  :
  : - Tidy-up the NOMAP irqdomain API variant
  :
  : - Teach action_show() to use for_each_action_of_desc()
  :
  : - Check ioremap() return value in the MIPS GIC driver
  :
  : - Move MMP driver init function declarations into the common .h
  :
  : - The obligatory typo fixes
  : .
  irqchip/mmp: Declare init functions in common header file
  irqchip/mips-gic: Check the return value of ioremap() in gic_of_init()
  genirq: Use for_each_action_of_desc in actions_show()
  irqdomain: Use hwirq_max instead of revmap_size for NOMAP domains
  irqdomain: Report irq number for NOMAP domains
  irqchip/gic-v3: Fix comment typo
  pinctrl: ocelot: Make irq_chip immutable
  genirq: Allow irq_set_chip_handler_name_locked() to take a const irq_chip

Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-07-25 09:45:34 +01:00
Vladimir Oltean
4546760619 pinctrl: armada-37xx: use raw spinlocks for regmap to avoid invalid wait context
The irqchip->irq_set_type method is called by __irq_set_trigger() under
the desc->lock raw spinlock.

The armada-37xx implementation, armada_37xx_irq_set_type(), uses an MMIO
regmap created by of_syscon_register(), which uses plain spinlocks
(the kind that are sleepable on RT).

Therefore, this is an invalid locking scheme for which we get a kernel
splat stating just that ("[ BUG: Invalid wait context ]"), because the
context in which the plain spinlock may sleep is atomic due to the raw
spinlock. We need to go raw spinlocks all the way.

Make this driver create its own MMIO regmap, with use_raw_spinlock=true,
and stop relying on syscon to provide it.

This patch depends on commit 67021f25d9 ("regmap: teach regmap to use
raw spinlocks if requested in the config").

Cc: <stable@vger.kernel.org> # 5.15+
Fixes: 2f22760539 ("pinctrl: armada-37xx: Add irqchip support")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Link: https://lore.kernel.org/r/20220716233745.1704677-3-vladimir.oltean@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-19 00:57:38 +02:00
Vladimir Oltean
984245b66c pinctrl: armada-37xx: make irq_lock a raw spinlock to avoid invalid wait context
The irqchip->irq_set_type method is called by __irq_set_trigger() under
the desc->lock raw spinlock.

The armada-37xx implementation, armada_37xx_irq_set_type(), takes a
plain spinlock, the kind that becomes sleepable on RT.

Therefore, this is an invalid locking scheme for which we get a kernel
splat stating just that ("[ BUG: Invalid wait context ]"), because the
context in which the plain spinlock may sleep is atomic due to the raw
spinlock. We need to go raw spinlocks all the way.

Replace the driver's irq_lock with a raw spinlock, to disable preemption
even on RT.

Cc: <stable@vger.kernel.org> # 5.15+
Fixes: 2f22760539 ("pinctrl: armada-37xx: Add irqchip support")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Link: https://lore.kernel.org/r/20220716233745.1704677-2-vladimir.oltean@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-19 00:56:01 +02:00
Mario Limonciello
41ef3c1a6b pinctrl: Don't allow PINCTRL_AMD to be a module
It was observed that by allowing pinctrl_amd to be loaded
later in the boot process that interrupts sent to the GPIO
controller early in the boot are not serviced.  The kernel treats
these as a spurious IRQ and disables the IRQ.

This problem was exacerbated because it happened on a system with
an encrypted partition so the kernel object was not accesssible for
an extended period of time while waiting for a passphrase.

To avoid this situation from occurring, stop allowing pinctrl-amd
from being built as a module and instead require it to be built-in
or disabled.

Reported-by: madcatx@atlas.cz
Suggested-by: jwrdegoede@fedoraproject.org
Link: https://bugzilla.kernel.org/show_bug.cgi?id=216230
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20220713175950.964-1-mario.limonciello@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-18 12:47:28 +02:00
Linus Walleij
4a2d4e2df5 Revert "pinctrl: qcom: spmi-gpio: make the irqchip immutable"
This reverts commit 7542766e78.

It was noted during follow-up that the approach is incorrect.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-18 11:58:09 +02:00
Fabio Estevam
5d11f8392b pinctrl: imx93: Add MODULE_DEVICE_TABLE()
Pass MODULE_DEVICE_TABLE() so that module autoloading can work.

This also aligns with the other i.MX8 pinctrl drivers.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Link: https://lore.kernel.org/r/20220712115154.2348971-1-festevam@denx.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-18 11:42:21 +02:00
Samuel Holland
0569af4811 pinctrl: sunxi: Add driver for Allwinner D1
This SoC contains a pinctrl with a new register layout. Use the variant
parameter to set the right register offsets. This pinctrl also increases
the number of functions per pin from 8 to 16, taking advantage of all 4
bits in the mux config field (so far, only functions 0-8 and 14-15 are
used). This increases the maximum possible number of functions.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20220713025233.27248-7-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-18 11:39:33 +02:00
Samuel Holland
622b681ef9 pinctrl: sunxi: Make some layout parameters dynamic
Starting with the D1/D1s/T113 SoC, Allwinner changed the layout of the
pinctrl registers. This new layout widens the drive level field, which
affects the pull register offset and the overall bank size.

In order to support multiple register layouts, some of the layout
parameters need to be set based on the pinctrl variant. This requires
passing the pinctrl struct pointer to the register/offset calculation
functions.

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220713025233.27248-6-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-18 11:39:33 +02:00
Samuel Holland
0bb95ae267 pinctrl: sunxi: Refactor register/offset calculation
Starting with the D1/D1s/T113 SoC, Allwinner changed the layout of the
pinctrl registers. This new layout widens the drive level field, which
affects the pull register offset and the overall bank size.

As a first step to support this, combine the register and offset
calculation functions, and refactor the math to depend on one constant
for field widths instead of three. This minimizes the code size impact
of making some of the factors dynamic.

While rewriting these functions, move them to the implementation file,
since that is the only file where they are used. And make the comment
more generic, without mentioning specific offsets/sizes.

The callers are updated to expect a shifted mask, and to use consistent
terminology (reg/shift/mask/val).

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220713025233.27248-5-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-18 11:39:33 +02:00
Samuel Holland
88df36f2e6 pinctrl: sunxi: Support the 2.5V I/O bias mode
H616 and newer SoCs feature a 2.5V I/O bias mode in addition to the
1.8V and 3.3V modes. This mode is entered by selecting the 3.3V level
and disabling the "withstand function".

H616 supports this capability on its main PIO only. A100 supports this
capability on both its PIO and R-PIO.

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220713025233.27248-4-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-18 11:39:33 +02:00
Samuel Holland
fc153c8f28 pinctrl: sunxi: Add I/O bias setting for H6 R-PIO
H6 requires I/O bias configuration on both of its PIO devices.
Previously it was only done for the main PIO.

The setting for Port L is at bit 0, so the bank calculation needs to
account for the pin base. Otherwise the wrong bit is used.

Fixes: cc62383fce ("pinctrl: sunxi: Support I/O bias voltage setting on H6")
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220713025233.27248-3-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-18 11:39:33 +02:00
Robert Marko
6cd81a86ff pinctrl: qcom-pmic-gpio: add support for PMP8074
PMP8074 has 12 GPIO-s with holes on GPIO1 and GPIO12.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Link: https://lore.kernel.org/r/20220711203408.2949888-4-robimarko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-18 11:38:37 +02:00
Dominik Kobinski
eebe11b5bb pinctrl: qcom: spmi-gpio: Add pm8226 compatibility
Add support for pm8226 SPMI GPIOs. The PMIC features
8 GPIOs, with no holes inbetween.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Suggested-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Signed-off-by: Dominik Kobinski <dominikkobinski314@gmail.com>
Link: https://lore.kernel.org/r/20211125215310.62371-1-dominikkobinski314@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-18 11:38:37 +02:00
Andy Shevchenko
03da7f9873 pinctrl: core: Use device_match_of_node() helper
Instead of open coding, use device_match_of_node() helper.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220629115840.16241-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-18 11:38:37 +02:00
Claudiu Beznea
04156e7dd7 pinctrl: at91: remove #ifdef CONFIG_PM
Remove #ifdef CONFIG_PM and use pm_ptr() macro instead.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220704101253.808519-2-claudiu.beznea@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-18 11:38:36 +02:00
Claudiu Beznea
cc701e18a9 pinctrl: at91-pio4: remove #ifdef CONFIG_PM_SLEEP
Remove #ifdef CONFIG_PM_SLEEP and use pm_sleep_ptr() macro instead.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220704101253.808519-1-claudiu.beznea@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-18 11:38:36 +02:00
Horatiu Vultur
ba9c4745fc pinctrl: ocelot: Fix pincfg
The blamed commit changed to use regmaps instead of __iomem. But it
didn't update the register offsets to be at word offset, so it uses byte
offset.
Another issue with the same commit is that it has a limit of 32 registers
which is incorrect. The sparx5 has 64 while lan966x has 77.

Fixes: 076d9e71bc ("pinctrl: ocelot: convert pinctrl to regmap")
Acked-by: Colin Foster <colin.foster@in-advantage.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Link: https://lore.kernel.org/r/20220713193750.4079621-3-horatiu.vultur@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-18 11:22:43 +02:00
Horatiu Vultur
dc62db7138 pinctrl: ocelot: Fix pincfg for lan966x
The blamed commit introduce support for lan966x which use the same
pinconf_ops as sparx5. The problem is that pinconf_ops is specific to
sparx5. More precisely the offset of the bits in the pincfg register are
different and also lan966x doesn't have support for
PIN_CONFIG_INPUT_SCHMITT_ENABLE.

Fix this by making pinconf_ops more generic such that it can be also
used by lan966x. This is done by introducing 'ocelot_pincfg_data' which
contains the offset and what is supported for each SOC.

Fixes: 531d6ab365 ("pinctrl: ocelot: Extend support for lan966x")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220713193750.4079621-2-horatiu.vultur@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-18 11:22:43 +02:00
Michael Walle
51ff93923e pinctrl: ocelot: Make irq_chip immutable
Since recently, the kernel is nagging about mutable irq_chips:

[    2.593426] gpio gpiochip0: (ocelot-gpio): not an immutable chip, please consider fixing it!

Make it const, flag it as IRQCHIP_IMMUTABLE, add the new helper
functions and call the appropriate gpiolib functions.

Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220706151553.1580790-2-michael@walle.cc
2022-07-16 11:47:45 +01:00