Commit Graph

103 Commits

Author SHA1 Message Date
Thierry Reding
a13f1dc4c3 drm/tegra: Use SIMPLE_DEV_PM_OPS
Use this macro to reduce some of the boilerplate.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:24 +02:00
Thierry Reding
cdc630b6c6 drm/tegra: Allow VBLANK to be disabled
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:22 +02:00
Dave Airlie
c861acc4d5 drm/tegra: Changes for v4.2-rc1
This contains a couple of mostly fixes for issues that have crept up in
 recent versions of linux-next. One issue is that DP AUX transactions of
 more than 4 bytes will access the wrong FIFO registers and hence become
 corrupt. Another fix is required to restore functionality of Tegra20 if
 using the GART. The current code expects the IOMMU aperture to be the
 complete 4 GiB address space, whereas the GART on Tegra20 only provides
 a 128 MiB aperture. One more issue with IOMMU support is that on 64-bit
 ARM, swiotlb is the default IOMMU implementation backing the DMA API. A
 side-effect of that is that when dma_map_sg() is called to flush caches
 (yes, this is a bit of a hack, but ARM does not provide a better API),
 swiotlb will immediately run out of memory because its bounce buffer is
 too small to make a framebuffer.
 
 Finally I've included a mostly cosmetic fix that stores register values
 in u32 rather than unsigned long to avoid sign-extension issues on 64-
 bit ARM. This is only a precaution since it hasn't caused any issues
 (yet).
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Merge tag 'drm/tegra/for-4.2-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next

drm/tegra: Changes for v4.2-rc1

This contains a couple of mostly fixes for issues that have crept up in
recent versions of linux-next. One issue is that DP AUX transactions of
more than 4 bytes will access the wrong FIFO registers and hence become
corrupt. Another fix is required to restore functionality of Tegra20 if
using the GART. The current code expects the IOMMU aperture to be the
complete 4 GiB address space, whereas the GART on Tegra20 only provides
a 128 MiB aperture. One more issue with IOMMU support is that on 64-bit
ARM, swiotlb is the default IOMMU implementation backing the DMA API. A
side-effect of that is that when dma_map_sg() is called to flush caches
(yes, this is a bit of a hack, but ARM does not provide a better API),
swiotlb will immediately run out of memory because its bounce buffer is
too small to make a framebuffer.

Finally I've included a mostly cosmetic fix that stores register values
in u32 rather than unsigned long to avoid sign-extension issues on 64-
bit ARM. This is only a precaution since it hasn't caused any issues
(yet).

* tag 'drm/tegra/for-4.2-rc1' of git://anongit.freedesktop.org/tegra/linux:
  drm/tegra: dpaux: Registers are 32-bit
  drm/tegra: gem: Flush pages after allocation
  drm/tegra: gem: Take into account IOMMU aperture
  drm/tegra: dpaux: Fix transfers larger than 4 bytes
2015-06-18 12:53:54 +10:00
Thierry Reding
4553f733c6 drm/tegra: gem: Take into account IOMMU aperture
The IOMMU may not always be able to address 2 GiB of memory. On Tegra20,
the GART supports 32 MiB starting at 0x58000000. Also the aperture on
Tegra30 and later is in fact the full 4 GiB, rather than just 2 GiB as
currently assumed.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-12 16:23:50 +02:00
Mario Kleiner
3790e395b8 drm/tegra: Don't use vblank_disable_immediate on incapable driver.
Tegra would not only need a hardware vblank counter that
increments at leading edge of vblank, but also support
for instantaneous high precision vblank timestamp queries, ie.
a proper implementation of dev->driver->get_vblank_timestamp().

Without these, there can be off-by-one errors during vblank
disable/enable if the scanout is inside vblank at en/disable
time, and additionally clients will never see any useable
vblank timestamps when querying via drmWaitVblank ioctl. This
would negatively affect swap scheduling under X11 and Wayland.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-05-08 20:56:34 +10:00
Dave Airlie
1ddd36eda1 drm/tegra: Changes for v4.1-rc1
Perhaps the most noteworthy change in this set is the implementation of
 a hardware VBLANK counter using host1x syncpoints. The SOR registers can
 now be dumped via debugfs, which can be useful while debugging. The IOVA
 address space maintained by the driver can also be dumped via debugfs.
 
 Other than than, these changes are mostly cleanup work, such as making
 register names more consistent or removing unused code (that was left
 over after the atomic mode-setting conversion). There's also a fix for
 eDP that makes the driver cope with firmware that already initialized
 the display (such as the firmware on the Tegra-based Chromebooks).
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Merge tag 'drm/tegra/for-4.1-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next

drm/tegra: Changes for v4.1-rc1

Perhaps the most noteworthy change in this set is the implementation of
a hardware VBLANK counter using host1x syncpoints. The SOR registers can
now be dumped via debugfs, which can be useful while debugging. The IOVA
address space maintained by the driver can also be dumped via debugfs.

Other than than, these changes are mostly cleanup work, such as making
register names more consistent or removing unused code (that was left
over after the atomic mode-setting conversion). There's also a fix for
eDP that makes the driver cope with firmware that already initialized
the display (such as the firmware on the Tegra-based Chromebooks).

* tag 'drm/tegra/for-4.1-rc1' of git://anongit.freedesktop.org/tegra/linux:
  drm/tegra: sor: Reset during initialization
  drm/tegra: gem: Return 64-bit offset for mmap(2)
  drm/tegra: hdmi: Name register fields consistently
  drm/tegra: hdmi: Resets are synchronous
  drm/tegra: dc: Document tegra_dc_state_setup_clock()
  drm/tegra: dc: Remove unused callbacks
  drm/tegra: dc: Remove unused function
  drm/tegra: dc: Use base atomic state helpers
  drm/atomic: Add helpers for state-subclassing drivers
  drm/tegra: dc: Implement hardware VBLANK counter
  gpu: host1x: Export host1x_syncpt_read()
  drm/tegra: sor: Dump registers via debugfs
  drm/tegra: sor: Registers are 32-bit
  drm/tegra: Provide debugfs file for the IOVA space
  drm/tegra: dc: Check for valid parent clock
2015-04-08 11:13:06 +10:00
Thierry Reding
42e9ce0523 drm/tegra: dc: Implement hardware VBLANK counter
The display controller on Tegra can use syncpoints to count VBLANK
events. syncpoints are 32-bit unsigned integers, so well suited as
VBLANK counters.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02 18:46:21 +02:00
Thierry Reding
28c23373b8 drm/tegra: Provide debugfs file for the IOVA space
The Tegra DRM driver uses a single IO virtual address space for buffer
mappings. Provide a table of the address space usage in debugfs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02 18:46:14 +02:00
Daniel Vetter
1af434a928 drm/atomic-helper: Rename commmit_post/pre_planes
These names only make sense because of backwards compatability with
the order used by the crtc helper library. There's not really any real
requirement in the ordering here.

So rename them to something more descriptive and update the kerneldoc
a bit. Motivated in a discussion with Laurent about how to restore
plane state for dpms for drivers with runtime pm.

v2: Squash in fixup from Stephen Rothwell to fix a conflict with
tegra.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
2015-02-24 01:57:46 +01:00
David Ung
31f40f8652 drm/tegra: Use correct relocation target offsets
When copying a relocation from userspace, copy the correct target
offset.

Signed-off-by: David Ung <davidu@nvidia.com>
Fixes: 961e3beae3 ("drm/tegra: Make job submission 64-bit safe")
Cc: stable@vger.kernel.org
[treding@nvidia.com: provide a better commit message]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27 10:14:59 +01:00
Thierry Reding
359ae687db drm/tegra: Add minimal power management
For now only disable the KMS hotplug polling helper logic upon suspend
and re-enable it on resume.

Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Mark Zhang <markz@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27 10:14:58 +01:00
Thierry Reding
1503ca47d7 drm/tegra: Atomic conversion, phase 3, step 3
Provide a custom ->atomic_commit() implementation which supports async
commits. The generic atomic page-flip helper can use this to implement
page-flipping.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27 10:14:55 +01:00
Thierry Reding
07866963b6 drm/tegra: Atomic conversion, phase 3, step 1
Switch out the regular plane helpers for the atomic plane helpers. Also
use the default atomic helpers to implement the ->atomic_check() and
->atomic_commit() callbacks. The driver now exclusively uses the atomic
interfaces.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27 10:14:51 +01:00
Thierry Reding
9d44189f55 drm/tegra: Atomic conversion, phase 2
Hook up the default ->reset() and ->atomic_duplicate_state() helpers.
This ensures that state objects are properly created and framebuffer
reference counts correctly maintained.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27 10:14:51 +01:00
Thierry Reding
4aa3df7149 drm/tegra: Atomic conversion, phase 1
Implement initial atomic state handling. Hook up the CRTCs, planes' and
connectors' ->atomic_destroy_state() callback to ensure that the atomic
state objects don't leak.

Furthermore the CRTC now implements the ->mode_set_nofb() callback that
is used by new helpers to implement ->mode_set() and ->mode_set_base().
These new helpers also make use of the new plane helper functions which
the driver now provides.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27 10:14:50 +01:00
Thierry Reding
f991421490 drm/tegra: Move tegra_drm_mode_funcs to the core
This structure will be extended using non-framebuffer related callbacks
in subsequent patches, so it should move to a more central location.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27 10:14:44 +01:00
Dan Carpenter
bf19b885f9 drm/tegra: Check for NULL pointer instead of IS_ERR()
iommu_domain_alloc() returns NULL on error, it never returns error
pointers.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27 10:14:36 +01:00
Thierry Reding
f4c5cf88fb gpu: host1x: Provide a proper struct bus_type
Previously the struct bus_type exported by the host1x infrastructure was
only a very basic skeleton. Turn that implementation into a more full-
fledged bus to support proper probe ordering and power management.

Note that the bus infrastructure needs to be available before any of the
drivers can be registered. This is automatically ensured if all drivers
are built as loadable modules (via symbol dependencies). If all drivers
are built-in there are no such guarantees and the link order determines
the initcall ordering. Adjust drivers/gpu/Makefile to make sure that the
host1x bus infrastructure is initialized prior to any of its users (only
drm/tegra currently).

v2: Fix building host1x and tegra-drm as modules
    Reported-by: Dave Airlie <airlied@gmail.com>

Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Mark Zhang <markz@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27 10:09:14 +01:00
Thierry Reding
ed7dae58de drm/tegra: dc: Consistently use the same pipe
The hardware pipe numbers don't always match the DRM CRTC indices. This
can happen for example if the first display controller defers probe,
causing it to be registered with DRM after the second display
controller. When that happens the hardware pipe numbers and DRM CRTC
indices become different. Make sure that the CRTC index is always used
when accessing per-CRTC VBLANK data. This can be ensured by using the
drm_crtc_vblank_*() API, which will do the right thing automatically
given a struct drm_crtc *.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-12-17 14:27:36 +01:00
Thierry Reding
1053f4dd82 drm/tegra: Plug memory leak
Free the DRM device-private memory upon driver unload to make sure the
memory doesn't leak.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:18:32 +01:00
Thierry Reding
df06b759f2 drm/tegra: Add IOMMU support
When an IOMMU device is available on the platform bus, allocate an IOMMU
domain and attach the display controllers to it. The display controllers
can then scan out non-contiguous buffers by mapping them through the
IOMMU.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:14:48 +01:00
Thierry Reding
1d1e6fe9b5 drm/tegra: Fix error handling cleanup
The DRM driver's ->load() implementation didn't do a good job (no job at
all really) cleaning up on failure. Fix that by undoing any prior setup
when an error occurs. This requires a bit of rework to make it possible
to clean up fbdev midway.

This was tested by injecting errors at various points during the
initialization sequence and verifying that error cleanup didn't crash
and no memory leaked (using kmemleak).

Reported-by: Stéphane Marchesin <marcheu@chromium.org>
Reported-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:14:48 +01:00
Thierry Reding
961e3beae3 drm/tegra: Make job submission 64-bit safe
Job submission currently relies on the fact that struct drm_tegra_reloc
and struct host1x_reloc are the same size and uses a simple call to the
copy_from_user() function to copy them to kernel space. This causes the
handle to be stored in the buffer object field, which then needs a cast
to a 32 bit integer to resolve it to a proper buffer object pointer and
store it back in the buffer object field.

On 64-bit architectures that will no longer work, since pointers are 64
bits wide whereas handles will remain 32 bits. This causes the sizes of
both structures to because different and copying will no longer work.

Fix this by adding a new function, host1x_reloc_get_user(), that copies
the structures field by field.

While at it, use substructures for the command and target buffers in
struct host1x_reloc for better readability. Also use unsized types to
make it more obvious that this isn't part of userspace ABI.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-08-04 10:07:36 +02:00
Thierry Reding
bd4f236024 drm/tegra: Allow non-authenticated processes to create buffer objects
This matches what other drivers do for equivalent IOCTLs.

Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-08-04 10:07:36 +02:00
Thierry Reding
7b12908787 drm/tegra: Add SET/GET_FLAGS IOCTLs
The DRM_TEGRA_GEM_SET_FLAGS IOCTL can be used to set the flags of a
buffer object after it has been allocated or imported. Flags associated
with a buffer object can be queried using the DRM_TEGRA_GEM_GET_FLAGS
IOCTL.

Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-08-04 10:07:35 +02:00
Thierry Reding
7678d71fb4 drm/tegra: Add SET/GET_TILING IOCTLs
Currently the tiling parameters of buffer objects can only be set at
allocation time, and only a single tiled mode is supported. This new
DRM_TEGRA_GEM_SET_TILING IOCTL allows more modes to be set and also
allows the tiling mode to be changed after the allocation. This will
enable the Tegra DRM driver to import buffers from a GPU and directly
scan them out by configuring the display controller appropriately.

To complement this, the DRM_TEGRA_GEM_GET_TILING IOCTL can query the
current tiling mode of a buffer object. This is necessary when importing
buffers via handle (as is done in Mesa for example) so that userspace
can determine the proper parameters for the 2D or 3D engines.

Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-08-04 10:07:34 +02:00
Thierry Reding
e2215321ff drm/tegra: Implement race-free hotplug detection
A race condition currently exists on Tegra, where it can happen that a
monitor attached via HDMI isn't detected during the initial FB helper
setup, but the hotplug event happens too early to be processed by the
poll helpers because they haven't been initialized yet. This happens
because on some boards the HDMI driver can control the regulator that
supplies the +5V pin on the HDMI connector. Therefore depending on the
timing between the initialization of the HDMI driver and the rest of
DRM, it's possible that the monitor returns the hotplug signal right
within the window where we would miss it.

Unfortunately, drm_kms_helper_poll_init() will wreak havoc when called
before at least some parts of the FB helpers have been set up.

This commit fixes this by splitting out the minimum of initialization
required to make drm_kms_helper_poll_init() work into a separate
function that can be called early. It is then safe to move all of the
poll helper initialization to an earlier point in time (before the
HDMI output driver has a chance to enable the +5V supply). That way if
the hotplug signal is returned before the initial FB helper setup, the
monitor will be forcefully detected at that point, and if the hotplug
signal is returned after that it will be properly handled by the poll
helpers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-07-08 11:31:36 +10:00
Thierry Reding
9910f5c455 drm/tegra: Remove host1x drm_bus implementation
The DRM core can now cope with drivers that don't have an associated
struct drm_bus, so the host1x implementation is no longer useful.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-05 23:14:46 +02:00
Thierry Reding
fb7be70e73 drm/tegra: hdmi - Add Tegra124 support
Tegra124 is mostly backwards-compatible with Tegra114. However, Tegra124
supports a few more features (e.g. interlacing, ...). Introduce a new
compatible string and TMDS tables to cope with these differences.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-05 23:09:35 +02:00
Dave Airlie
82c68b6ccd drm/tegra: Changes for v3.15-rc1
Implement eDP support for Tegra124 and support the PRIME vmap()/vunmap()
 operations.
 
 A symbol that is required for upcoming V4L2 support is now exported by
 the host1x driver.
 
 Relicense drivers under the GPL v2 for consistency. One exception is the
 public header file, which is relicensed under MIT to abide by the common
 rule.
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Merge tag 'drm/tegra/for-3.15-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next

drm/tegra: Changes for v3.15-rc1

Implement eDP support for Tegra124 and support the PRIME vmap()/vunmap()
operations.

A symbol that is required for upcoming V4L2 support is now exported by
the host1x driver.

Relicense drivers under the GPL v2 for consistency. One exception is the
public header file, which is relicensed under MIT to abide by the common
rule.

* tag 'drm/tegra/for-3.15-rc1' of git://anongit.freedesktop.org/tegra/linux:
  drm/tegra: Use standard GPL v2 license text
  drm/tegra: Relicense under GPL v2
  drm/tegra: Relicense public header under MIT
  drm/tegra: Add eDP support
  gpu: host1x: export host1x_syncpt_incr_max() function
  drm/tegra: prime: Add vmap support
2014-04-05 16:13:08 +10:00
Thierry Reding
6b6b604215 drm/tegra: Add eDP support
Add support for eDP functionality found on Tegra124 and later SoCs. Only
fast link training is currently supported.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-04-04 09:12:50 +02:00
Paul Bolle
6e60163b9d drm/tegra: fix typo 'CONFIG_TEGRA_DRM_FBDEV'
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-02-12 07:50:37 +01:00
Thierry Reding
3800391db1 drm/tegra: Add PRIME support
Implement very basic PRIME support. This currently only works with
buffers that are contiguous in memory and will refuse to import any
physically non-contiguous buffers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-20 15:56:07 +01:00
Thierry Reding
8620fc629a drm/tegra: Add Tegra124 DC support
Tegra124 and later support interlacing, but the driver doesn't support
it yet. Make sure interlacing stays disabled on hardware that supports
it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-20 15:56:06 +01:00
Thierry Reding
60c2f709d9 drm/tegra: Make legacy fbdev support optional
A lot of the modern userspace is capable of working without the legacy
fbdev support. kmscon can be used as a replacement for the framebuffer
console, and KMS X drivers create their own framebuffers.

Most people don't have a system where all of this works yet, though, so
leave support enabled by default.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-20 15:56:05 +01:00
Thierry Reding
dec727399a drm/tegra: Add DSI support
This commit adds support for both DSI outputs found on Tegra. Only very
minimal functionality is implemented, so advanced features like ganged
mode won't work.

Due to the lack of other test hardware, some sections of the driver are
hardcoded to work with Dalmore.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-20 15:56:04 +01:00
Dan Carpenter
9a991600e3 drm/tegra: return -EFAULT if copy_from_user() fails
copy_from_user() returns the number of bytes remaining if it fails, but
we want to return -EFAULT here.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-03 10:14:03 +01:00
Thierry Reding
9b57f5f2c5 drm/tegra: Make tegra_drm_driver static
There is no need to access it from other files now that the driver has
been decoupled from host1x.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-03 10:04:56 +01:00
Thierry Reding
a7ed68fcc7 drm/tegra: Fix address space mismatches
sparse complains because __user annotations aren't placed consistently.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-03 10:04:42 +01:00
Arto Merilainen
c54a169b52 drm/tegra: Deliver syncpoint base to user space
This patch adds a separate ioctl for delivering syncpoint base number
to user space. If the syncpoint does not have an associated base, the
function returns -ENXIO.

Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:55:48 +01:00
Thierry Reding
773af77fc4 drm/tegra: Add support for tiled buffer objects
The gr2d and gr3d engines work more efficiently on buffers with a tiled
memory layout. Allow created buffers to be marked as tiled so that the
display controller can scan them out properly.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:55:46 +01:00
Thierry Reding
5f60ed0d84 drm/tegra: Add 3D support
Initialize and power the 3D unit on Tegra20, Tegra30 and Tegra114 and
register a channel with the Tegra DRM driver so that the unit can be
used from userspace.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:55:45 +01:00
Thierry Reding
c40f0f1afc drm/tegra: Introduce tegra_drm_submit()
Command stream submissions are the same across all devices that expose
a channel to userspace, so move the code into a generic function.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:55:45 +01:00
Mikko Perttunen
7d1d28aca0 drm/tegra: Add Tegra114 HDMI support
Tegra114 TMDS configuration requires a new peak_current field and the
driver current override bit has changed position.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:55:42 +01:00
Thierry Reding
f002abc19a drm/tegra: Properly cleanup and zero out resources
When the DRM driver is unloaded, all the associated resources must be
cleaned up and zeroed out. This is necessary because of the architecture
of the Tegra DRM driver, where not all subdrivers are unloaded along
with the DRM driver. Therefore device-managed managed won't be freed and
memory cannot be assumed to have been cleared (because it hasn't been
reallocated using kzalloc()) by the time the DRM driver is reloaded. It
is therefore necessary to zero out the structures to prevent strange
errors (such as slab corruptions) from occurring.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:55:40 +01:00
Thierry Reding
dee8268f8f drm/tegra: Move driver to DRM tree
In order to make subsystem-wide changes easier, move the Tegra DRM
driver back into the DRM tree.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:55:40 +01:00
Terje Bergstrom
4231c6b01a drm/tegra: Move drm to live under host1x
Make drm part of host1x driver.

Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Erik Faye-Lund <kusmabite@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
2013-04-22 12:39:11 +02:00
Linus Torvalds
fffddfd6c8 Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Pull drm merge from Dave Airlie:
 "Highlights:

   - TI LCD controller KMS driver

   - TI OMAP KMS driver merged from staging

   - drop gma500 stub driver

   - the fbcon locking fixes

   - the vgacon dirty like zebra fix.

   - open firmware videomode and hdmi common code helpers

   - major locking rework for kms object handling - pageflip/cursor
     won't block on polling anymore!

   - fbcon helper and prime helper cleanups

   - i915: all over the map, haswell power well enhancements, valleyview
     macro horrors cleaned up, killing lots of legacy GTT code,

   - radeon: CS ioctl unification, deprecated UMS support, gpu reset
     rework, VM fixes

   - nouveau: reworked thermal code, external dp/tmds encoder support
     (anx9805), fences sleep instead of polling,

   - exynos: all over the driver fixes."

Lovely conflict in radeon/evergreen_cs.c between commit de0babd60d
("drm/radeon: enforce use of radeon_get_ib_value when reading user cmd")
and the new changes that modified that evergreen_dma_cs_parse()
function.

* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (508 commits)
  drm/tilcdc: only build on arm
  drm/i915: Revert hdmi HDP pin checks
  drm/tegra: Add list of framebuffers to debugfs
  drm/tegra: Fix color expansion
  drm/tegra: Split DC_CMD_STATE_CONTROL register write
  drm/tegra: Implement page-flipping support
  drm/tegra: Implement VBLANK support
  drm/tegra: Implement .mode_set_base()
  drm/tegra: Add plane support
  drm/tegra: Remove bogus tegra_framebuffer structure
  drm: Add consistency check for page-flipping
  drm/radeon: Use generic HDMI infoframe helpers
  drm/tegra: Use generic HDMI infoframe helpers
  drm: Add EDID helper documentation
  drm: Add HDMI infoframe helpers
  video: Add generic HDMI infoframe helpers
  drm: Add some missing forward declarations
  drm: Move mode tables to drm_edid.c
  drm: Remove duplicate drm_mode_cea_vic()
  gma500: Fix n, m1 and m2 clock limits for sdvo and lvds
  ...
2013-02-25 16:46:44 -08:00
Thierry Reding
e450fcc666 drm/tegra: Add list of framebuffers to debugfs
This list is most useful to inspect whether framebuffer reference
counting works as expected. The code is loosely based on the i915
implementation.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
2013-02-22 08:21:37 +01:00
Thierry Reding
3c03c46ac8 drm/tegra: Implement page-flipping support
All the necessary support bits like .mode_set_base() and VBLANK are now
available, so page-flipping case easily be implemented on top.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
2013-02-22 08:21:27 +01:00
Thierry Reding
6e5ff99899 drm/tegra: Implement VBLANK support
Implement support for the VBLANK IOCTL. Note that Tegra is somewhat
special in this case because it doesn't use the generic IRQ support
provided by the DRM core (DRIVER_HAVE_IRQ) but rather registers one
interrupt handler for each display controller.

While at it, clean up the way that interrupts are enabled to ensure
that the VBLANK interrupt only gets enabled when required.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
2013-02-22 08:21:23 +01:00
Prashant Gaikwad
61fd290d21 ARM: tegra: migrate to new clock code
Migrate Tegra clock support to drivers/clk/tegra, this involves
moving:
1. definition of tegra_cpu_car_ops to clk.c
2. definition of reset functions to clk-peripheral.c
3. change parent of cpu clock.
4. Remove legacy clock initialization.
5. Initialize clocks using DT.
6. Remove all instance of mach/clk.h

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: use to_clk_periph_gate().]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28 11:19:07 -07:00
Thierry Reding
d8f4a9eda0 drm: Add NVIDIA Tegra20 support
This commit adds a KMS driver for the Tegra20 SoC. This includes basic
support for host1x and the two display controllers found on the Tegra20
SoC. Each display controller can drive a separate RGB/LVDS output.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Mark Zhang <markz@nvidia.com>
Reviewed-by: Mark Zhang <markz@nvidia.com>
Tested-by: Mark Zhang <markz@nvidia.com>
Tested-and-acked-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-11-20 15:43:41 +10:00