- Add CAN and USB1 PWEN pin groups on R-Car H2 and RZ/G1,
- Three more conversion of DT bindings to json-schema,
- Group all Renesas pinctrl drivers and improve visual Kconfig
structure,
- Rename drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas,
- Minor fixes and improvements.
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Merge tag 'renesas-pinctrl-for-v5.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.10
- Add CAN and USB1 PWEN pin groups on R-Car H2 and RZ/G1,
- Three more conversion of DT bindings to json-schema,
- Group all Renesas pinctrl drivers and improve visual Kconfig
structure,
- Rename drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas,
- Minor fixes and improvements.
Most, but not all, Renesas pin control drivers use the "sh-pfc" pin
control framework. As of commit 8449bfa9e6a9f7ec ("pinctrl: sh-pfc:
Collect Renesas related CONFIGs in one place"), the code for this
framework is always built when Renesas SoC pin control support is
enabled, regardless of whether the enabled pin control drivers need it
or not.
Fix this by reintroducing the CONFIG_SH_PFC symbol to control inclusion
of the "sh-pfc" framework and its dependencies, and selecting it when
needed.
This reduces kernel size of a typical RZ/A1 or RZ/A2 kernel by more than
6 resp. 11 KiB.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200909131534.12897-4-geert+renesas@glider.be
The drivers/pinctrl/sh-pfc subdirectory was originally created to group
pin control drivers for various Renesas SuperH and SH-Mobile platforms.
However, the name "sh-pfc" no longer reflects its contents, as the
directory now contains pin control drivers for Renesas SuperH, ARM32,
and ARM64 SoCs.
Hence rename the subdirectory from drivers/pinctrl/sh-pfc to
drivers/pinctrl/renesas, and the related Kconfig symbol from
PINCTRL_SH_PFC to PINCTRL_RENESAS.
Rename the git branch in MAINTAINERS, too, for consistency.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200909131534.12897-3-geert+renesas@glider.be
The RZ/N1 pin control driver does not use pin groups or pin functions,
so there is no need to select GENERIC_PINCTRL_GROUPS or
GENERIC_PINMUX_FUNCTIONS.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200909131534.12897-2-geert+renesas@glider.be
For pins requiring software driven IO output operations, the RZ/A1 Pin
Controller uses either the "output-high" or "output-low" DT property to
enable the corresponding output buffer. The actual line value doesn't
matter, as it is ignored.
Commit 425562429d ("pinctrl: generic: Add output-enable property")
introduced a new DT property for this specific use case.
Update the RZ/A1 Pin Controller DT bindings and driver to use this new
property instead. Preserve backwards compatibility with old DTBs in the
driver, as this comes at a very small cost.
Notes:
- The DT binding examples already used the new property,
- There are no upstream users of the old properties.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Chris Brandt <chris.brandt@renesas.com>
Acked-by: Jacopo Mondi <jacopo@jmondi.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200821111401.4021-1-geert+renesas@glider.be
Now, Renesas Pin Control drivers are under menu, but current
descriptions are not aligned.
This patch aligns them.
- RZ/A2 gpio and pinctrl driver
- RZ/N1 pinctrl driver
- Emma Mobile EV2 pin control support
- R-Mobile APE6 pin control support
- R-Mobile A1 pin control support
- RZ/G1H pin control support
- RZ/G1M pin control support
+ pin control support for RZ/A2
+ pin control support for RZ/N1
+ pin control support for Emma Mobile EV2
+ pin control support for R-Mobile APE6
+ pin control support for R-Mobile A1
+ pin control support for RZ/G1H
+ pin control support for RZ/G1M
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87imd8y4r2.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Renesas related pinctrl CONFIGs are located in many places, which is
confusing.
This patch collects them into the same place, grouped in a new "Renesas
pinctrl drivers" menu.
This patch also moves pinctrl-rz{a1,a2,n1}.c into the sh-pfc folder.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87k0xoy4r7.wl-kuninori.morimoto.gx@renesas.com
[geert: Update path in MAINTAINERS]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
It is "Emma Mobile EV2" not "AV2".
This patch tidies it up.
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87lfi4y4re.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
driver_deferred_probe_check_state() may return -ETIMEDOUT instead of
-EPROBE_DEFER after all built-in drivers have been probed. This can
cause issues for built-in drivers that depend on resources provided by
loadable modules.
One such case happens on Tegra where I2C controllers are used during
early boot to set up the system PMIC, so the I2C driver needs to be a
built-in driver. At the same time, some instances of the I2C controller
depend on the DPAUX hardware for pinmuxing. Since the DPAUX is handled
by the display driver, which is usually not built-in, the pin control
states will not become available until after the root filesystem has
been mounted and the display driver loaded from it.
Fixes: bec6c0ecb2 ("pinctrl: Remove use of driver_deferred_probe_check_state_continue()")
Suggested-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20200825143348.1358679-1-thierry.reding@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
I encountered bug in SX1502 expander driver in 5.7.7. Here is relevant
DTS part:
compatible = "semtech,sx1502q";
gpio4_cfg_pins: gpio2-cfg {
pins = "gpio5";
output-high;
};
And part of OOPS:
[ 0.673996] [<c023cfa6>] (gpiochip_get_data) from [<c023b235>]
(sx150x_gpio_direction_output+0xd)
[ 0.683259] [<c023b235>] (sx150x_gpio_direction_output) from
[<c023b363>] (sx150x_pinconf_set+0x)
[ 0.692796] [<c023b363>] (sx150x_pinconf_set) from [<c0238fef>]
(pinconf_apply_setting+0x39/0x7e)
[ 0.701635] [<c0238fef>] (pinconf_apply_setting) from [<c0236c77>]
(pinctrl_commit_state+0xa5/0x)
[ 0.710648] [<c0236c77>] (pinctrl_commit_state) from [<c0237e03>]
(pinctrl_enable+0xff/0x1d4)
[ 0.719139] [<c0237e03>] (pinctrl_enable) from [<c023b791>]
(sx150x_probe+0x1a3/0x358)
[ 0.727027] [<c023b791>] (sx150x_probe) from [<c02c38bf>]
(i2c_device_probe+0x1bb/0x1dc)
The problem is that sx150x_pinconf_set uses sx150x_gpio_direction_output
but gpio is not setup yet. Patch below fixes it but I'm not sure whether
is it correct.
Link: https://lore.kernel.org/r/f32130bf-cfd4-b1bf-538c-dbc9ee2d947a@eaxlabs.cz
Signed-off-by: Martin DEVERA <devik@eaxlabs.cz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Rockchip pinctrl driver needs to handle information from Devicetree
so only makes sense getting compiled on systems with CONFIG_OF enabled.
This also fixes a problem found by the "kernel-test-robot" when compiling
the driver on test-builds that do not have CONFIG_OF enabled:
drivers/pinctrl/pinctrl-rockchip.c: In function 'rockchip_pinctrl_parse_groups':
>> drivers/pinctrl/pinctrl-rockchip.c:2881:9: error: implicit declaration of function 'pinconf_generic_parse_dt_config'; did you mean 'pinconf_generic_dump_config'? [-Werror=implicit-function-declaration]
2881 | ret = pinconf_generic_parse_dt_config(np_config, NULL,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| pinconf_generic_dump_config
drivers/pinctrl/pinctrl-rockchip.c: In function 'rockchip_gpiolib_register':
>> drivers/pinctrl/pinctrl-rockchip.c:3473:5: error: 'struct gpio_chip' has no member named 'of_node'
3473 | gc->of_node = bank->of_node;
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Link: https://lore.kernel.org/r/20200905214955.907950-1-heiko@sntech.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The only usage of s900_padinfo[] is to assign it to the padinfo field in
the owl_pinctrl_soc_data struct, which is a const pointer. Make it const
to allow the compiler to put it in read-only memory.
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200830224311.36994-4-rikard.falkeborn@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The only usage of s700_padinfo[] is to assign it to the padinfo field in
the owl_pinctrl_soc_data struct, which is a const pointer. Make it const
to allow the compiler to put it in read-only memory.
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200830224311.36994-3-rikard.falkeborn@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The only usage of owl_pinctrl_ops and owl_pinmux_ops is to assign their
addresses to the pctlops and the pmxops fields in the pinctrl_desc struct,
which are const pointers. Make them const to allow the compiler to put them
in read-only memory.
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200830224311.36994-2-rikard.falkeborn@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On page 23 of the datasheet [0] it says "The register remains unchanged
until the interrupt is cleared via a read of INTCAP or GPIO." Include
INTCAPA and INTCAPB registers in precious range, so that they aren't
accidentally cleared when we read via debugfs.
[0] https://ww1.microchip.com/downloads/en/DeviceDoc/20001952C.pdf
Fixes: 8f38910ba4 ("pinctrl: mcp23s08: switch to regmap caching")
Signed-off-by: Thomas Preston <thomas.preston@codethink.co.uk>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20200828213226.1734264-3-thomas.preston@codethink.co.uk
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The mcp23x17_regmap is initialised with structs named "mcp23x16".
However, the mcp23s08 driver doesn't support the MCP23016 device yet, so
this appears to be a typo.
Fixes: 8f38910ba4 ("pinctrl: mcp23s08: switch to regmap caching")
Signed-off-by: Thomas Preston <thomas.preston@codethink.co.uk>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20200828213226.1734264-2-thomas.preston@codethink.co.uk
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Print particular message in each of error case in the ->probe().
While here, use dev_err_probe() for that.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200828103235.78380-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add initial Qualcomm msm8226 pinctrl driver to support pin configuration
with pinctrl framework for msm8226 SoC.
- Initial formatting and style was taken from the msm8x74 pinctrl driver
added by Björn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
Link: https://lore.kernel.org/r/20200716205530.22910-3-bartosz.dudziak@snejp.pl
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Group name 'pcie1' is misleading as it controls only PCIe reset pin. Like
other PCIe groups it should have been called 'pcie1_reset'. But due to
backward compatibility it is not possible to change existing group name.
So just add comment describing this PCIe reset functionality.
Signed-off-by: Pali Rohár <pali@kernel.org>
Link: https://lore.kernel.org/r/20200724132457.7094-1-pali@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The nomadik pinctrl hardware doesn't have any way to
determine if the active pull is up or down. Reading
the bit currently used to report if the pull is up/down
indicates if the gpio input is reading high or low, it
doesn't reflect the pull state.
For this reason change the output from "pull up"/"pull down" to
"pull enabled". This avoids confusing developers who were using
the output to determine what the pull state is.
Signed-off-by: Andrew Halaney <ajhalaney@gmail.com>
Link: https://lore.kernel.org/r/20200806155322.GA25523@ola-jn9phv2.ad.garmin.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
kernel series:
Core changes:
- The GPIO patch "gpiolib: Introduce
for_each_requested_gpio_in_range() macro" was put in an
immutable branch and merged into the pinctrl tree as well.
We see these changes also here.
- Improved debug output for pins used as GPIO.
New drivers:
- Ocelot Sparx5 SoC driver.
- Intel Emmitsburg SoC subdriver.
- Intel Tiger Lake-H SoC subdriver.
- Qualcomm PM660 SoC subdriver.
- Renesas SH-PFC R8A774E1 subdriver.
Driver improvements:
- Linear improvement and cleanups of the Intel drivers for
Cherryview, Lynxpoint, Baytrail etc. Improved locking among
other things.
- Renesas SH-PFC has added support for RPC pins, groups, and
functions to r8a77970 and r8a77980.
- The newere Freescale (now NXP) i.MX8 pin controllers have
been modularized. This is driven by the Google Android
GKI initiative I think.
- Open drain support for pins on the Qualcomm IPQ4019.
- The Ingenic driver can handle both edges IRQ detection.
- A big slew of documentation fixes all over the place.
- A few irqchip template conversions by yours truly.
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Merge tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of the pin control changes for the v5.9 kernel
series:
Core changes:
- The GPIO patch "gpiolib: Introduce for_each_requested_gpio_in_range()
macro" was put in an immutable branch and merged into the pinctrl
tree as well. We see these changes also here.
- Improved debug output for pins used as GPIO.
New drivers:
- Ocelot Sparx5 SoC driver.
- Intel Emmitsburg SoC subdriver.
- Intel Tiger Lake-H SoC subdriver.
- Qualcomm PM660 SoC subdriver.
- Renesas SH-PFC R8A774E1 subdriver.
Driver improvements:
- Linear improvement and cleanups of the Intel drivers for
Cherryview, Lynxpoint, Baytrail etc. Improved locking among other
things.
- Renesas SH-PFC has added support for RPC pins, groups, and
functions to r8a77970 and r8a77980.
- The newere Freescale (now NXP) i.MX8 pin controllers have been
modularized. This is driven by the Google Android GKI initiative I
think.
- Open drain support for pins on the Qualcomm IPQ4019.
- The Ingenic driver can handle both edges IRQ detection.
- A big slew of documentation fixes all over the place.
- A few irqchip template conversions by yours truly.
* tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (107 commits)
dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
pinctrl: stmfx: Use irqchip template
pinctrl: amd: Use irqchip template
pinctrl: mediatek: fix build for tristate changes
pinctrl: samsung: Use bank name as irqchip name
pinctrl: core: print gpio in pins debugfs file
pinctrl: mediatek: add mt6779 eint support
pinctrl: mediatek: add pinctrl support for MT6779 SoC
pinctrl: mediatek: avoid virtual gpio trying to set reg
pinctrl: mediatek: update pinmux definitions for mt6779
pinctrl: stm32: use the hwspin_lock_timeout_in_atomic() API
pinctrl: mcp23s08: Use irqchip template
pinctrl: sx150x: Use irqchip template
dt-bindings: ingenic,pinctrl: Support pinmux/pinconf nodes
pinctrl: intel: Add Intel Emmitsburg pin controller support
pinctl: ti: iodelay: Replace HTTP links with HTTPS ones
Revert "gpio: omap: handle pin config bias flags"
pinctrl: single: Use fallthrough pseudo-keyword
pinctrl: qcom: spmi-gpio: Use fallthrough pseudo-keyword
pinctrl: baytrail: Use fallthrough pseudo-keyword
...
Core changes:
- Introduce the for_each_requested_gpio() macro to help in
dependent code all over the place. Also patch a few locations
to use it while we are at it.
- Split out the sysfs code into its own file.
- Split out the character device code into its own file, then
make a set of refactorings and improvements to this code.
We are setting the stage to revamp the userspace API a bit
in the next cycle.
- Fix a whole slew of kerneldoc that was wrong or missing.
New drivers:
- The PCA953x driver now supports the PCAL9535.
Driver improvements:
- A host of incremental modernizations and improvements to the
PCA953x driver.
- Incremental improvements to the Xilinx Zynq driver.
- Some improvements to the GPIO aggregator driver.
- I ran all over the place switching all threaded and other
drivers requesting their own IRQ while using the core
GPIO IRQ helpers to pass the GPIO irq chip as a template
instead of calling the explicit set-up functions. Next merge
window we may retire the old code altogether.
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Merge tag 'gpio-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij:
"This is the bulk of GPIO changes for the v5.9 kernel cycle.
There is nothing too exciting in it, but a new macro that fixes a
build failure on a minor ARM32 platform that appeared yesterday is
part of it so we better merge it.
Core changes:
- Introduce the for_each_requested_gpio() macro to help in dependent
code all over the place. Also patch a few locations to use it while
we are at it.
- Split out the sysfs code into its own file.
- Split out the character device code into its own file, then make a
set of refactorings and improvements to this code. We are setting
the stage to revamp the userspace API a bit in the next cycle.
- Fix a whole slew of kerneldoc that was wrong or missing.
New drivers:
- The PCA953x driver now supports the PCAL9535.
Driver improvements:
- A host of incremental modernizations and improvements to the
PCA953x driver.
- Incremental improvements to the Xilinx Zynq driver.
- Some improvements to the GPIO aggregator driver.
- I ran all over the place switching all threaded and other drivers
requesting their own IRQ while using the core GPIO IRQ helpers to
pass the GPIO irq chip as a template instead of calling the
explicit set-up functions. Next merge window we may retire the old
code altogether"
* tag 'gpio-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (97 commits)
gpio: wcove: Request IRQ after all initialisation done
gpio: crystalcove: Free IRQ on error path
gpio: pca953x: Request IRQ after all initialisation done
gpio: don't use same lockdep class for all devm_gpiochip_add_data users
gpio: max732x: Use irqchip template
gpio: stmpe: Move chip registration
gpio: rcar: Use irqchip template
gpio: regmap: fix type clash
gpio: Correct kernel-doc inconsistency
gpio: pci-idio-16: Use irqchip template
gpio: pcie-idio-24: Use irqchip template
gpio: 104-idio-16: Use irqchip template
gpio: 104-idi-48: Use irqchip template
gpio: 104-dio-48e: Use irqchip template
gpio: ws16c48: Use irqchip template
gpio: omap: improve coding style for pin config flags
gpio: dln2: Use irqchip template
gpio: sch: Add a blank line between declaration and code
gpio: sch: changed every 'unsigned' to 'unsigned int'
gpio: ich: changed every 'unsigned' to 'unsigned int'
...
This makes the driver use the irqchip template to assign
properties to the gpio_irq_chip instead of using the
explicit calls to gpiochip_irqchip_add_nested() and
gpiochip_set_nested_irqchip(). The irqchip is instead
added while adding the gpiochip.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Cc: Amelie Delaunay <amelie.delaunay@st.com>
Cc: Benjamin Gaignard <benjamin.gaignard@st.com>
Link: https://lore.kernel.org/r/20200721131814.357182-1-linus.walleij@linaro.org
This makes the driver use the irqchip template to assign
properties to the gpio_irq_chip instead of using the
explicit call to gpiochip_irqchip_add().
The irqchip is instead added while adding the gpiochip.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Cc: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Cc: Sandeep Singh <sandeep.singh@amd.com>
Link: https://lore.kernel.org/r/20200722101545.144373-1-linus.walleij@linaro.org
Export mtk_is_virt_gpio() for the case when
CONFIG_PINCTRL_MTK=y
CONFIG_PINCTRL_MTK_V2=y
CONFIG_PINCTRL_MTK_MOORE=y
CONFIG_PINCTRL_MTK_PARIS=m
to fix this build error:
ERROR: modpost: "mtk_is_virt_gpio" [drivers/pinctrl/mediatek/pinctrl-paris.ko] undefined!
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Sean Wang <sean.wang@kernel.org>
Cc: linux-mediatek@lists.infradead.org
Link: https://lore.kernel.org/r/d15827a3-d0c8-e231-9f61-8507b3d7be3a@infradead.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use the bank name as the irqchip name. This name is later visible in
/proc/interrupts, what makes it possible to easily identify each
GPIO interrupt.
/proc/interrupts before this patch:
143: 0 exynos4210_wkup_irq_chip 7 Edge hdmi
144: 0 exynos4210_wkup_irq_chip 6 Level wm8994
145: 1 exynos4210_wkup_irq_chip 7 Edge max77686-pmic, max77686-rtc
146: 1 exynos_gpio_irq_chip 3 Edge 3-0048
/proc/interrupts after this patch:
143: 0 gpx3 7 Edge hdmi
144: 0 gpx3 6 Level wm8994
145: 1 gpx0 7 Edge max77686-pmic, max77686-rtc
146: 1 gpm2 3 Edge 3-0048
Handling of the eint_wake_mask_value has been reworked, because each bank
has now its own exynos_irq_chip structure allocated.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200720145412.24221-1-krzk@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
add driver setting to support mt6779 eint
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Link: https://lore.kernel.org/r/1595503197-15246-6-git-send-email-hanks.chen@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds MT6779 pinctrl driver based on MediaTek pinctrl-paris core.
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Andy Teng <andy.teng@mediatek.com>
Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Link: https://lore.kernel.org/r/1595503197-15246-5-git-send-email-hanks.chen@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
for virtual gpios, they should not do reg setting and
should behave as expected for eint function.
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Link: https://lore.kernel.org/r/1595503197-15246-4-git-send-email-hanks.chen@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use the hwspin_lock_timeout_in_atomic() API which is the most appropriated
here. Indeed:
- hwspin_lock_() is called after spin_lock_irqsave()
- the hwspin_lock_timeout() API relies on jiffies count which won't work
if IRQs are disabled which is the case here.
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Link: https://lore.kernel.org/r/20200615124456.27328-1-alexandre.torgue@st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This makes the driver use the irqchip template to assign
properties to the gpio_irq_chip instead of using the
explicit calls to gpiochip_irqchip_add_nested() and
gpiochip_set_nested_irqchip(). The irqchip is instead
added while adding the gpiochip.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Jan Kundrát <jan.kundrat@cesnet.cz>
Cc: Phil Reid <preid@electromag.com.au>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Jason Kridner <jkridner@gmail.com>
Link: https://lore.kernel.org/r/20200721125223.344411-1-linus.walleij@linaro.org
This makes the driver use the irqchip template to assign
properties to the gpio_irq_chip instead of using the
explicit calls to gpiochip_irqchip_add_nested() and
gpiochip_set_nested_irqchip(). The irqchip is instead
added while adding the gpiochip.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Cc: Peter Rosin <peda@axentia.se>
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200721132537.362160-1-linus.walleij@linaro.org
* New driver for Emmitsburg
* New driver for Tiger Lake-H
* Part 3 of Cherryview driver clean up
* Fix a glitch on Baytrail platforms
The following is an automated git shortlog grouped by driver:
ARM/orion/gpio:
- Make use of for_each_requested_gpio()
at91:
- Make use of for_each_requested_gpio()
baytrail:
- Use fallthrough pseudo-keyword
- Fix pin being driven low for a while on gpiod_get(..., GPIOD_OUT_HIGH)
- Drop no-op ACPI_PTR() call
cherryview:
- Re-use data structures from pinctrl-intel.h (part 3)
- Convert chv_writel() to use chv_padreg()
- Introduce helpers to IO with common registers
- Introduce chv_readl() helper
gpio:
- xra1403: Make use of for_each_requested_gpio()
- mvebu: Make use of for_each_requested_gpio()
gpiolib:
- Introduce for_each_requested_gpio_in_range() macro
intel:
- Add Intel Emmitsburg pin controller support
- Make use of for_each_requested_gpio_in_range()
- Protect IO in few call backs by lock
- Split intel_config_get() to three functions
- Drop the only label in the code for consistency
- Get rid of redundant 'else' in intel_config_set_debounce()
- Make use of IRQ_RETVAL()
- Reduce scope of the lock
- Disable input and output buffer when switching to GPIO
- Allow drivers to define ACPI address space ID
- Allow drivers to define total amount of IRQs per community
lynxpoint:
- Drop no-op ACPI_PTR() call
- Introduce helpers to enable or disable input
- Make use of for_each_requested_gpio()
merrifield:
- Add I²S bus 2 pins to groups and functions
- Update pin names in accordance with official list
tigerlake:
- Add support for Tiger Lake-H
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Merge tag 'intel-pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v5.9-1
* New driver for Emmitsburg
* New driver for Tiger Lake-H
* Part 3 of Cherryview driver clean up
* Fix a glitch on Baytrail platforms
The following is an automated git shortlog grouped by driver:
ARM/orion/gpio:
- Make use of for_each_requested_gpio()
at91:
- Make use of for_each_requested_gpio()
baytrail:
- Use fallthrough pseudo-keyword
- Fix pin being driven low for a while on gpiod_get(..., GPIOD_OUT_HIGH)
- Drop no-op ACPI_PTR() call
cherryview:
- Re-use data structures from pinctrl-intel.h (part 3)
- Convert chv_writel() to use chv_padreg()
- Introduce helpers to IO with common registers
- Introduce chv_readl() helper
gpio:
- xra1403: Make use of for_each_requested_gpio()
- mvebu: Make use of for_each_requested_gpio()
gpiolib:
- Introduce for_each_requested_gpio_in_range() macro
intel:
- Add Intel Emmitsburg pin controller support
- Make use of for_each_requested_gpio_in_range()
- Protect IO in few call backs by lock
- Split intel_config_get() to three functions
- Drop the only label in the code for consistency
- Get rid of redundant 'else' in intel_config_set_debounce()
- Make use of IRQ_RETVAL()
- Reduce scope of the lock
- Disable input and output buffer when switching to GPIO
- Allow drivers to define ACPI address space ID
- Allow drivers to define total amount of IRQs per community
lynxpoint:
- Drop no-op ACPI_PTR() call
- Introduce helpers to enable or disable input
- Make use of for_each_requested_gpio()
merrifield:
- Add I²S bus 2 pins to groups and functions
- Update pin names in accordance with official list
tigerlake:
- Add support for Tiger Lake-H
This driver adds pinctrl/GPIO support for Intel Emmitsburg PCH. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Link: https://lore.kernel.org/r/20200718120807.19714-1-grandmaster@al2klimov.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Add support for the new RZ/G2H (R8A774E1) SoC,
- One more conversion of DT bindings to json-schema,
- Fix RZ/A1 kerneldoc.
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Merge tag 'sh-pfc-for-v5.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v5.9 (take two)
- Add support for the new RZ/G2H (R8A774E1) SoC,
- One more conversion of DT bindings to json-schema,
- Fix RZ/A1 kerneldoc.
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20200713183541.36963-1-grandmaster@al2klimov.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
