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Commit Graph

3045 Commits

Author SHA1 Message Date
Chris Wilson
e6c3a2a6d3 drm/i915: Use an uninterruptible wait for page-flips during modeset
We need to drain the pending flips prior to disabling the pipe during
modeset, and these need to be done in an uninterruptible fashion.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-24 14:19:57 +01:00
Chris Wilson
d3849eded2 drm/i915: Remove unused dev_priv->panel_wants_dither
This is now private to the DVO connector, remove it from the main device
private.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-24 14:19:56 +01:00
Chris Wilson
780f0ca3e0 drm/i915/ringbuffer: Fix sign of ring space.
As we presume space is signed when computing and looking for wrap along,
make it so.

Reported-by: Owain G. Ainsworth <zerooa@googlemail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-24 14:19:55 +01:00
Chris Wilson
3eee1794ac drm/i915: Remove idle timer debugging messages
These have served their purpose and are now just noise in the debug
stream.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-24 14:19:54 +01:00
Chris Wilson
428d2e828c drm/i915/lvds: Probe DDC on creation
Try to validate the panel's connection by writing to address 0xA0.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=18072
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-24 14:19:44 +01:00
Chris Wilson
29e1316ab1 drm/i915/tv: Sleep before checking for state changes.
We need to wait for the PLLs to settle prior to detecting the state
changes. The BIOS writers guide suggests waiting for the next vblank.

Reported-by: Carlos R. Mafra <crmafra2@gmail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-23 11:05:44 +01:00
Chris Wilson
20f0cd55f6 drm/i915: Remove the broken flush_ring from page-flip
This is already performed with the pipelined flush, so by the time we
schedule the flush in the page-flip, the ring is NULL and we OOPs
instead.

Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-23 11:02:55 +01:00
Chris Wilson
6ec3d0c0e9 drm/i915/crt: Use a DDC probe on 0xA0 before load-detect
The BIOS writer's guide suggests that a VGA connection will ACK a write
to address 0xA0 and that this should be used before doing legacy
load-detection. Considering the extreme cost of load-detection,
performing an extra DDC seems a risk worth taking.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-22 18:32:55 +01:00
Chris Wilson
a5cad620b3 drm/i915: Disable "disabled FBC" message when a no-op
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-22 13:15:10 +01:00
Chris Wilson
5c12a07e80 drm/i915: Drop ring->lazy_request
We are not currently using it as intended, so remove the complication.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-22 11:58:55 +01:00
Chris Wilson
2896b53975 drm/i915: Don't offset the pin used for crt_ddc
Previously when converting the GMBUS pin to the GPIO reg, we would
offset the pin by one and then use the look-up table. Now that we first
try to use the GMBUS pin, we no longer need the offset and can use the
value from the VBIOS directly.

Reported-by: Carlos R. Mafra <crmafra2@gmail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-22 11:58:33 +01:00
Chris Wilson
dfaae392f4 drm/i915: Clear the gpu_write_list on resetting write_domain upon hang
Otherwise we will hit a list handling assertion when moving the object
to the inactive list.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-22 10:31:52 +01:00
Chris Wilson
9e0ae53404 drm/i915: Don't overwrite the returned error-code
During i915_gem_create_mmap_offset() if the subsystem reports an error
code, use it.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 15:05:24 +01:00
Chris Wilson
4fd21dc8ee drm/i915/lvds: Unlock the PP register when panel-fitting
As we do not wait for the panel to turn off when we need to adjust the
panel-fitting registers we also need to unlock the PLLs as with the
non-pfit update path.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 14:22:54 +01:00
Chris Wilson
a6b17b4367 drm/i915: Use the correct DPB GMBUS port for GPIOE
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 12:50:13 +01:00
Chris Wilson
cdd5998311 drm/i915: Drop crtc->fb pin on disable.
In order to handle disable_functions() where the framebuffer is
decoupled from the crtc we need to unpin the fb in order to prevent a
leak.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29857
Reported-by: Sitsofe Wheeler <sitsofe@yahoo.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:59:21 +01:00
Chris Wilson
6eecba33f2 drm/i915: Disable output polling across suspend & resume
Suspending (especially hibernating) may take a finite amount of time,
during which a hotplug event may trigger and we will attempt to handle
it with inconsistent state. Disable hotplug polling around suspend and
resume.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30070
Reported-by: Rui Tiago Matos <tiagomatos@gmail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:57:15 +01:00
Daniel Vetter
0af9e92e77 intel-gtt: clean up gtt size reporting
Consolidate everything in intel-gtt.c and also kill the export
of intel_max_stolen.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:40:06 +01:00
Chris Wilson
f13d3f7311 drm/i915: Track pinned objects
Keep a list of pinned objects and display it via debugfs. Now all
objects that exist in the GTT are always tracked on one of the
active, flushing, inactive or pinned lists.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:24:17 +01:00
Chris Wilson
265db9585e drm/i915: Drain any pending flips on the fb prior to unpinning
If we have queued a page flip on the current fb and then request a mode
change, wait until the page flip completes before performing the new
request.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:24:17 +01:00
Chris Wilson
c78ec30bba drm/i915: Merge ring flushing and lazy requests
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:24:16 +01:00
Chris Wilson
53640e1d07 drm/i915: Track gpu fence usage
Track if the gpu requires the fence for the execution of a batch buffer
and so only wait upon the retirement of the object's last rendering
seqno if the fence is in use by the GPU.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:20:54 +01:00
Chris Wilson
ab6f8e3250 drm/i915/ringbuffer: whitespace cleanup
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:20:06 +01:00
Daniel Vetter
a9db5c8fdd drm/i915: drop alignment ringbuffer parameter
Always PAGE_SIZE and only complicates the code.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:20:05 +01:00
Daniel Vetter
fa7ed4d206 drm/i915: don't explicitly initialize ringbuffer members to zero
The compiler happily does that for us.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:20:05 +01:00
Daniel Vetter
7f2ab69913 drm/i915: use new macros to access the ring ctl register
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:20:04 +01:00
Daniel Vetter
570ef60859 drm/i915: use new macros to access the ring head register
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:20:03 +01:00
Daniel Vetter
6c0e1c556e drm/i915: use new macros to access the ring start register
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:20:02 +01:00
Daniel Vetter
870e86ddc2 drm/i915: use new macros to access the ring tail register
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:20:02 +01:00
Daniel Vetter
333e9fe94d drm/i915: add relative ring register macros
Documentation explicitly mentions that the ring registers are
designed to have the same offsets relative to a base registers.

Use this to fight the code beaurocratic in intel_ringbuffer.c.

No code changes in this patch, just the new definitions.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:20:01 +01:00
Daniel Vetter
b8aea0c800 drm/i915: kill duplicated/unneeded register defines
This looks like a copy-paste remnant from the i810. All the regs
that are actually used are already defined somewhere else in i915_reg.h!

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:20:00 +01:00
Chris Wilson
c7f9f9a8b8 drm/i915: Use ring->flush() instead of MI_FLUSH
Use the ring abstraction to hide the details of having choose the
appropriate flushing method.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:59 +01:00
Chris Wilson
e070868ef2 drm/i915/ringbuffer: Mark the initialisation structs as constant.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:58 +01:00
Xiang, Haihao
881f47b647 drm/i915: add a new BSD ring buffer for Sandybridge
This ring buffer is used for video decoding/encoding on Sandybridge.

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:57 +01:00
Chris Wilson
a3f07cd53e drm/i915/ringbuffer: Implement advance using set_tail
As noted by Zhenyu, we can now simply replace the existing advance hook
by calling the new set_tail function pointer directly.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:57 +01:00
Xiang, Haihao
d46eefa297 drm/i915: add set_tail hook in struct intel_ring_buffer
This is prepared for video codec ring buffer on Sandybridge. It is
needed to read/write more than one register to move the tail pointer of
the video codec ring on Sandybridge.

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:56 +01:00
Xiang, Haihao
5c1143bbec drm/i915: do not export the instances of struct intel_ring_buffer
Introduce intel_init_render_ring_buffer(), intel_init_bsd_ring_buffer
for ring initialization.

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:55 +01:00
Xiang, Haihao
92f49d9cec drm/i915: fix HAS_BSD with a device info flag
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:54 +01:00
Chris Wilson
f803aa5532 drm/i915: Clean up bo lists on all hung gpus
Previously we only tidied up the active bo lists for chipsets were we
would attempt to reset the GPU. However, this action is necessary for
the system to continue and reclaim the dead bo for all chipsets.

Pointed out, in passing, by Owain Ainsworth.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:54 +01:00
Chris Wilson
77f0123022 drm/i915: Clear GPU read domains on reset
Clear the GPU read domain for the inactive objects on a reset so that
they are correctly invalidated on reuse.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:53 +01:00
Chris Wilson
9375e446e7 drm/i915: Clear flushing lists on GPU reset
Owain Ainsworth noticed that the reset code failed to clear the flushing
list leaving the driver in an inconsistent state following a hung GPU.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:52 +01:00
Chris Wilson
9220434a87 drm/i915: Only emit a flush request on the active ring.
When flushing the GPU domains,we emit a flush on *both* rings, even
though they share a unified cache. Only emit the flush on the currently
active ring.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:51 +01:00
Chris Wilson
b84d5f0c22 drm/i915: Inline i915_gem_ring_retire_request()
Change the semantics to retire any buffer older than the current seqno
rather than repeatedly calling calling the function to retire the
buffer at the head of the list matching the request seqno.

Whilst this should have no semantic impact on the implementation, Daniel
was wondering if there was a bug where we might miss a retirement and so
end up with a continually growing active list.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:50 +01:00
Chris Wilson
82690bba37 drm/i915/debug: Dump BSD ring buffers to debugfs
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:49 +01:00
Chris Wilson
9fd981413e drm/i915: After a reset perform a forced modeset
On more recent chipsets, restoring the display is not as simple as
writing a few registers, so force a full modeset of the current
configuration in order to retrain the display link.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:49 +01:00
Kenneth Graunke
0573ed4a94 drm/i915: Add support for GPU soft reset on Ironlake.
Ironlake's graphics reset register has to be accessed via the MCHBAR,
rather than via PCI config space, which requires some refactoring.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:48 +01:00
Kenneth Graunke
eeccdcac07 drm/i915: Rename graphics reset registers.
The graphics domains are listed as GRDOM in the documentation, and the
GDRST PCI config register (0xc0) is only valid on I965 and GM45.  Newer
chips (like Sandy Bridge) have a different GDRST.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:47 +01:00
Kenneth Graunke
f49f058619 drm/i915: Actually set the reset bit in i965_reset.
Previously, it was only being set if passed GDRST_FULL - but the only
caller passed GDRST_RENDER.  So the hardware never actually reset.
The comments also did not match the code.

Instead, just set the reset bit regardless of what flags were passed.
The GPU now resets correctly on my GM45.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:46 +01:00
Chris Wilson
a6c45cf013 drm/i915: INTEL_INFO->gen supercedes i8xx, i9xx, i965g
Avoid confusion between i965g meaning broadwater and the gen4+ chipset
families.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:45 +01:00
Chris Wilson
219adae138 drm/i915: Cache LVDS EDID
We assume that the panel is permenantly connected and that the EDID data
is consistent from boot, so simply cache the whole EDID for the panel.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:45 +01:00