In some cases reset_sccr1() can be called when no message available.
This means that there is no associated chip to receive that message
and hence no threshold needs to be set. Adapt the function to such
cases.
Fixes: 3bbdc08326 ("spi: pxa2xx: Reuse int_stop_and_reset() in couple of places")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20210721121520.62605-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
The security restrictions on the FSI-attached SPI controllers have
been applied universally to all controllers, so the controller can no
longer transfer more than 8 bytes for one transfer. Refactor the driver
to remove the looping and support for larger transfers, and remove the
"restricted" compatible string, as all the controllers are now
considered restricted.
Eddie James (2):
spi: fsi: Reduce max transfer size to 8 bytes
dt-bindings: fsi: Remove ibm,fsi2spi-restricted compatible
.../devicetree/bindings/fsi/ibm,fsi2spi.yaml | 1 -
drivers/spi/spi-fsi.c | 125 +++---------------
2 files changed, 22 insertions(+), 104 deletions(-)
--
2.27.0
For each usage of fifo_words it is clear if ->dynamic_burst is true or
not. This can be used to simplify the function a bit.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/20210716173927.2050620-1-u.kleine-koenig@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
Reuse int_stop_and_reset() in couple of places.
While at it, change the order of the int_stop_and_reset() and pxa2xx_spi_off()
to be in align with the similar flow in int_error_stop().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20210719074842.36060-3-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
The comment in setup_fifo_xfer() about setting the watermark wasn't
quite proper grammar and also stopped making sense around commit
6d66507d9b ("spi: spi-geni-qcom: Don't wait to start 1st transfer if
transmitting"). After that commit we actually start the transfer
_before_ the watermark interrupt comes.
I don't think the comment really has any value anymore. We've already
got a comment when we grab the spinlock saying that our interrupt can
come any time as a result of the things in the locked section. Let's
just remove it.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210712085010.1.Ie3bb9f9d30d6475bb75251d32635194c1c72b9ee@changeid
Signed-off-by: Mark Brown <broonie@kernel.org>
This patch support tick_delay setting, some users need use
high-speed spi speed, which can use tick_delay to tuning spi clk timing.
Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
Link: https://lore.kernel.org/r/20210713114048.29509-1-mason.zhang@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This series contains fixes & cleanup mainly regarding fifo
and the way end of transfer triggered, when used with or
without DMA.
An additional patch cleans up the pm_runtime calls and another
one enables the autosuspend.
v2: - split pm_runtime fix patch into two
- correct revert commit subject line
Alain Volmat (6):
spi: stm32: fixes pm_runtime calls in probe/remove
spi: stm32: enable pm_runtime autosuspend
spi: stm32h7: fix full duplex irq handler handling
spi: stm32: Revert "properly handle 0 byte transfer"
spi: stm32h7: don't wait for EOT and flush fifo on disable
spi: stm32: finalize message either on dma callback or EOT
Amelie Delaunay (1):
spi: stm32h7: rework rx fifo read function
drivers/spi/spi-stm32.c | 146 +++++++++++++++++-----------------------
1 file changed, 61 insertions(+), 85 deletions(-)
--
2.25.1
This patch add no_need_unprepare support for spi, if spi src clk is
MAIN PLL, it can keep the clk_prepare and will not cause low power
issue. So we no need do clk_prepare/clk_unprepare in runtime pm,
and it will get better performance, because clk_prepare has called
mutex lock.
In the same way,
clk_get_rate also has called mutex lock, so we moved it to spi_probe.
Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
Link: https://lore.kernel.org/r/20210629100814.21402-1-mason.zhang@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Depending on the usage, it is necessary to perform the finalize
message operation either upon receiving the EOT interruption,
eiher upon receiving the DMA callback. Indeed, when relying
on DMA, even if the SPI EOT IT has been received, it is
necessary to wait for the end of the DMA RX transaction before
accessing to the data.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Link: https://lore.kernel.org/r/1625646426-5826-8-git-send-email-alain.volmat@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
In nominal cases, disable is called as part of the unprepare_message,
after receiving a EOT and after receiving all data so it doesn't
make sense to check for EOT and empty the FIFO.
Moreover, at the end of the disable, the SPI is disable (SPE) leading
to clear of all internal FIFO, leaving the IP in a known status.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Link: https://lore.kernel.org/r/1625646426-5826-7-git-send-email-alain.volmat@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Remove flush parameter and check RXWNE or RXPLVL when end of transfer
flag is set.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Link: https://lore.kernel.org/r/1625646426-5826-6-git-send-email-alain.volmat@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
0 byte transfer handling is now done within the core in code added
by commit b306320322 ("spi: Skip zero-length transfers in spi_transfer_one_message()")
This reverts commit 2269f5a8b1 ("spi: stm32: properly handle 0 byte transfer")
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Link: https://lore.kernel.org/r/1625646426-5826-5-git-send-email-alain.volmat@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Add pm_runtime calls in probe/probe error path and remove
in order to be consistent in all places in ordering and
ensure that pm_runtime is disabled prior to resources used
by the SPI controller.
This patch also fixes the 2 following warnings on driver remove:
WARNING: CPU: 0 PID: 743 at drivers/clk/clk.c:594 clk_core_disable_lock+0x18/0x24
WARNING: CPU: 0 PID: 743 at drivers/clk/clk.c:476 clk_unprepare+0x24/0x2c
Fixes: 038ac869c9 ("spi: stm32: add runtime PM support")
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Link: https://lore.kernel.org/r/1625646426-5826-2-git-send-email-alain.volmat@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Since 00b80ac935 ("spi: imx: mx51-ecspi: Move some initialisation to
prepare_message hook."), the MX51_ECSPI_CONFIG write no longer happens
in prepare_transfer hook, but rather in prepare_message hook, however
the MX51_ECSPI_CONFIG delay is still left in prepare_transfer hook and
thus has no effect. This leads to low bus frequency operation problems
described in 6fd8b8503a ("spi: spi-imx: Fix out-of-order CS/SCLK
operation at low speeds") again.
Move the MX51_ECSPI_CONFIG write delay into the prepare_message hook
as well, thus reinstating the low bus frequency fix.
Fixes: 00b80ac935 ("spi: imx: mx51-ecspi: Move some initialisation to prepare_message hook.")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20210703022300.296114-1-marex@denx.de
Signed-off-by: Mark Brown <broonie@kernel.org>
In case of Full-Duplex mode, DXP flag is set when RXP and TXP flags are
set. But to avoid 2 different handlings, just add TXP and RXP flag in
the mask instead of DXP, and then keep the initial handling of TXP and
RXP events.
Also rephrase comment about EOTIE which is one of the interrupt enable
bits. It is not triggered by any event.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Reviewed-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/1625042723-661-3-git-send-email-alain.volmat@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Some controllers like qcom geni need the parent device to be used for
dma mapping, so add a dma_map_dev field and let drivers fill this to be
used as mapping device
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210625052213.32260-4-vkoul@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
There is an assignment of ancillary->mode to itself which looks
dubious since the proceeding comment states that the speed and
mode is taken over from the SPI main device, indicating that
ancillary->mode should assigned using the value spi->mode.
Fix this.
Addresses-Coverity: ("Self assignment")
Fixes: 0c79378c01 ("spi: add ancillary device support")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20210623172300.161484-1-colin.king@canonical.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Changes in v10:
- The internal CS inactive function is only supported after VER 0x00110002
Changes in v9:
- Conver to use CS GPIO description
Changes in v8:
- There is a problem with the version 7 mail format. resend it
Changes in v7:
- Fall back "rockchip,rv1126-spi" to "rockchip,rk3066-spi"
Changes in v6:
- Consider to compatibility, the "rockchip,rk3568-spi" is removed in
Series-changes v5, so the commit massage should also remove the
corresponding information
Changes in v5:
- Change to leave one compatible id rv1126, and rk3568 is compatible
with rv1126
Changes in v4:
- Adjust the order patches
- Simply commit massage like redundancy "application" content
Changes in v3:
- Fix compile error which is find by Sascha in [v2,2/8]
Jon Lin (6):
dt-bindings: spi: spi-rockchip: add description for rv1126
spi: rockchip: add compatible string for rv1126
spi: rockchip: Set rx_fifo interrupt waterline base on transfer item
spi: rockchip: Wait for STB status in slave mode tx_xfer
spi: rockchip: Support cs-gpio
spi: rockchip: Support SPI_CS_HIGH
.../devicetree/bindings/spi/spi-rockchip.yaml | 1 +
drivers/spi/spi-rockchip.c | 55 ++++++++++++++-----
2 files changed, 41 insertions(+), 15 deletions(-)
--
2.17.1
dmaengine_terminate_all() is deprecated in favor of explicitly saying if
it should be sync or async. Here, we want dmaengine_terminate_sync()
because there is no other synchronization code in the driver to handle
an async case.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210623095843.3228-3-wsa+renesas@sang-engineering.com
Signed-off-by: Mark Brown <broonie@kernel.org>
dmaengine_terminate_all() is deprecated in favor of explicitly saying if
it should be sync or async. Here, we want dmaengine_terminate_sync()
because there is no other synchronization code in the driver to handle
an async case.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210623095843.3228-2-wsa+renesas@sang-engineering.com
Signed-off-by: Mark Brown <broonie@kernel.org>
The current sun6i SPI implementation initializes the transfer too early,
resulting in SCK going high before the transfer. When using an additional
(gpio) chipselect with sun6i, the chipselect is asserted at a time when
clock is high, making the SPI transfer fail.
This is due to SUN6I_GBL_CTL_BUS_ENABLE being written into
SUN6I_GBL_CTL_REG at an early stage. Moving that to the transfer
function, hence, right before the transfer starts, mitigates that
problem.
Fixes: 3558fe900e (spi: sunxi: Add Allwinner A31 SPI controller driver)
Signed-off-by: Mirko Vogt <mirko-dev|linux@nanl.de>
Signed-off-by: Ralf Schlatterbeck <rsc@runtux.com>
Link: https://lore.kernel.org/r/20210614144507.y3udezjfbko7eavv@runtux.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Introduce support for ancillary devices, similar to existing
implementation for I2C. This is useful for devices having
multiple chip-selects, for example some microcontrollers
provide a normal SPI interface and a flashing SPI interface.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20210621175359.126729-2-sebastian.reichel@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Add OF support as already done for ACPI to take driver
MODULE_DEVICE_TABLE(of, ..) into account.
For example with this change a spi nor device MODALIAS changes from:
MODALIAS=spi:spi-nor
to
MODALIAS=of:Nspi-flashT(null)Cjedec,spi-nor
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Link: https://lore.kernel.org/r/20210525091003.18228-1-m.felsch@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
In meson_spifc_probe function, when enable the device pclk clock is
error, it should use clk_disable_unprepare to release the core clock.
Signed-off-by: zpershuai <zpershuai@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/1623562172-22056-1-git-send-email-zpershuai@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Fix the following make W=1 warning:
drivers/spi/spi-mem.c:819: warning: expecting prototype for spi_mem_driver_unregister_with_owner(). Prototype was for spi_mem_driver_unregister() instead
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20210601120721.3198488-1-yangyingliang@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Move the register operation after the clock enable, otherwise system
will stuck when this driver probe.
Fixes: 71d80563b0 ("spi: spi-nxp-fspi: fix fspi panic by unexpected interrupts")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Link: https://lore.kernel.org/r/1623317073-25158-1-git-send-email-haibo.chen@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
No one seems to be using this global and exported function, so remove it
as it is no longer needed.
Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Link: https://lore.kernel.org/r/20210609071918.2852069-1-gregkh@linuxfoundation.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Commit 4782c0a5dd ("clk: tegra: Don't deassert reset on enabling
clocks") removed some legacy code for handling resets on Tegra from
within the Tegra clock code. This exposed an issue in the Tegra20 slink
driver where the SPI controller reset was not being deasserted as needed
during probe. This is causing the Tegra30 Cardhu platform to hang on
boot. Fix this by ensuring the SPI controller reset is deasserted during
probe.
Fixes: 4782c0a5dd ("clk: tegra: Don't deassert reset on enabling clocks")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://lore.kernel.org/r/20210608071518.93037-1-jonathanh@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This patch uses debugfs_regset32 interface to create the registers dump
file. Use it instead of creating a generic debugfs file with manually
written read callback function.
With these entries, users can check all the SPI controller registers
during run time.
Signed-off-by: Jay Fang <f.fangjian@huawei.com>
Link: https://lore.kernel.org/r/1622789718-13977-1-git-send-email-f.fangjian@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Fix the following compilation warning using W=1 build:
arm-linux-gnueabi-ld: drivers/spi/spi-stm32-qspi.o: in function `stm32_qspi_poll_status':
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20210604075009.25914-1-patrice.chotard@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Patrice Chotard <patrice.chotard@foss.st.com>:
From: Patrice Chotard <patrice.chotard@foss.st.com>
This series adds support for the spi_mem_poll_status() spinand
interface.
Some QSPI controllers allows to poll automatically memory
status during operations (erase, read or write). This allows to
offload the CPU for this task.
STM32 QSPI is supporting this feature, driver update are also
part of this series.
Changes in v5:
- Update spi_mem_read_status() description.
- Update poll_status() description API by indicating that data buffer is
filled with last status value.
- Update timeout parameter by timeout_ms in spi_mem_poll_status() prototype.
- Remove parenthesys arount -EINVAL in spi_mem_poll_status().
- Add missing spi_mem_supports_op() call in stm32_qspi_poll_status().
- Add Boris Reviewed-by for patch 1 and 2.
Changes in v4:
- Remove init_completion() from spi_mem_probe() added in v2.
- Add missing static for spi_mem_read_status().
- Check if operation in spi_mem_poll_status() is a READ.
- Update patch 2 commit message.
- Add comment which explains how delays has been calculated.
- Rename SPINAND_STATUS_TIMEOUT_MS to SPINAND_WAITRDY_TIMEOUT_MS.
Chnages in v3:
- Add spi_mem_read_status() which allows to read 8 or 16 bits status.
- Add initial_delay_us and polling_delay_us parameters to spi_mem_poll_status().
and also to poll_status() callback.
- Move spi_mem_supports_op() in SW-based polling case.
- Add delay before invoquing read_poll_timeout().
- Remove the reinit/wait_for_completion() added in v2.
- Add initial_delay_us and polling_delay_us parameters to spinand_wait().
- Add SPINAND_READ/WRITE/ERASE/RESET_INITIAL_DELAY_US and
SPINAND_READ/WRITE/ERASE/RESET_POLL_DELAY_US defines.
- Remove spi_mem_finalize_op() API added in v2.
Changes in v2:
- Indicates the spi_mem_poll_status() timeout unit
- Use 2-byte wide status register
- Add spi_mem_supports_op() call in spi_mem_poll_status()
- Add completion management in spi_mem_poll_status()
- Add offload/non-offload case management in spi_mem_poll_status()
- Optimize the non-offload case by using read_poll_timeout()
- mask and match stm32_qspi_poll_status()'s parameters are 2-byte wide
- Make usage of new spi_mem_finalize_op() API in
stm32_qspi_wait_poll_status()
Patrice Chotard (3):
spi: spi-mem: add automatic poll status functions
mtd: spinand: use the spi-mem poll status APIs
spi: stm32-qspi: add automatic poll status feature
drivers/mtd/nand/spi/core.c | 45 +++++++++++++------
drivers/spi/spi-mem.c | 86 ++++++++++++++++++++++++++++++++++++
drivers/spi/spi-stm32-qspi.c | 86 ++++++++++++++++++++++++++++++++----
include/linux/mtd/spinand.h | 22 +++++++++
include/linux/spi/spi-mem.h | 16 +++++++
5 files changed, 234 insertions(+), 21 deletions(-)
base-commit: 6efb943b86
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.orghttp://lists.infradead.org/mailman/listinfo/linux-arm-kernel
The current implementation of the driver holds a spin lock for the
duration of the transfer, releasing it only to enable interrupts for
short periods of time. As this would prevent any interrupt from
happening, this could cause system performance issues every time a SPI
message is sent. Since the spi core now handles message syncronization
we can reduce the amount of time the spin-lock is held to the regions
where both the calling thread and the interrupt might interract.
Signed-off-by: Dan Sneddon <dan.sneddon@microchip.com>
Link: https://lore.kernel.org/r/20210602160816.4890-2-dan.sneddon@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
STM32 QSPI is able to automatically poll a specified register inside the
memory and relieve the CPU from this task.
As example, when erasing a large memory area, we got cpu load
equal to 50%. This patch allows to perform the same operation
with a cpu load around 2%.
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20210518162754.15940-4-patrice.chotard@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
With STM32 QSPI, it is possible to poll the status register of the device.
This could be done to offload the CPU during an operation (erase or
program a SPI NAND for example).
spi_mem_poll_status API has been added to handle this feature.
This new function take care of the offload/non-offload cases.
For the non-offload case, use read_poll_timeout() to poll the status in
order to release CPU during this phase.
For example, previously, when erasing large area, in non-offload case,
CPU load can reach ~50%, now it decrease to ~35%.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Link: https://lore.kernel.org/r/20210518162754.15940-2-patrice.chotard@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
