Support for CN400 northbridge when ACPI C3 isn't available.
Tested on Epia SP13000. Thanks to Robert for testing it.
Signed-off-by: Rafa³ Bilski <rafalbilski@interia.pl>
Signed-off-by: Dave Jones <davej@redhat.com>
On board of Epia SP13000 is 10x133Mhz VIA Nehemiah. It is reported
as 10x200MHz. This patch is fixing this issue.
Signed-off-by: Rafa³ Bilski <rafalbilski@interia.pl>
Signed-off-by: Dave Jones <davej@redhat.com>
Support for Core CPUs was broken in two ways in speedstep-lib: for x86_64,
we missed a MSR definition; for both x86_64 and i386, the FSB calculation
was wrong by four (it's a quad-pumped bus). Also increase the accuracy
of the calculation.
Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
Signed-off-by: Dave Jones <davej@redhat.com>
Fix the bug in duplicate states elimination in acpi-cpufreq.
Bug: Due to duplicate state elimiation in the loop earlier, the number
of valid_states can be less than perf->state_count, in which case
freq_table was ending up with some garbage/uninitialized entries
in the table.
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
From: Alexey Starikovskiy <alexey.y.starikovskiy@intel.com>
Signed-off-by: Dave Jones <davej@redhat.com>
On some systems there could be bits set in the upper half of
the control value provided by the _PSS object. These bits are
only relevant for cpufreq drivers that use IO ports which are not
currently supported by the speedstep-centrino driver. The current
MSR oriented code assumes that upper bits are not set and thus
fails to work correctly when they are. e.g. the control and status
value equality check failed on the IBM x3650 even though the ACPI
spec allows inequality.
Signed-off-by: Gary Hade <garyhade@us.ibm.com>
Signed-off-by: Dave Jones <davej@redhat.com>
We don't need a temporary variable to get the PCI revision ID.
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Dave Jones <davej@redhat.com>
arch/x86_64/kernel/cpufreq/../../../i386/kernel/cpu/cpufreq/speedstep-lib.c:131: error: 'MSR_FSB_FREQ' undeclared (first use in this function)
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Dave Jones <davej@redhat.com>
On some systems such as the IBM x3650 there are bits set in the
upper half of the control values provided by the _PSS object.
These bits are only relevant for cpufreq drivers that use IO ports
which are not currently supported by the speedstep-centrino driver.
The current MSR oriented code assumes that upper bits are not set
and thus fails to work correctly when they are. e.g. the control
and status value equality check fails even though the ACPI spec
allows the inequality.
Signed-off-by: Gary Hade <garyh@us.ibm.com>
Signed-off-by: Dave Jones <davej@redhat.com>
Several more Intel CPUs are now capable using the p4-clockmod cpufreq
driver. As it is of limited use most of the time, print a big bold warning
if a better cpufreq driver might be available.
Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
Signed-off-by: Dave Jones <davej@redhat.com>
acpi-cpufreq needs the same patch as the previous speedstep-centrino change.
Additionally, the centrino driver can have its ifdef moved out a little
further to eliminate some more code/variables.
Signed-off-by: Dave Jones <davej@redhat.com>
arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c:396: warning: 'sw_any_bug_dmi_table' defined but not used
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Dave Jones <davej@redhat.com>
If someone inserts speedstep-smi on a mobile P4, it prevents other cpufreq
modules from loading until it is unloaded.
Signed-off-by: Hiroshi Miura <miura@da-cha.org>
Signed-off-by: Dave Jones <davej@redhat.com>
ioremap must be balanced by an iounmap and failing to do so can result
in a memory leak.
Tested (compilation only):
- using allmodconfig
- making sure the files are compiling without any warning/error due to
new changes
Signed-off-by: Amol Lad <amol@verismonetworks.com>
Signed-off-by: Dave Jones <davej@redhat.com>
Enable ondemand governor and acpi-cpufreq to use IA32_APERF and IA32_MPERF MSR
to get active frequency feedback for the last sampling interval. This will
make ondemand take right frequency decisions when hardware coordination of
frequency is going on.
Without APERF/MPERF, ondemand can take wrong decision at times due
to underlying hardware coordination or TM2.
Example:
* CPU 0 and CPU 1 are hardware cooridnated.
* CPU 1 running at highest frequency.
* CPU 0 was running at highest freq. Now ondemand reduces it to
some intermediate frequency based on utilization.
* Due to underlying hardware coordination with other CPU 1, CPU 0 continues to
run at highest frequency (as long as other CPU is at highest).
* When ondemand samples CPU 0 again next time, without actual frequency
feedback from APERF/MPERF, it will think that previous frequency change
was successful and can go to wrong target frequency. This is because it
thinks that utilization it has got this sampling interval is when running at
intermediate frequency, rather than actual highest frequency.
More information about IA32_APERF IA32_MPERF MSR:
Refer to IA-32 Intel® Architecture Software Developer's Manual at
http://developer.intel.com
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Dave Jones <davej@redhat.com>
Recent speedstep-centrino unification onto acpi-cpufreq patchset broke
cpuinfo_cur_freq interface in /sys/../cpuinfo/, when MSR was used for
transitions. Attached patch fixes that breakage.
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Dave Jones <davej@redhat.com>
Only change the frequency if the state previously set is different
from what we are trying to set. We don't really have to get the current
frequency at this point.
Signed-off-by: Denis Sadykov <denis.m.sadykov@intel.com>
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Alexey Starikovskiy <alexey.y.starikovskiy@intel.com>
Signed-off-by: Dave Jones <davej@redhat.com>
Mark ACPI hooks in speedstep-centrino as deprecated. Change the order in which
speedstep-centrino and acpi-cpufreq (when both are in kernel) will be
added. First driver to be tried is now acpi-cpufreq, followed by
speedstep-centrino.
Add a note in feature-removal-schedule to mark this deprecation.
Signed-off-by: Denis Sadykov <denis.m.sadykov@intel.com>
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Alexey Starikovskiy <alexey.y.starikovskiy@intel.com>
Signed-off-by: Dave Jones <davej@redhat.com>
Add in the support for Intel Enhanced Speedstep - MSR based transitions.
With this change, the ACPI based support in speedstep-centrino can be
deprecated and duplicate code in that driver can be marked for removal.
Much easier to maintain and support this way. This also reduces the
user misconfigurations and questions on which driver is to be used
under which CPUs to support Enhanced Speedstep.
Signed-off-by: Denis Sadykov <denis.m.sadykov@intel.com>
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Alexey Starikovskiy <alexey.y.starikovskiy@intel.com>
Signed-off-by: Dave Jones <davej@redhat.com>
Some clean up and redsign of the driver. Mainly making it easier to add
support for multiple sub-mechanisms of changing frequency. Currently this
driver supports only ACPI SYSTEM_IO address space. With the changes
below it is easier to add support for other address spaces like Intel
Enhanced Speedstep which uses MSR (ACPI FIXED_FEATURE_HARDWARE) to do the
transitions.
Signed-off-by: Denis Sadykov <denis.m.sadykov@intel.com>
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Alexey Starikovskiy <alexey.y.starikovskiy@intel.com>
Signed-off-by: Dave Jones <davej@redhat.com>
This patchset has refresh/rebase of a bunch of patches/bugfixes related to
acpi-cpufreq that were sent earlier on this list.
patch 1/8
Patch that fixes a bug in swcoordination code in acpi-cpufreq
patch 2/8 through patch 7/8
Grand unification of ACPI based speedstep-centrino and acpi-cpufreq drivers.
ACPI allows P-state transitions in multiple ways. Like using IO ports or using
processor native method (MSR). Without this patch, IO port based P-state
transitions are handled in acpi-cpufreq driver and MSR based transitions on
Intel CPUs are handled in speedstep-centrino driver. Even though most of the
code in these two drivers should be similar, except for final changing/checking
of frequency (one driver does it using IO port and other does it through
MSR), we have duplicated code in these two drivers. There are also issues
around BIOSes supporting both MSR and IO port and which driver should be
loaded first in standard installations.
The patchset combines functionality of these two driver into acpi-cpufreq
driver. ACPI based functionality in speedstep-centrino is marked deprecated
and will be removed in future. speedstep-centrino will continue to work
on systems that depend on older non-ACPI table based P-state chanes.
* 2/8 - Patch that reorganizes the code in acpi-cpufreq, cleaning it up
a little and making it easier to add MSR support later.
* 3/8 - Pull in the MSR based transition support into acpi-cpufreq.
* 4/8 - Mark speedstep-centrino deprecated. Change the order in Makefile to
load acpi-cpufreq first and speedstep-centrino later, in cases where both
are configured in.
* 5/8 - lindent acpi-cpufreq.c
* 6/8 - Minor change to eliminate the check of current frequency on
notifications. We can use last set frequency instead.
* 7/8 - Make cpufreq->get of acpi_cpufreq work correctly again.
There will be a patch in future that removes ACPI based support in
speedstep-centrino in coming months.
patch 8/8
Add support for IA32_APERF and IA32_MPERF MSR and get the actual frequency
from these MSRs and use it to determine the next frequency target in ondemand
governor
This patch:
There is a bug in software coordination patch in acpi-cpufreq, due to which
frequency will only be set on first CPU of any coordinated group.
Bug identified by Denis, was not recognised earlier as there are no platforms
yet that use software coordination with acpi-cpufreq driver.
Signed-off-by: Denis Sadykov <denis.m.sadykov@intel.com>
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Dave Jones <davej@redhat.com>
I need this patch to get a UML kernel to compile. This is with the
kernel headers in FC6 which are automatically generated from the kernel
tree. Some headers are missing but those files don't need them. At
least it appears so since the resuling kernel works fine.
Tested on x86-64.
Signed-off-by: Ulrich Drepper <drepper@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
The Linux group at Stratus Technologies has come across an issue with SCI
routing under ACPI. We were bitten by this when we made an x86_64 platform
whose BIOS provides an Interrupt Source Override for the SCI itself.
Apparently the override has no effect for the System Control Interrupt, and
this appears to be because of the way the SCI is setup in the ACPI code.
It does not handle the case where busirq != gsi.
The code that sets up the SCI routing assumes that bus irq == global irq.
So there is simply no provision for telling it otherwise. The attached
patch provides this mechanism.
This patch provided by David Bulkow, was tested on an i386 platform, which
does not use the SCI override, and also on an x86_64 platform which does
use an override.
Signed-off-by: David Bulkow <david.bulkow@stratus.com>
Cc: Andi Kleen <ak@muc.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Len Brown <len.brown@intel.com>
Intel processors starting with the Core Duo support
support processor native C-state using the MWAIT instruction.
Refer: Intel Architecture Software Developer's Manual
http://www.intel.com/design/Pentium4/manuals/253668.htm
Platform firmware exports the support for Native C-state to OS using
ACPI _PDC and _CST methods.
Refer: Intel Processor Vendor-Specific ACPI: Interface Specification
http://www.intel.com/technology/iapc/acpi/downloads/302223.htm
With Processor Native C-state, we use 'MWAIT' instruction on the processor
to enter different C-states (C1, C2, C3). We won't use the special IO
ports to enter C-state and no SMM mode etc required to enter C-state.
Overall this will mean better C-state support.
One major advantage of using MWAIT for all C-states is, with this and
"treat interrupt as break event" feature of MWAIT, we can now get accurate
timing for the time spent in C1, C2, .. states.
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Len Brown <len.brown@intel.com>
Get rid of warning in the thermal throttling code about not checking
sysfs return values.
Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Apparently whoever converted voyager never actually checked that the
patch would compile ...
Remove as much of the pt_regs references as possible and move the
remaining ones into line with what's in x86 generic.
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
The implementation of genirq in x86 completely broke voyager (and
presumably visws). Since it's plugged into so much of the x86
infrastructure, you can't expect it to work unconverted.
This patch introduces a voyager IRQ handler type and switches voyager
to the genirq infrastructure.
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Kernel build breaks with CONFIG_X86_VSMP. Probably due to some header
file cleanups in 2.6.19-rc1.
Signed-off-by: Ravikiran Thirumalai <kiran@scalex86.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This patch fixes my one line thinko where I was clearing
the vector_irq entries on the wrong cpus.
Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Fix these 2.6.19-rc1 build warnings from modpost:
WARNING: vmlinux - Section mismatch: reference to .init.text:_sinittext from .text between 'core_kernel_text' (at offset 0x3e060) and '__kernel_text_address'
WARNING: vmlinux - Section mismatch: reference to .init.text:_sinittext from .text between 'core_kernel_text' (at offset 0x3e064) and '__kernel_text_address'
WARNING: vmlinux - Section mismatch: reference to .init.text:_einittext from .text between 'core_kernel_text' (at offset 0x3e07c) and '__kernel_text_address'
WARNING: vmlinux - Section mismatch: reference to .init.text:_einittext from .text between 'core_kernel_text' (at offset 0x3e080) and '__kernel_text_address'
WARNING: vmlinux - Section mismatch: reference to .init.text:_sinittext from .text between 'is_ksym_addr' (at offset 0x4b3a4) and 'kallsyms_expand_symbol'
WARNING: vmlinux - Section mismatch: reference to .init.text:_sinittext from .text between 'is_ksym_addr' (at offset 0x4b3a8) and 'kallsyms_expand_symbol'
WARNING: vmlinux - Section mismatch: reference to .init.text:_einittext from .text between 'is_ksym_addr' (at offset 0x4b3b4) and 'kallsyms_expand_symbol'
WARNING: vmlinux - Section mismatch: reference to .init.text:_einittext from .text between 'is_ksym_addr' (at offset 0x4b3e4) and 'kallsyms_expand_symbol'
WARNING: vmlinux - Section mismatch: reference to .init.text:_sinittext from .text between 'get_symbol_pos' (at offset 0x4b640) and 'kallsyms_lookup_size_offset'
WARNING: vmlinux - Section mismatch: reference to .init.text:_sinittext from .text between 'get_symbol_pos' (at offset 0x4b644) and 'kallsyms_lookup_size_offset'
WARNING: vmlinux - Section mismatch: reference to .init.text:_einittext from .text between 'get_symbol_pos' (at offset 0x4b654) and 'kallsyms_lookup_size_offset'
WARNING: vmlinux - Section mismatch: reference to .init.text:_einittext from .text between 'get_symbol_pos' (at offset 0x4b658) and 'kallsyms_lookup_size_offset'
WARNING: vmlinux - Section mismatch: reference to .init.text:_sinittext from .text between 'get_symbol_pos' (at offset 0x4b68c) and 'kallsyms_lookup_size_offset'
The crux of the matter is that modpost only checks the relocatable
sections. i386 vmlinux has none, so modpost does no checking on it (it
does on the modules). However, sparc vmlinux has plenty of
relocatable sections because it is being built with 'ld -r' (to allow
for btfixup processing). So for sparc, modpost does do a lot of
checking. Sure enough, running modpost on arch/sparc/boot/image yields
no output (i.e. all is well).
modpost.c check_sec_ref() has:
/* We want to process only relocation sections and not .init */
if (sechdrs[i].sh_type == SHT_RELA) {
// check here
} else if (sechdrs[i].sh_type == SHT_REL) {
// check here
}
Signed-off-by: Martin Habets <errandir_news@mph.eclipse.co.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
Fix this 2.6.19-rc1 build warnings from modpost:
WARNING: vmlinux - Section mismatch: reference to .init.text:sunzilog_console_setup from .data between 'sunzilog_console' (at offset 0x8394) and 'devices_subsys'
Signed-off-by: Martin Habets <errandir_news@mph.eclipse.co.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
Fix these 2.6.19-rc1 build warnings from modpost:
WARNING: vmlinux - Section mismatch: reference to .init.text:__alloc_bootmem from .text between 'srmmu_nocache_init' (at offset 0x1a0f8) and 'srmmu_mmu_info'
WARNING: vmlinux - Section mismatch: reference to .init.text:__alloc_bootmem from .text between 'srmmu_nocache_init' (at offset 0x1a118) and 'srmmu_mmu_info'
WARNING: vmlinux - Section mismatch: reference to .init.text:srmmu_early_allocate_ptable_skeleton from .text between 'srmmu_nocache_init' (at offset 0x1a188) and 'srmmu_mmu_info'
Signed-off-by: Martin Habets <errandir_news@mph.eclipse.co.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
Kill off interrupt_table for all of the CPU subtypes, we now
default in to stepping in to do_IRQ() for _all_ IRQ exceptions
and counting the spurious ones, rather than simply flipping on
the ones we cared about. This and enabling the IRQ by default
automatically has already uncovered a couple of bugs and IRQs
that weren't being caught, as well as some that are being
generated far too often (SCI Tx Data Empty, for example).
The general rationale is to use a marker for interrupt exceptions,
test for it in the handle_exception() path, and skip out to
do_IRQ() if it's found. Everything else follows the same behaviour
of finding the cached EXPEVT value in r2/r2_bank, we just rip out
the INTEVT read from entry.S entirely (except for in the kGDB NMI
case, which is another matter).
Note that while this changes the do_IRQ() semantics regarding r4
handling, they were fundamentally broken anyways (relying entirely
on r2_bank for the cached code). With this, we do the INTEVT read
from do_IRQ() itself (in the CONFIG_CPU_HAS_INTEVT case), or fall
back on r4 for the muxed IRQ number, which should also be closer
to what SH-2 and SH-2A want anyways.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Now that we've started accounting for spurious IRQs, change the
logic somewhat so that we have a better chance of catching them.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] Pass NULL not 0 for pointer value.
[MIPS] IP27: Make declaration of setup_replication_mask a proper prototype.
[MIPS] BigSur: More useful defconfig.
[MIPS] Cleanup definitions of speed_t and tcflag_t.
[MIPS] Fix compilation warnings in arch/mips/sibyte/bcm1480/smp.c
[MIPS] Optimize and cleanup get_saved_sp, set_saved_sp
[MIPS] <asm/irq.h> does not need pt_regs anymore.
[MIPS] Workaround for bug in gcc -EB / -EL options.
[MIPS] Fix timer setup for Jazz
