[why]
Sometimes there are indications that the incorrect driver is being
loaded in automated tests. This change adds the ability for builds to
be tagged with a string, and picked up by the test infrastructure.
[how]
dc.c will allocate const for build id, which is init-ed with default
value, indicating production build. For test builds, build server will
find/replace this value. The test machine will then verify this value.
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
We observe black lines (underflow) on display when playing a
4K video with UVD. On Disabling Low memory P state this issue is
not seen.
Multiple runs of power measurement shows no imapct.
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
HW CG feature will be enabled after hw ip initialized
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
the vcn power will be controlled by VCN.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
smu only expose interface to other ip blocks.
in order to reduce dependence between smu and other ip blocks
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
SDMA IP can be power up/down via smu message
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The minRPM speed maybe equal to zero. so need to check
input RPM not equal to 0, otherwise cause divide-by-zero driver crash.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
set the target rpm value to wrong register.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Added Vega20 specific implementation for MGPU fan boost
feature.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
MGPU fan boost feature is enabled only when two or more dGPUs
in the system.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Count all GPU instances from AMD(including iGPUs and
dGPUs) in the system.
V2: drop unnecessary initialization for other gpu_info
members except mutex
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Make the profile name line match previous generations more closely.
E.g.,
0 3D_FULL_SCREEN :
vs:
0(3D_FULL_SCREEN )
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
For Vega10 and Vega20, the always on CUs are 12.
For Raven, it's 4.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Enable LBPW support on vega20.
v2: squash in warning fix (Alex)
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Manual fan RPM and pwm setting on vega20 are
available now.
V2: correct the register for fan speed setting and
avoid divide-by-zero
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Export the correct gfx voltage by hwmon interface.
V2: update the register naming for consistency
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The ppt limit read out by hwmon interface is always 0.
Correct this hwmon interface output.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Unfortunately Gustavo has decided to step down as drm-misc maintainer to
focus on other projects. Thanks Gustavo for your dedication and hard work!
Fortunately for us, we have a wealth of people qualified to assume a
-misc maintainer role. Maxime has done an outstanding job with sun4i and
in the community in general. I'm really excited that he agreed to take
on this responsibility and I look forward to working with him!
Cc: Dave Airlie <airlied@linux.ie>
Cc: Gustavo Padovan <gustavo@padovan.org>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Dave Airlie <airlied@linux.ie>
Signed-off-by: Sean Paul <sean@poorly.run>
Link: https://patchwork.freedesktop.org/patch/msgid/20181005160256.200162-1-sean@poorly.run
This patch uses the proper do_div() macro to perform u64 division and
guards against overflow if the result is too large for the unsigned long
return type
Fixes: a2c3c0a54d drm/msm/a6xx: Add devfreq support for a6xx
Cc: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
I've realised that the commit 3dae1c0919 ("drm/arm/malidp: Implemented
the size validation for AFBC framebuffers") got bungled up in the
upstreaming process and it was missing an important line from the
function that calculates the size of the AFBC framebuffer
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Liviu Dudau <Liviu.Dudau@arm.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181005152423.GF1156@e110455-lin.cambridge.arm.com
The CP performance counter selects were accidentally marked as protected
so they couldn't be written from PM4 streams. Remove the protection
because user space does have an interest in setting up their own
counters.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
We are currently leaking a drm_crtc_commit struct for every atomic
commit containing plane state. The dpu plane destroy function cleans up
the fb reference manually, but fails to release the commit ref. As a
result, we just keep allocating drm_crtc_commits without ever freeing
them. Fortunately there's a helper function which will clean up all of
our mess at once, so use that.
Thanks to Doug Anderson for reporting the memory leak (and leaving
breadcrumbs from kmemleak!).
Reported-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
This patch uses the proper do_div() macro to perform u64 division and
guards against overflow if the result is too large for the unsigned long
return type
Fixes: de0a3d094d drm/msm: re-factor devfreq code
Cc: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
size for AFBC buffers
The size of the superblocks being added to the total AFBC buffer size
got lost in the upstreaming process. Add it back.
Reviewed-by: Ayan Kumar Halder <ayan.halder@arm.com>
Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
The variable is declared in an #ifdef section, but the user is
now unconditional, which leads to a build failure:
drivers/gpu/drm/imx/imx-drm-core.c: In function 'imx_drm_bind':
drivers/gpu/drm/imx/imx-drm-core.c:264:6: error: 'legacyfb_depth' undeclared (first use in this function); did you mean 'lockdep_depth'?
Remove the remaining #ifdef as well.
Fixes: f53705fd98 ("drm/imx: Use drm_fbdev_generic_setup()")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20180926193846.2490574-1-arnd@arndb.de
Implement routines to estimate GPU busy time and fetching the
current frequency for the polling interval. This is required by
the devfreq framework which recommends a frequency change if needed.
The driver code then tries to set this new frequency on the GPU by
sending an Out Of Band(OOB) request to the GMU.
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The devfreq framework requires the drivers to provide busy time estimations.
The GPU driver relies on the hardware performance counteres for the busy time
estimations, but different hardware revisions have counters which can be
sourced from different clocks. So the busy time estimation will be target
dependent. Additionally on targets where the clocks are completely controlled
by the on chip microcontroller, fetching and setting the current GPU frequency
will be different. This patch aims to embrace these differences by re-factoring
the devfreq code a bit.
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Add a simple function to read 64 registers in the GMU domain
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Devfreq turns on and starts recommending power level as soon as it is
initialized. The GPU is still not powered on by the time the devfreq
init happens and this leads to problems on GPU's where register access
is needed to get/set power levels. So we start suspended and only restart
devfreq when GPU is powered on.
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEZH8oZUiU471FcZm+ONu9yGCSaT4FAluw4MIACgkQONu9yGCS
aT7+8xAAiYnc4khUsxeInm3z44WPfRX1+UF51frTNSY5C8Nn5nvRSnTUNLuKkkrz
8RbwCL6UYyJxF9I/oZdHPsPOD4IxXkQY55tBjz7ZbSBIFEwYM6RJMm8mAGlXY7wq
VyWA5MhlpGHM9DjrguB4DMRipnrSc06CVAnC+ZyKLjzblzU1Wdf2dYu+AW9pUVXP
j4r74lFED5djPY1xfqfzEwmYRCeEGYGx7zMqT3GrrF5uFPqj1H6O5klEsAhIZvdl
IWnJTU2coC8R/Sd17g4lHWPIeQNnMUGIUbu+PhIrZ/lDwFxlocg4BvarPXEdzgYi
gdZzKBfovpEsSu5RCQsKWG4IGQxY7I1p70IOP9eqEFHZy77qT1YcHVAWrK1Y/bJd
UA08gUOSzRnhKkNR3+PsaMflUOl9WkpyHECZu394cyRGMutSS50aWkavJPJ/o1Qi
D/oGqZLLcKFyuNcchG+Met1TzY3LvYEDgSburqwqeUZWtAsGs8kmiiq7qvmXx4zV
IcgM8ERqJ8mbfhfsXQU7hwydIrPJ3JdIq19RnM5ajbv2Q4C/qJCyAKkQoacrlKR4
aiow/qvyNrP80rpXfPJB8/8PiWeDtAnnGhM+xySZNlw3t8GR6NYpUkIzf5TdkSb3
C8KuKg6FY9QAS62fv+5KK3LB/wbQanxaPNruQFGe5K1iDQ5Fvzw=
=dMl4
-----END PGP SIGNATURE-----
BackMerge v4.19-rc6 into drm-next
I have some pulls based on rc6, and I prefer to have an explicit backmerge.
Signed-off-by: Dave Airlie <airlied@redhat.com>
- This patch series enables out-bridge for LVDS bridge device support,
and also includes two cleanups and one relevant dt binding update
for this.
Add Samsung 16x16 tiled format support
- This patch series adds Samsung 16x16 tiled format to scaler and
gsc drivers. As for this, it adds Samsung specific format to
drm_forcc.h header. For the git-pull request with relevant patches,
I requested ack-by[1] to relevant maintainers but there was no any response.
I'm pretty sure no problem to go to mainline though Exynos tree
because the only user of it is Exynos.
[1] https://patchwork.freedesktop.org/patch/243921/
Add configurable plane alpha and pixel blend mode support
- This patch series makes mixer driver to be configuragle for
pixel blend mode and plane alpha, which also includes one fixup
to set all default values correctly after reset.
One cleanup
- This patch replaces drm_atomic_helper_suspend/resume() with
drm_mode_config_helper_suspend/resume() to remove exynos specific
suspend_state.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJbsdElAAoJEFc4NIkMQxK4orIP/1NTuVHySKv44mwcNY/cKs66
kcC+KTRcB/cMF2ZFaACe3R4a+2EBAxMeqo33FbTycnmS5DCUbV7C9OLgIihSYtu8
RLojyZuEl3BE3k47QuBwdm4PTn5BqkAdG80MNyc6+rsnUY8bIaWYfGYouy7abdwU
9coKwoit6S8GyeoRmfoLGt37uLqm+MdF+mTsNGNHQ68axYTZwo9nTZHudhKOriJs
Ksuf3mUtfXVl4AwTmoVfvLwZt8/L8ZNxJMvZFYypAxFBZ608LptTzX9oVAGodaAn
JHpWQsIKNbjcenNDd2TgsRwoCYFfnS5LbrJRYoKPDzu3VCDO8PYQ8o7YW+svBzdR
FYKmCimJiHuxoU4wBxL+OcTLzrNK5c8/7Osn0bWTLlugMuOIdj8OvYTlk241V645
3nD5kyiPgZiCF2oBx4y5U8LyIlOx+yZGA4Lhm4tVwnU/1DsJTCTXZOdu86LlMwSN
A0i6/WupV2aei3s+x00li30NgsbEJKfWZJBdV5X8IZqwDRAIxEfphFmCk5Y68OHP
Swdmy2x0Y7fLST/9Bnex7f2BJMR8vLbMH6OOLWF/JPOV5WxprKOqp3FCmWdhea06
pUBiQNDI4KOg8rn2mKcNlpNolqMVqV9sbmTWUySV2l2a0dmwsepsQRp652jGFQ1u
3RdiJrrUDnbR5P/s1emZ
=aoJQ
-----END PGP SIGNATURE-----
Merge tag 'exynos-drm-next-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
Add out-bridge support
- This patch series enables out-bridge for LVDS bridge device support,
and also includes two cleanups and one relevant dt binding update
for this.
Add Samsung 16x16 tiled format support
- This patch series adds Samsung 16x16 tiled format to scaler and
gsc drivers. As for this, it adds Samsung specific format to
drm_forcc.h header. For the git-pull request with relevant patches,
I requested ack-by[1] to relevant maintainers but there was no any response.
I'm pretty sure no problem to go to mainline though Exynos tree
because the only user of it is Exynos.
(airlied: this looked fine to me)
[1] https://patchwork.freedesktop.org/patch/243921/
Add configurable plane alpha and pixel blend mode support
- This patch series makes mixer driver to be configuragle for
pixel blend mode and plane alpha, which also includes one fixup
to set all default values correctly after reset.
One cleanup
- This patch replaces drm_atomic_helper_suspend/resume() with
drm_mode_config_helper_suspend/resume() to remove exynos specific
suspend_state.
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Inki Dae <inki.dae@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1538380891-24040-1-git-send-email-inki.dae@samsung.com
Cc: Neil Armstrong <narmstrong@baylibre.com>
-----BEGIN PGP SIGNATURE-----
iQEzBAABCgAdFiEEfxcpfMSgdnQMs+QqlvcN/ahKBwoFAlu1H1cACgkQlvcN/ahK
Bwq9Lgf/RxZs3/4x6BQi0uNaJ+InuQDaPy91VWM7J4VSvTvPkDGQJgQS4a4AQqK8
p41rodzdFGhbE1C3GeWKd2eGDYG2+8M5xSzQ4F1q0gAJhseaJgC1EW3AP9zZRHwU
ByVLflSW3KJKXST+Id4pF10cVs1X1RZCkUQj7T6uRaM9i7bFXekwLJrV/cHRrnnV
KbYpzMq6s+JRxaLKp8s4OIfdpVxHxTYtj34S22r5D56X3N5NF+wg1MZQgaH4prjk
Bbc7Y5HfH2GgTaSc1X7haD/HAPfAST0YZmkew1OsWddIuCTKECddXYelVEA3B8+1
nBNKZXlqldPOwnvOMiqz52U+2o/aKw==
=zl4K
-----END PGP SIGNATURE-----
Merge tag 'drm-misc-next-fixes-2018-10-03' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
- Add EXPERT config option to allow phys mem leak from fbdev for blob drivers (Neil)
Cc: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Sean Paul <sean@poorly.run>
Link: https://patchwork.freedesktop.org/patch/msgid/20181003195957.GA64584@art_vandelay
The target definition for a630 didn't set a reasonable
value for inactive_period so it defaulted to zero and
we were essentially powering down after every submission.
Set it back to the default value to keep the GPU from
bouncing too much during regular workloads.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
This patch unifies the naming of DRM functions for reference counting
of struct drm_device. The resulting code is more aligned with the rest
of the Linux kernel interfaces.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Signed-off-by: Rob Clark <robdclark@gmail.com>
This patch unifies the naming of DRM functions for reference counting
of struct drm_gem_object. The resulting code is more aligned with the
rest of the Linux kernel interfaces.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
This patch unifies the naming of DRM functions for reference counting
of struct drm_framebuffer. The resulting code is more aligned with the
rest of the Linux kernel interfaces.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The only HFI communication with the GMU on sdm845 happens
during initialization and all commands are synchronous. A fancy
interrupt tasklet and associated infrastructure is entirely
not eeded and puts us at the mercy of the scheduler.
Instead poll for the message signal and handle the response
immediately and go on our way.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The point of the 'force_dma' parameter for of_dma_configure
is to force the device to be set up even if DMA capability is
not described by the firmware which is exactly the use case
we have for GMU - we need SMMU to get set up but we have no
other dma capabilities since memory is managed by the GPU
driver. Currently we pass false so of_dma_configure() fails
and subsequently GMU and GPU probe does as well.
Fixes: 4b565ca5a2 ("drm/msm: Add A6XX device support")
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Tested-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
In the case where preemption is not enabled, this patch simply skips
preemption related initialization in hardware init sequence.
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The return from the call to _mixer_stages can be a negative error
code however this is being assigned to an unsigned variable 'stages'
hence the check is always false. Fix this by making 'stages' an
int.
Detected by Coccinelle ("Unsigned expression compared with zero:
stages < 0")
Fixes: 25fdd5933e ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The current design greedily takes a big chunk of the PDC
register space instead of just the GPU specific sections
which conflicts with other drivers and generally makes
a mess of things.
Furthermore we only need to map the GPU PDC sections
just once during init so map the memory inside the function
that uses it and adjust the pointers and register offsets
accordingly.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
>From the review for the DT bindings for the GPU/GMU it
was suggested that the phandle for the GMU be
'qcom,gmu' instead of just 'gmu'.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
When CONFIG_DEV_COREDUMP isn't defined msm_gpu_crashstate_capture
doesn't pass the correct parameters.
drivers/gpu/drm/msm/msm_gpu.c: In function ‘recover_worker’:
drivers/gpu/drm/msm/msm_gpu.c:479:34: error: passing argument 2 of ‘msm_gpu_crashstate_capture’ from incompatible pointer type [-Werror=incompatible-pointer-types]
msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
^~~~~~
drivers/gpu/drm/msm/msm_gpu.c:388:13: note: expected ‘char *’ but argument is of type ‘struct msm_gem_submit *’
static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, char *comm,
^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/msm/msm_gpu.c:479:2: error: too many arguments to function ‘msm_gpu_crashstate_capture’
msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/msm/msm_gpu.c:388:13: note: declared here
static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, char *comm,
In current code the function msm_gpu_crashstate_capture parameters.
Fixes: cdb95931de ("drm/msm/gpu: Add the buffer objects from the submit to the crash dump")
Signed-off-by: Anders Roxell <anders.roxell@linaro.org>
Reviewed-By: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The index of the perf table was being set in the wrong bit position
in the register. With this fix, the GPU clock can be seen running at
desired frequency.
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
