Pull MIPS fixes from Ralf Baechle:
"Random fixes across the MIPS tree. The two hotspots are several bugs
in the module loader and the ath79 SOC support; also noteworthy is the
restructuring of the code to synchronize CPU timers across CPUs on
startup; the old code recently ceased to work due to unrelated
changes.
All except one of these patches have sat for a significant time in
linux-next for testing."
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: pci-ar724x: avoid data bus error due to a missing PCIe module
MIPS: Malta: Delete duplicate PCI fixup.
MIPS: ath79: don't hardcode the unavailability of the DSP ASE
MIPS: Synchronize MIPS count one CPU at a time
MIPS: BCM63xx: Fix SPI message control register handling for BCM6338/6348.
MIPS: Module: Deal with malformed HI16/LO16 relocation sequences.
MIPS: Fix race condition in module relocation code.
MIPS: Fix memory leak in error path of HI16/LO16 relocation handling.
MIPS: MTX-1: Add udelay to mtx1_pci_idsel
MIPS: ath79: select HAVE_CLK
MIPS: ath79: Use correct IRQ number for the OHCI controller on AR7240
MIPS: ath79: Fix number of GPIO lines for AR724[12]
MIPS: Octeon: Fix broken interrupt controller code.
BCM6338 and BCM6348 have a message control register width of 8 bits, instead
of 16-bits like what the SPI driver assumes right now. Also the SPI message
type shift value of 14 is actually 6 for these SoCs.
This resulted in transmit FIFO corruption because we were writing 16-bits
to an 8-bits wide register, thus spanning on the first byte of the transmit
FIFO, which had already been filed in bcm63xx_spi_fill_txrx_fifo().
Fix this by passing the message control register width and message type
shift through platform data back to the SPI driver so that it can use
it properly.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: grant.likely@secretlab.ca
Cc: spi-devel-general@lists.sourceforge.net
Cc: jonas.gorski@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/3983/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The call to spi_unregister_master() in the device remove function frees device
memory, and with it any device local data. However, device local data is still
accessed after the call to spi_unregister_master().
Acquire a reference to the SPI device and release it after cleanup is complete
to solve the problem.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
We are currently using an inferior or equal operator for comparing
the transfer frequency with the clock frequency table. Because of
this, we always end up selecting 20Mhz as a frequency, due to the
inequality transfer hz <= 20 Mhz being always true. Fix this by
reversing the inequality, which is how the comparison should be done.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
We were not properly advertising the MODE bits supported by this driver, fix
that.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
We do not need to use a flag to indicate if the master driver is stopping
it is sufficient to perform spi master unregistering in the platform
driver's remove function.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This patch converts the bcm63xx SPI driver to use the SPI infrastructure
pump message queue. Since we were previously sleeping in the SPI
driver's transfer() function (which is not allowed) this is now fixed as well.
To complete that conversion a certain number of changes have been made:
- the transfer len is split into multiple hardware transfers in case its
size is bigger than the hardware FIFO size
- the FIFO refill is no longer done in the interrupt context, which was a
bad idea leading to quick interrupt handler re-entrancy
Tested-by: Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This patch adds support for the SPI controller found on the Broadcom BCM63xx
SoCs.
Signed-off-by: Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
