Commit Graph

2924 Commits

Author SHA1 Message Date
Stephen Boyd
5759d6cdd4 This pull request against clk/clk-next brings in fixes for fractional
clocks on 2835, add the PCM clock that used to be driven directly by
 the bcm2835-i2s driver (that driver has been broken since this driver
 was introduced), and adds many other new clocks.
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Merge tag 'bcm2835-clk-next-2016-03-17' of git://github.com/anholt/linux into clk-next

This pull request against clk/clk-next brings in fixes for fractional
clocks on 2835, add the PCM clock that used to be driven directly by
the bcm2835-i2s driver (that driver has been broken since this driver
was introduced), and adds many other new clocks.

* tag 'bcm2835-clk-next-2016-03-17' of git://github.com/anholt/linux:
  clk: bcm2835: add missing osc and per clocks
  clk: bcm2835: add missing PLL clock dividers
  clk: bcm2835: enable management of PCM clock
  clk: bcm2835: reorganize bcm2835_clock_array assignment
  clk: bcm2835: remove use of BCM2835_CLOCK_COUNT in driver
  clk: bcm2835: expose raw clock-registers via debugfs
  clk: bcm2835: clean up coding style issues
  clk: bcm2835: correctly enable fractional clock support
  clk: bcm2835: divider value has to be 1 or more
  clk: bcm2835: add locking to pll*_on/off methods
  clk: bcm2835: pll_off should only update CM_PLL_ANARST
2016-03-29 16:37:54 -07:00
Matthew McClintock
2aac7ddf9a clk: qcom: ipq4019: add some fixed clocks for ddrppl and fepll
Drivers for these don't exist yet so we will add them as fixed clocks
so we don't BUG() if we change clocks that reference these clocks.

Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29 16:31:16 -07:00
Matthew McClintock
bc95d4f0a9 clk: qcom: ipq4019: switch remaining defines to enums
When this was added not all the remaining defines were switched over to
use enums, so let's complete that process here

Reported-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29 16:31:11 -07:00
Philipp Zabel
add479eeb1 clk: qcom: Make reset_control_ops const
The qcom_reset_ops structure is never modified. Make it const.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29 16:30:26 -07:00
Philipp Zabel
7ba256d2aa clk: tegra: Make reset_control_ops const
The rst_ops structure is never modified. Make it const.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29 16:30:12 -07:00
Philipp Zabel
5e7bc9c6ce clk: sunxi: Make reset_control_ops const
The sunxi_ve_reset_ops, sun9i_mmc_reset_ops, and sunxi_usb_reset_ops
structures are never modified. Make them const.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29 16:30:07 -07:00
Philipp Zabel
b1b69c5dd5 clk: atlas7: Make reset_control_ops const
The atlas7_rst_ops structure is never modified. Make it const.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29 16:30:01 -07:00
Philipp Zabel
3fb950fea6 clk: rockchip: Make reset_control_ops const
The rockchip_softrst_ops structure is never modified. Make it const.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29 16:29:46 -07:00
Philipp Zabel
fd92f41dc2 clk: mmp: Make reset_control_ops const
The mmp_clk_reset_ops structure is never modified. Make it const.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29 16:29:34 -07:00
Philipp Zabel
f39bb4579c clk: mediatek: Make reset_control_ops const
The mtk_reset_ops structure is never modified. Make it const.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29 16:29:19 -07:00
Wolfram Sang
ba8c1a81d4 clk: renesas: r8a7795: make SD clk definition specific for GEN3
About SD clocks: The clock type is Gen3 specific, the callbacks are all
Gen3 specific; I think the clock definition should also be Gen3 specific
and not in the general header file.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-03-29 09:24:02 +02:00
Ulrich Hecht
847e87920c clk: renesas: r8a7795: add PWM clock
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-03-29 09:24:02 +02:00
Xing Zheng
115510053e clk: rockchip: add clock controller for the RK3399
Add the clock tree definition for the new RK3399 SoC.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-28 14:57:07 +02:00
Shawn Lin
1d003eb080 clk: rockchip: release io resource when failing to init clk
We should call iounmap to relase reg_base since it's not going
to be used any more if failing to init clk.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27 13:03:35 +02:00
Shawn Lin
ff1ae20961 clk: rockchip: remove redundant checking of device_node
rockchip_clk_of_add_provider is used by sub-clk driver which
already call of_iomap before calling it. If device_node does
not exist, of_iomap returns NULL which will fail to init the
sub-clk driver. So really it's redundant.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27 13:03:35 +02:00
Shawn Lin
2af2544d60 clk: rockchip: fix warning reported by kernel-doc
./scripts/kernel-doc -man -v drivers/clk/rockchip/clk.h > /dev/null

drivers/clk/rockchip/clk.h:133: warning: missing initial short
description on line:
 * struct rockchip_clk_provider: information about clock provider
drivers/clk/rockchip/clk.h:133: info: Scanning doc for struct
drivers/clk/rockchip/clk.h:164: warning: missing initial short
description on line:
 * struct rockchip_pll_clock: information about pll clock
drivers/clk/rockchip/clk.h:164: info: Scanning doc for struct
drivers/clk/rockchip/clk.h:194: warning: No description found for
parameter 'parent_names'
drivers/clk/rockchip/clk.h:194: warning: No description found for
parameter 'num_parents'
drivers/clk/rockchip/clk.h:194: warning: Excess struct/union/enum/typedef
member 'parent_name' description in 'rockchip_pll_clock'
drivers/clk/rockchip/clk.h:235: warning: missing initial short
description on line:
 * struct rockchip_cpuclk_reg_data: describes register offsets and
masks of the cpuclock

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27 13:03:35 +02:00
Shawn Lin
cb3abdd628 clk: rockchip: remove mux_core_reg from rockchip_cpuclk_reg_data
mux_core_reg isn't been used anywhere, let's remove it.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27 13:03:34 +02:00
Xing Zheng
b40baccd23 clk: rockchip: add new pll-type for rk3399 and similar socs
The rk3399's pll and clock are similar with rk3036's, it different
with base on the rk3066(rk3188, rk3288, rk3368 use it), there are
different adjust foctors and control registers, so these should be
independent and separate from the series of rk3066s.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27 13:03:34 +02:00
Xing Zheng
ef1d9feecc clk: rockchip: Add support for multiple clock providers
There are need to support Multi-CRUs probability in future, but
it is not supported on the current Rockchip Clock Framework.

Therefore, this patch add support a provider as the parameter
handler when we call the clock register functions for per CRU.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27 13:03:34 +02:00
Xing Zheng
268aebaa24 clk: rockchip: allow varying mux parameters for cpuclk pll-sources
Thers are only two parent PLLs that APLL and GPLL for core on the
previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
GPLL as alternate parent when core is switching freq.

Since RK3399 big.LITTLE architecture, we need to select and adapt
more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27 13:03:33 +02:00
Xing Zheng
9387bfd19b clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type
Because there are some frac clock mux nodes don't have a gate node on
the RK3399.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27 00:53:20 +01:00
Linus Torvalds
33c1f638a0 The clk changes for this release cycle are mostly dominated by
new device support in terms of LoC, but there has been some cleanup
 in the core as well as the usual minor clk additions to various
 drivers.
 
 Core:
 
  - parent tracking has been simplified
 
  - CLK_IS_ROOT is now a no-op flag, cleaning up drivers has started
 
  - of_clk_init() doesn't consider disabled DT nodes anymore
 
  - clk_unregister() had an error path bug squashed
 
  - of_clk_get_parent_count() has been fixed to only return unsigned ints
 
  - HAVE_MACH_CLKDEV is removed now that the last arch user (ARM) is gone
 
 New Drivers:
 
  - NXP LPC18xx creg
 
  - QCOM IPQ4019 GCC
 
  - TI dm814x ADPLL
 
  - i.MX6QP
 
 Updates:
 
  - Cyngus audio clks found on Broadcom iProc devices
 
  - Non-critical fixes for BCM2385 PLLs
 
  - Samsung exynos5433 updates for clk id errors, HDMI support,
    suspend/resume simplifications
 
  - USB, CAN, LVDS, and FCP clks on shmobile devices
 
  - sunxi got support for more clks on new SoCs and went through a minor
    refactoring/rewrite to use a simpler factor clk construct
 
  - rockchip added some more clk ids and added suport for fraction dividers
 
  - QCOM GDSCs in msm8996
 
  - A new devm helper to make adding custom actions simpler (acked by Greg)
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "The clk changes for this release cycle are mostly dominated by new
  device support in terms of LoC, but there has been some cleanup in the
  core as well as the usual minor clk additions to various drivers.

  Core:
   - parent tracking has been simplified
   - CLK_IS_ROOT is now a no-op flag, cleaning up drivers has started
   - of_clk_init() doesn't consider disabled DT nodes anymore
   - clk_unregister() had an error path bug squashed
   - of_clk_get_parent_count() has been fixed to only return unsigned ints
   - HAVE_MACH_CLKDEV is removed now that the last arch user (ARM) is gone

  New Drivers:
   - NXP LPC18xx creg
   - QCOM IPQ4019 GCC
   - TI dm814x ADPLL
   - i.MX6QP

  Updates:
   - Cyngus audio clks found on Broadcom iProc devices
   - Non-critical fixes for BCM2385 PLLs
   - Samsung exynos5433 updates for clk id errors, HDMI support,
     suspend/resume simplifications
   - USB, CAN, LVDS, and FCP clks on shmobile devices
   - sunxi got support for more clks on new SoCs and went through a
     minor refactoring/rewrite to use a simpler factor clk construct
   - rockchip added some more clk ids and added suport for fraction
     dividers
   - QCOM GDSCs in msm8996
   - A new devm helper to make adding custom actions simpler (acked by Greg)"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (197 commits)
  clk: bcm2835: fix check of error code returned by devm_ioremap_resource()
  clk: renesas: div6: use RENESAS for #define
  clk: renesas: Rename header file renesas.h
  clk: max77{686,802}: Remove CLK_IS_ROOT
  clk: versatile: Remove CLK_IS_ROOT
  clk: sunxi: Remove use of variable length array
  clk: fixed-rate: Remove CLK_IS_ROOT
  clk: qcom: Remove CLK_IS_ROOT
  doc: dt: add documentation for lpc1850-creg-clk driver
  clk: add lpc18xx creg clk driver
  clk: lpc32xx: fix compilation warning
  clk: xgene: Add missing parenthesis when clearing divider value
  clk: mb86s7x: Remove CLK_IS_ROOT
  clk: x86: Remove clkdev.h and clk.h includes
  clk: x86: Remove CLK_IS_ROOT
  clk: mvebu: Remove CLK_IS_ROOT
  clk: renesas: move drivers to renesas directory
  clk: si5{14,351,70}: Remove CLK_IS_ROOT
  clk: scpi: Remove CLK_IS_ROOT
  clk: s2mps11: Remove CLK_IS_ROOT
  ...
2016-03-23 06:06:45 -07:00
Linus Torvalds
46e595a17d ARM: SoC driver updates for v4.6
Driver updates for ARM SoCs, these contain various things that touch
 the drivers/ directory but got merged through arm-soc for practical
 reasons:
 
 - Rockchip rk3368 gains power domain support
 - Small updates for the ARM spmi driver
 - The Atmel PMC driver saw a larger rework, touching both
   arch/arm/mach-at91 and drivers/clk/at91
 - All reset controller driver changes alway get merged through
   arm-soc, though this time the largest change is the addition
   of a MIPS pistachio reset driver
 - One bugfix for the NXP (formerly Freescale) i.MX weim bus driver
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "Driver updates for ARM SoCs, these contain various things that touch
  the drivers/ directory but got merged through arm-soc for practical
  reasons:

   - Rockchip rk3368 gains power domain support
   - Small updates for the ARM spmi driver
   - The Atmel PMC driver saw a larger rework, touching both
     arch/arm/mach-at91 and drivers/clk/at91
   - All reset controller driver changes alway get merged through
     arm-soc, though this time the largest change is the addition of a
     MIPS pistachio reset driver
   - One bugfix for the NXP (formerly Freescale) i.MX weim bus driver"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (43 commits)
  bus: imx-weim: Take the 'status' property value into account
  clk: at91: remove useless includes
  clk: at91: pmc: remove useless capacities handling
  clk: at91: pmc: drop at91_pmc_base
  usb: gadget: atmel: access the PMC using regmap
  ARM: at91: remove useless includes and function prototypes
  ARM: at91: pm: move idle functions to pm.c
  ARM: at91: pm: find and remap the pmc
  ARM: at91: pm: simply call at91_pm_init
  clk: at91: pmc: move pmc structures to C file
  clk: at91: pmc: merge at91_pmc_init in atmel_pmc_probe
  clk: at91: remove IRQ handling and use polling
  clk: at91: make use of syscon/regmap internally
  clk: at91: make use of syscon to share PMC registers in several drivers
  hwmon: (scpi) add energy meter support
  firmware: arm_scpi: add support for 64-bit sensor values
  firmware: arm_scpi: decrease Tx timeout to 20ms
  firmware: arm_scpi: fix send_message and sensor_get_value for big-endian
  reset: sti: Make reset_control_ops const
  reset: zynq: Make reset_control_ops const
  ...
2016-03-20 15:40:32 -07:00
Linus Torvalds
8c6d4082fc ARM: SoC 64-bit changes for v4.6
Here's our branch of ARM64 contents for this merge window, now
 containing all ARM64 changes other than device tree files.
 
 - Various new platforms get added
   - Allwinner A64 SoC
   - Annapurna Labs Alpine SoCs
   - Broadcom Vulcan
   - Marvell Armada 3700 SoCs
   - Amlogic S905
 
 - Various defconfig changes to enable platform specific drivers
 
 This branch includes the clk git tree to resolve a build-time
 dependency.
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Merge tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC 64-bit changes from Arnd Bergmann:
 "Here's our branch of ARM64 contents for this merge window, now
  containing all ARM64 changes other than device tree files.

   - Various new platforms get added:
      * Allwinner A64 SoC
      * Annapurna Labs Alpine SoCs
      * Broadcom Vulcan
      * Marvell Armada 3700 SoCs
      * Amlogic S905

   - Various defconfig changes to enable platform specific drivers

  This branch includes the clk git tree to resolve a build-time
  dependency"

* tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits)
  arm64: defconfig: Increase MMC_BLOCK_MINORS to 16
  arm64: defconfig: Add Qualcomm sdhci and restart functionality
  ARM64: Enable Amlogic Meson GXBaby platform
  arm64: defconfig: Enable Samsung MFD and related configs
  arm64: alpine: select the Alpine MSI controller driver
  arm64: defconfig: enable the Alpine family
  arm64: add Alpine SoC family
  arm64: defconfig: Enable exynos thermal config
  arm64: add defconfig options for Allwinner SoCs
  arm64: defconfig: Enable DesignWare APB GPIO controller
  arm64: defconfig: Add Renesas R-Car Gen3 USB 2.0 phy driver support
  arm64: EXYNOS: Consolidate ARCH_EXYNOS7 symbol into ARCH_EXYNOS
  clk: samsung: Don't build ARMv8 clock drivers on ARMv7
  MAINTAINERS: Add entry for Broadcom Vulcan SoC
  arm64: cputype info for Broadcom Vulcan
  arm64: Broadcom Vulcan support
  arm64: defconfig: Add Broadcom Vulcan to defconfig
  arm64: update ARCH_MVEBU for Marvell Armada 7K/8K support
  Documentation: arm: add Marvell Armada 7K and 8K families
  Documentation: arm: add link to Armada 38x Functional Spec
  ...
2016-03-20 15:08:45 -07:00
Linus Torvalds
33b3d2e88c ARM: SoC platform updates for v4.6
Newly added support for additional SoCs:
 
 - Axis Artpec-6 SoC family
 - Allwinner A83T SoC
 - Mediatek MT7623
 - NXP i.MX6QP SoC
 - ST Microelectronics stm32f469 microcontroller
 
 New features:
 - SMP support for Mediatek mt2701
 - Big-endian support for NXP i.MX
 - DaVinci now uses the new DMA engine dma_slave_map
 - OMAP now uses the new DMA engine dma_slave_map
 - earlyprintk support for palmchip uart on mach-tango
 - delay timer support for orion
 
 Other:
 - Exynos PMU driver moved out to drivers/soc/
 - Various smaller updates for Renesas, Xilinx, PXA, AT91, OMAP, uniphier
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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform updates from Arnd Bergmann:
 "Newly added support for additional SoCs:
   - Axis Artpec-6 SoC family
   - Allwinner A83T SoC
   - Mediatek MT7623
   - NXP i.MX6QP SoC
   - ST Microelectronics stm32f469 microcontroller

  New features:
   - SMP support for Mediatek mt2701
   - Big-endian support for NXP i.MX
   - DaVinci now uses the new DMA engine dma_slave_map
   - OMAP now uses the new DMA engine dma_slave_map
   - earlyprintk support for palmchip uart on mach-tango
   - delay timer support for orion

  Other:
   - Exynos PMU driver moved out to drivers/soc/
   - Various smaller updates for Renesas, Xilinx, PXA, AT91, OMAP,
     uniphier"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits)
  ARM: uniphier: rework SMP code to support new System Bus binding
  ARM: uniphier: add missing of_node_put()
  ARM: at91: avoid defining CONFIG_* symbols in source code
  ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1
  ARM: imx: Make reset_control_ops const
  ARM: imx: Do L2 errata only if the L2 cache isn't enabled
  ARM: imx: select ARM_CPU_SUSPEND only for imx6
  dmaengine: pxa_dma: fix the maximum requestor line
  ARM: alpine: select the Alpine MSI controller driver
  ARM: pxa: add the number of DMA requestor lines
  dmaengine: mmp-pdma: add number of requestors
  dma: mmp_pdma: Add the #dma-requests DT property documentation
  ARM: OMAP2+: Add rtc hwmod configuration for ti81xx
  ARM: s3c24xx: Avoid warning for inb/outb
  ARM: zynq: Move early printk virtual address to vmalloc area
  ARM: DRA7: hwmod: Add custom reset handler for PCIeSS
  ARM: SAMSUNG: Remove unused register offset definition
  ARM: EXYNOS: Cleanup header files inclusion
  drivers: soc: samsung: Enable COMPILE_TEST
  MAINTAINERS: Add maintainers entry for drivers/soc/samsung
  ...
2016-03-20 14:57:08 -07:00
Linus Torvalds
de06dbfa78 Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
Pull ARM updates from Russell King:
 "Another mixture of changes this time around:

   - Split XIP linker file from main linker file to make it more
     maintainable, and various XIP fixes, and clean up a resulting
     macro.

   - Decompressor cleanups from Masahiro Yamada

   - Avoid printing an error for a missing L2 cache

   - Remove some duplicated symbols in System.map, and move
     vectors/stubs back into kernel VMA

   - Various low priority fixes from Arnd

   - Updates to allow bus match functions to return negative errno
     values, touching some drivers and the driver core.  Greg has acked
     these changes.

   - Virtualisation platform udpates form Jean-Philippe Brucker.

   - Security enhancements from Kees Cook

   - Rework some Kconfig dependencies and move PSCI idle management code
     out of arch/arm into drivers/firmware/psci.c

   - ARM DMA mapping updates, touching media, acked by Mauro.

   - Fix places in ARM code which should be using virt_to_idmap() so
     that Keystone2 can work.

   - Fix Marvell Tauros2 to work again with non-DT boots.

   - Provide a delay timer for ARM Orion platforms"

* 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (45 commits)
  ARM: 8546/1: dma-mapping: refactor to fix coherent+cma+gfp=0
  ARM: 8547/1: dma-mapping: store buffer information
  ARM: 8543/1: decompressor: rename suffix_y to compress-y
  ARM: 8542/1: decompressor: merge piggy.*.S and simplify Makefile
  ARM: 8541/1: decompressor: drop redundant FORCE in Makefile
  ARM: 8540/1: decompressor: use clean-files instead of extra-y to clean files
  ARM: 8539/1: decompressor: drop more unneeded assignments to "targets"
  ARM: 8538/1: decompressor: drop unneeded assignments to "targets"
  ARM: 8532/1: uncompress: mark putc as inline
  ARM: 8531/1: turn init_new_context into an inline function
  ARM: 8530/1: remove VIRT_TO_BUS
  ARM: 8537/1: drop unused DEBUG_RODATA from XIP_KERNEL
  ARM: 8536/1: mm: hide __start_rodata_section_aligned for non-debug builds
  ARM: 8535/1: mm: DEBUG_RODATA makes no sense with XIP_KERNEL
  ARM: 8534/1: virt: fix hyp-stub build for pre-ARMv7 CPUs
  ARM: make the physical-relative calculation more obvious
  ARM: 8512/1: proc-v7.S: Adjust stack address when XIP_KERNEL
  ARM: 8411/1: Add default SPARSEMEM settings
  ARM: 8503/1: clk_register_clkdev: remove format string interface
  ARM: 8529/1: remove 'i' and 'zi' targets
  ...
2016-03-19 16:31:54 -07:00
Martin Sperl
d3d6f15fd3 clk: bcm2835: add missing osc and per clocks
Add AVE0, DFT, GP0, GP1, GP2, SLIM, SMI, TEC, DPI, CAM0, CAM1, DSI0E,
and DSI1E.  PULSE is not added because it has an extra divider.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-03-17 10:42:17 -07:00
Martin Sperl
728436956a clk: bcm2835: add missing PLL clock dividers
Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-03-17 10:42:17 -07:00
Martin Sperl
33b689600f clk: bcm2835: enable management of PCM clock
Enable the PCM clock in the SOC, which is used by the
bcm2835-i2s driver.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-03-17 10:42:17 -07:00
Martin Sperl
3b15afefbe clk: bcm2835: reorganize bcm2835_clock_array assignment
Reorganize bcm2835_clock_array so that there is no more
need for separate bcm2835_*_data structures to be defined.
Instead the required structures are generated inline via
helper macros.

To allow this to also work for pll alone it was required that
the parent_pll was changed from a pointer to bcm2835_pll_data
to the name of the pll instead.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-03-17 10:42:17 -07:00
Martin Sperl
56eb3a2ed9 clk: bcm2835: remove use of BCM2835_CLOCK_COUNT in driver
As the use of BCM2835_CLOCK_COUNT in
include/dt-bindings/clock/bcm2835.h is frowned upon as
it needs to get modified every time a new clock gets introduced
this patch changes the clk-bcm2835 driver to use a different
scheme for registration of clocks and pll, so that there
is no more need for BCM2835_CLOCK_COUNT to be defined.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-03-17 10:42:17 -07:00
Martin Sperl
96bf9c69d5 clk: bcm2835: expose raw clock-registers via debugfs
For debugging purposes under some circumstance
it helps to be able to see the actual clock registers.

E.g: when looking at the clock divider it is helpful to
see what the actual clock divider is.

This patch exposes all the clock registers specific to each
clock/pll/pll-divider via debugfs.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Eric Anholt <eric@anholt.net>
2016-03-17 10:42:17 -07:00
Martin Sperl
6e1e60dace clk: bcm2835: clean up coding style issues
Fix all the checkpatch complaints for clk-bcm2835.c

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2016-03-17 10:42:17 -07:00
Martin Sperl
959ca92a32 clk: bcm2835: correctly enable fractional clock support
The current driver calculates the clock divider with
fractional support enabled.

But it does not enable fractional support in the
control register itself resulting in an integer only divider,
but in clk_set_rate responds back the fractionally divided
clock frequency.

This patch enables fractional support in the control register
whenever there is a fractional bit set in the requested clock divider.

Mash clock limits are are also handled for the PWM clock
applying the correct divider limits (2 and max_int) applicable to
basic fractional divider support (mash order of 1).

It also adds locking to protect the read/modify/write cycle of
the register modification.

Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-03-17 10:42:17 -07:00
Martin Sperl
997f16bd5d clk: bcm2835: divider value has to be 1 or more
Current clamping of a normal divider allows a value < 1 to be valid.

A divider of < 1 would actually only be possible if we had a PLL...

So this patch clamps the divider to 1.

Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-03-17 10:42:17 -07:00
Martin Sperl
ec36a5c668 clk: bcm2835: add locking to pll*_on/off methods
Add missing locking to:
* bcm2835_pll_divider_on
* bcm2835_pll_divider_off
to protect the read modify write cycle for the
register access protecting both cm_reg and a2w_reg
registers.

Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-03-17 10:42:17 -07:00
Martin Sperl
6727f086cf clk: bcm2835: pll_off should only update CM_PLL_ANARST
bcm2835_pll_off is currently assigning CM_PLL_ANARST to the control
register, which may lose the other bits that are currently set by the
clock dividers.

It also now locks during the read/modify/write cycle of both
registers.

Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-03-17 10:42:17 -07:00
Heiko Stuebner
2c6fae2501 clk: rockchip: associate SCLK_MAC_PLL and disable reparenting on rk3036
The emac needs constant and very specific rate but the possible PLL-sources
are very limited, so we expect the PLL source to be set manually on per
board and don't want it to get changed in an automatic way later.
So add the necessary clock-id and disable reparenting on set_rate calls.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-03-16 19:28:02 -04:00
Xing Zheng
e764b93924 clk: rockchip: associate the rk3036 HCLK_EMAC clock-id
Associate the new clock id the clock.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: Xing Zheng <zhengxing@rock-chips.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-rockchip@lists.infradead.org
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-03-16 19:28:01 -04:00
Vladimir Zapolskiy
4d3ac66624 clk: bcm2835: fix check of error code returned by devm_ioremap_resource()
The change fixes potential oops while accessing iomem on invalid
address, if devm_ioremap_resource() fails due to some reason.

The devm_ioremap_resource() function returns ERR_PTR() and never
returns NULL, which makes useless a following check for NULL.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Fixes: 5e63dcc74b ("clk: bcm2835: Add a driver for the auxiliary peripheral clock gates")
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-15 18:14:11 -07:00
Simon Horman
e8087b5b90 clk: renesas: div6: use RENESAS for #define
Name the #define guarding compilation of this header
__RENESAS_CLK_DIV6_H__ rather than __SHMOBILE_CLK_DIV6_H__.

This is a follow-up to renaming the directory in which this file lives from
shmobile to renesas which is in turn part of an ongoing process to migrate
from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that
RENESAS seems to be a more appropriate name than SHMOBILE for the majority
of Renesas ARM based SoCs.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-15 18:13:02 -07:00
Simon Horman
09c32427c9 clk: renesas: Rename header file renesas.h
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.

Along with the above mentioned Kconfig changes it seems appropriate
to also rename files.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-15 18:12:14 -07:00
Stephen Boyd
4c9462b434 clk: max77{686,802}: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-15 15:19:49 -07:00
Stephen Boyd
ac82a8b507 clk: versatile: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Cc: Pawel Moll <pawel.moll@arm.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-15 15:19:21 -07:00
Stephen Boyd
1295e36a48 clk: sunxi: Remove use of variable length array
Using an array allocated on the stack may lead to stack overflows
and other problems so let's move the allocation to the heap
instead. This silences the following checker warning as well.

drivers/clk/sunxi/clk-sun8i-mbus.c:36:29: warning: Variable length array is used

Cc: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-15 15:15:27 -07:00
Stephen Boyd
d3781a74bc clk: fixed-rate: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-04 14:31:17 -08:00
Stephen Boyd
81925c5eaa clk: qcom: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-04 12:53:53 -08:00
Joachim Eastwood
378523d150 clk: add lpc18xx creg clk driver
The CREG block on lpc18xx contains configuration register
for two low power clocks. Support enabling of these two
clocks with a clk driver that access CREG trough the
syscon regmap interface.

These clocks are needed to support peripherals like the
internal RTC on lpc18xx.

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-04 12:52:10 -08:00
Stephen Boyd
37655fae0c Inclusion of the rk3368 fractional dividers into our handling scheme,
fixes for missing error-handling in mmc-phase, inverters and cpu-clocks
 and some more clock-ids.
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Merge tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull second batch of rockchip clk updates from Heiko Stuebner:

Inclusion of the rk3368 fractional dividers into our handling scheme,
fixes for missing error-handling in mmc-phase, inverters and cpu-clocks
and some more clock-ids.

* tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: include downstream muxes into fractional dividers on rk3368
  clk: rockchip: set the clock ids for RK3228 HDMI
  clk: rockchip: set the clock ids for RK3228 VOP
  clk: rockchip: add the tsadc clocks found on rk3228 SoCs
  clk: rockchip: add the new clock ids for RK3228 HDMI
  clk: rockchip: add the new clock ids for RK3228 VOP
  clk: rockchip: add id of the tsadc clock found on rk3228 SoCs
  clk: rockchip: fix coding style for clk-cpu.c
  clk: rockchip: don't return NULL when registering mmc branch fails
  clk: rockchip: don't return NULL when registering inverter fails
  clk: rockchip: check grf when waiting pll lock
  clk: rockchip: disable alt_parent clk in err cases when registering cpuclk
2016-03-04 09:36:29 -08:00
Sylvain Lemieux
8626556f25 clk: lpc32xx: fix compilation warning
Remove the following false positives compilation warning:
- drivers/clk/nxp/clk-lpc32xx.c: In function 'lpc32xx_clk_register':
  warning: 'hw' may be used uninitialized in this function [-Wmaybe-uninitialized]
- drivers/clk/nxp/clk-lpc32xx.c: In function 'clk_hclk_pll_round_rate':
  warning: 'p' may be used uninitialized in this function [-Wmaybe-uninitialized]
  warning: 'n' may be used uninitialized in this function [-Wmaybe-uninitialized]
  warning: 'm' may be used uninitialized in this function [-Wmaybe-uninitialized]

Tested using gcc version 4.7.3.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
[sboyd@codeaurora.org: Drop assignment of hw to NULL as return
silences it and is less likely to lead to hiding problems later]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03 11:41:43 -08:00
Loc Ho
0f4c7a138d clk: xgene: Add missing parenthesis when clearing divider value
In the initial fix for non-zero divider shift value, the parenthesis
was missing after the negate operation. This patch adds the required
parenthesis. Otherwise, lower bits may be cleared unintentionally.

Signed-off-by: Loc Ho <lho@apm.com>
Acked-by: Toan Le <toanle@apm.com>
Fixes: 1382ea631d ("clk: xgene: Fix divider with non-zero shift value")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03 11:37:15 -08:00
Stephen Boyd
0d9967fe4b clk: mb86s7x: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03 11:27:48 -08:00
Stephen Boyd
4106684e11 clk: x86: Remove clkdev.h and clk.h includes
This driver is a clk provider and not a clk consumer, so remove
the clk.h include. Also, drop clkdev.h because there's not clkdev
usage here either.

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03 11:27:26 -08:00
Stephen Boyd
553b485817 clk: x86: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03 11:27:18 -08:00
Stephen Boyd
2969f6ee37 clk: mvebu: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03 11:26:42 -08:00
Simon Horman
b3a33077c0 clk: renesas: move drivers to renesas directory
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.

Along with the above mentioned Kconfig changes it seems appropriate
to also rename directories that only hold drivers for such SoCs.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03 11:22:53 -08:00
Stephen Boyd
27fbd266de Merge branch 'clk-shmobile-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull shmobile clk updates from Geert Uytterhoeven:

   - Fix a bug in the div6 clock driver that was exposed by CAN
     support on R-Car H3,
   - Add more module clocks for R-Car H3.

* 'clk-shmobile-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: shmobile: r8a7795: Add CAN FD peripheral clock
  clk: shmobile: r8a7795: Add CANFD clock
  clk: shmobile: r8a7795: Add CAN peripheral clock
  clk: shmobile: div6: Fix .recalc_rate() using a stale divisor
  clk: shmobile: r8a7795: Add LVDS module clock
  clk: shmobile: r8a7795: Add FCP clocks
2016-03-03 11:21:40 -08:00
Stephen Boyd
803c43311f clk: si5{14,351,70}: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Cc: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:51:13 -08:00
Stephen Boyd
905936823e clk: scpi: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:50:58 -08:00
Stephen Boyd
8620925231 clk: s2mps11: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Andi Shyti <andi.shyti@samsung.com>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:50:32 -08:00
Stephen Boyd
1edfc1e700 clk: pwm: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:50:08 -08:00
Stephen Boyd
124603990d clk: efm32gg: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:48:47 -08:00
Stephen Boyd
0b4d613a71 clk: zynq: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:48:26 -08:00
Stephen Boyd
66f4ae777d clk: ux500: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:48:03 -08:00
Stephen Boyd
45e21151a2 clk: ti: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:47:46 -08:00
Stephen Boyd
f6da46a307 clk: tegra: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Rhyland Klein <rklein@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:47:19 -08:00
Stephen Boyd
afb4bdc9d8 clk: spear: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:46:55 -08:00
Stephen Boyd
728f288d2a clk: samsung: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:46:29 -08:00
Stephen Boyd
2c63935dd6 clk: pxa: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:46:00 -08:00
Stephen Boyd
615b34de1f clk: nxp: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:45:22 -08:00
Stephen Boyd
0f4207f3d8 clk: mxs: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:44:59 -08:00
Stephen Boyd
38c7035f9c clk: imx: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:44:26 -08:00
Stephen Boyd
3d08f1564b clk: mediatek: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:44:06 -08:00
Stephen Boyd
f61990f3c5 clk: hisilicon: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Tested-by: Leo Yan <leo.yan@linaro.org>
Cc: Bintian Wang <bintian.wang@huawei.com>
Cc: Zhangfei Gao <zhangfei.gao@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:43:32 -08:00
Stephen Boyd
a9bb2ef7c3 clk: at91: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:43:08 -08:00
Stephen Boyd
bd41aa6773 clk: bcm: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Cc: Lee Jones <lee@kernel.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:42:41 -08:00
Stephen Boyd
5788923b27 Merge tag 'imx-clk-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next
Pull i.MX clk updates from Shawn Guo:

The i.MX clock update for 4.6:
- Add the clock driver support for the latest i.MX6 family SoCs
  addition - i.MX6QP.
- Clean up the whitespace in i.MX6UL clock driver and add the missing
  KPP clock.
- Correct pwm7 clock name in i.MX6UL clock driver.

* tag 'imx-clk-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx: add kpp clock for i.MX6UL
  clk: imx: whitespace cleanup; no functional change
  clk: imx: correct pwm7 clock name in driver for i.MX6UL
  clk: imx: Add clock support for imx6qp
2016-03-02 14:31:47 -08:00
Stephen Boyd
06a9852747 Merge tag 'sunxi-clocks-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next
Pull Allwinner clk updates from Maxime Ripard:

Allwinner clocks additions for 4.6

A bunch of things, mostly:
  - Finally switched everything over to OF_CLK_DECLARE, which should remove
    orphans clocks entirely
  - Reworked the clk-factors to be able to add new parameters
  - Improved the error reporting
  - A bunch of new clocks for new SoCs.

* tag 'sunxi-clocks-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (25 commits)
  clk: sunxi: Add apb0 gates for H3
  clk: sunxi: Improve divs_clk error handling and reporting
  clk: sunxi: improve divider_clk error handling and reporting
  clk: sunxi: improve mux_clk error handling and reporting
  clk: sunxi: Fix sun8i-a23-apb0-clk divider flags
  clk: sunxi: Remove clk_register_clkdev calls
  clk: sunxi: Remove old probe and protection code
  clk: sunxi: convert current clocks registration to CLK_OF_DECLARE
  clk: sunxi: Make clocks setup functions take const pointer
  clk: sunxi: Make clocks setup functions return their clock
  clk: sunxi: improve error reporting for the mux clock
  clk: sunxi: don't mark sun6i_ar100_data __initconst
  clk: sunxi: add bus gates for A83T
  clk: sunxi: Add apb0 gates for A83T
  clk: sunxi: rewrite sun8i-a23-mbus-clk using the simpler composite clk
  clk: sunxi: rewrite sun6i-ar100 using factors clk
  clk: sunxi: rewrite sun6i-a31-ahb1-clk using factors clk with custom recalc
  clk: sunxi: factors: Drop round_rate from clk ops
  clk: sunxi: factors: Support custom formulas
  clk: sunxi: factors: Consolidate get_factors parameters into a struct
  ...
2016-03-02 14:31:42 -08:00
Stephen Boyd
0f75e1a370 clk: qcom: msm8960: Fix ce3_src register offset
The offset seems to have been copied from the sata clk. Fix it so
that enabling the crypto engine source clk works.

Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Fixes: 5f775498bd ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 14:31:31 -08:00
Michael Turquette
3b0f4ae3e9 Merge branch 'clk-ti' into clk-next
Conflicts:
	drivers/clk/Kconfig
2016-03-01 16:23:40 -08:00
Stephen Boyd
8a8b6eb7a8 clk: ti: Fix some errors found by static checkers
drivers/clk/ti/clk-814x.c:34:12: warning: symbol 'dm814x_adpll_early_init' was not declared. Should it be static?
drivers/clk/ti/clk-814x.c:58:12: warning: symbol 'dm814x_adpll_enable_init_clocks' was not declared. Should it be static?
drivers/clk/ti/adpll.c:465 ti_adpll_recalc_rate() warn: should '__readw(d->regs + 20) << 18' be a 64 bit type?
drivers/clk/ti/adpll.c:945 ti_adpll_probe() error: we previously assumed 'd->clocks' could be null (see line 921)

The last one looks like a real bug because we don't return an
error on allocation failure.

Cc: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-01 16:21:25 -08:00
Tony Lindgren
c2ee9bdc85 clk: ti: Allow COMPILE_TEST to build selected drivers
The arch independent drivers can be build testeed with
COMPILE_TEST. Let's allow that for drivers/clk/ti.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-03-01 16:21:25 -08:00
Tony Lindgren
21330497f3 clk: ti: Add support for dm814x ADPLL
On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The
ADPLLs have several dividers and muxes controlled by a shared
control register for each PLL.

Note that for the clocks to work as device drivers for booting on
dm814x, this patch depends on "ARM: OMAP2+: Change core_initcall
levels to postcore_initcall" that has already been merged.

Also note that this patch does not implement clk_set_rate for the
PLL, that will be posted later on when available.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-03-01 16:21:25 -08:00
Archit Taneja
811a498e5e clk: qcom: Fix pre-divider usage for pixel RCG
The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading
its current value from the NS register.

Using the pre-divider wasn't really intended when creating these ops.
The pixel RCG was only intended to achieve fractional multiplication
provided in the pixel_table array. Leaving the pre-divider to the
existing register value results in a wrong pixel clock when the
bootloader sets up the display. This was left unidentified because
the IFC6410 Plus board on which this was verified didn't have a
bootloader that configured the display.

Don't set the RCG pre-divider in freq_tbl to the existing NS register
value. Force it to 1 and only use the M/N counter to achieve the desired
fractional multiplication.

Cc: Vinay Simha <vinaysimha@inforcecomputing.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Tested-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-29 12:57:06 -08:00
Lothar Waßmann
f6c3aec2f7 clk: imx: add kpp clock for i.MX6UL
Add the necessary clock to use the KPP interface on i.MX6UL.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-02-28 10:45:29 +08:00
Lothar Waßmann
9797d81936 clk: imx: whitespace cleanup; no functional change
remove whitespace before TAB.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-02-28 10:45:13 +08:00
Stephen Boyd
d3622b5885 clk: h8300: Properly cast to __iomem pointer
Sparse complains here because we dropped the __iomem annotation
when casting the aligned address. Add __iomem back so that sparse
stops complaining.

Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: <uclinux-h8-devel@lists.sourceforge.jp>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-26 16:01:32 -08:00
Stephen Boyd
921bacfa34 clk: ti: Update for of_clk_get_parent_count() returning unsigned int
Change the types here to unsigned int instead of int and update
the checks for == 0 instead < 1 to be more explicit about what's
going on now that of_clk_get_parent_count() has changed return
types.

Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-26 16:01:32 -08:00
Stephen Boyd
36bf281141 clk: sunxi: Use proper type for of_clk_get_parent_count() return value
The return type of of_clk_get_parent_count() is an unsigned int
now, so let's update the code here to be more explicit about the
range of values we can test for.

Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-26 16:01:32 -08:00
Stephen Boyd
caeb057cd3 clk: st: Remove impossible check for of_clk_get_parent_count() < 0
The checks for < 0 are impossible now that
of_clk_get_parent_count() returns an unsigned int. Simplify the
code and update the types.

Cc: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-26 16:01:32 -08:00
Stephen Boyd
ebf3f9a923 clk: h8300: Remove impossible check for of_clk_get_parent_count()
The checks for < 1 can be simplified now that
of_clk_get_parent_count() returns an unsigned int. Update the
code to reflect the int to unsigned int change.

Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: <uclinux-h8-devel@lists.sourceforge.jp>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-26 16:01:32 -08:00
Stephen Boyd
0985df8953 clk: gpio: Remove impossible check for of_clk_get_parent_count() < 0
The check for < 0 is impossible now that
of_clk_get_parent_count() returns an unsigned int. Simplify the
code and update the type here.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-26 16:01:32 -08:00
Stephen Boyd
8c1b1e54fa clk: at91: Remove impossible checks for of_clk_get_parent_count()
These checks for < 0 are impossible now that
of_clk_get_parent_count() returns an unsigned int. Change the
checks for == 0 and update the type.

Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-26 16:01:32 -08:00
Stephen Boyd
929e7f3bc7 clk: Make of_clk_get_parent_count() return unsigned ints
Russell King recently pointed out a bug in the clk-gpio code
where it fails to register the clk if of_clk_get_parent_count()
returns an error because the "clocks" property isn't present in
the DT node. If we're trying to count parents from DT we'd like
to know the count, not if there is a "clocks" property or not.
Furthermore, some drivers are assigning the return value to their
clk_init_data::num_parents member which is unsigned, leading to
potentially large numbers of parents when the property isn't
present.

Let's change the API to return an unsigned int instead of an int.
All the callers just want to know the count anyway, and this
avoids the bug that was in the clk-gpio driver.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-26 16:01:32 -08:00
Geert Uytterhoeven
3e5dd6f6e6 clk: Ignore disabled DT clock providers
of_clk_init() uses for_each_matching_node_and_match() to find clock
providers, which returns all matching device nodes, whether they are
enabled or not. Hence clock providers that are disabled explicitly in DT
using e.g.

	"status = "disabled";

are still activated.

Add a check to ignore device nodes that are not enabled, like
of_irq_init() does.

Reported-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-26 09:39:38 -08:00
Ramesh Shanmugasundaram
a080c8c346 clk: shmobile: r8a7795: Add CAN FD peripheral clock
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-26 12:04:30 +01:00
Ramesh Shanmugasundaram
7e00d63199 clk: shmobile: r8a7795: Add CANFD clock
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-26 12:04:30 +01:00
Ramesh Shanmugasundaram
11c6fb7832 clk: shmobile: r8a7795: Add CAN peripheral clock
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-26 12:04:29 +01:00
Geert Uytterhoeven
3092d3b8e5 clk: shmobile: div6: Fix .recalc_rate() using a stale divisor
cpg_div6_clock_set_rate() only programs the new divisor if the clock
isn't stopped. If the clock is stopped, it will update the cached
divisor value only, which will be programmed into the clock registers
when enabling the clock later.

However, cpg_div6_clock_recalc_rate() reads the divisor from the clock
registers instead of using the cached value, leading to an incorrect
result if the clock is currently stopped.

Make cpg_div6_clock_recalc_rate() use the cached value to fix this.

Reported-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
2016-02-26 12:03:10 +01:00
Laurent Pinchart
31aeb5a523 clk: shmobile: r8a7795: Add LVDS module clock
The parent clock hasn't been validated yet.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-26 12:01:42 +01:00