This is to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind
with the Denverton pinctrl platform driver.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Use macros defined in linux/cleanup.h to automate resource lifetime
control in the driver.
While at it, unify the variables and approach in intel_gpio_irq_*().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
We don't need to update debounce pulse value in case debounce is to be
disabled. Break such a case where arg value is zero.
Fixes: 4cfff5b7af ("pinctrl: baytrail: consolidate common mask operation")
Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Closes: https://lore.kernel.org/linux-gpio/d164d471-5432-4c3c-afdb-33dc8f53d043@moroto.mountain/
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
First argument of acpi_*_address_space_handler() APIs is acpi_handle of
the device, which is incorrectly passed in driver ->remove() path here.
Fix it by passing the appropriate argument and while at it, make both
API calls consistent using ACPI_HANDLE().
Fixes: a0b028597d ("pinctrl: cherryview: Add support for GMMR GPIO opregion")
Cc: stable@vger.kernel.org
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Since all the Intel specific platform drivers depend on ACPI, we can
consolidate their config dependency.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Since pm.h provides a helper for system no-IRQ PM callbacks,
switch the driver to use it instead of open coded variant.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20230717172821.62827-4-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cleaning up the driver to use pm_ptr() and *_PM_OPS() macros that
make it simpler and allows the compiler to remove those functions
if built without CONFIG_PM and CONFIG_PM_SLEEP support.
The lp_gpio_resume() is also assigned to .thaw and .restore members.
This is not a problem as the function it enables input pins that
had been disabled by firmware and repetion of that doesn't change
the pin configuration, i.e. it is idempotent.
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20230717172821.62827-6-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cleaning up the driver to use pm_ptr() and *_PM_OPS() macros that
make it simpler and allows the compiler to remove those functions
if built without CONFIG_PM and CONFIG_PM_SLEEP support.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20230717172821.62827-3-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
We already have a few symbols exported in the namespace.
Let's do the same for others (except PM for now).
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Raag Jadav <raag.jadav@intel.com> says:
This series exports common pinctrl functions that are used across
Intel specific platform drivers to PINCTRL_INTEL namespace and
reuses them into Baytrail, Cherryview and Lynxpoint drivers.
This helps reduce their code and memory footprint.
X86 kernels are fairly unikernels such that pinctrl-intel driver is
enabled by most Linux distributions and most Intel specific platform
drivers (inside drivers/pinctrl/intel) depend on it.
The only exception to this is Lynxpoint. But taking into account its
fairly old age, it wouldn't suffer much from pinctrl-intel dependency.
bloat-o-meter:
==============
Intel:
add/remove: 17/10 grow/shrink: 0/0 up/down: 375/-319 (56)
Total: Before=9598, After=9654, chg +0.58%
Baytrail:
add/remove: 1/6 grow/shrink: 0/2 up/down: 41/-441 (-400)
Total: Before=16538, After=16138, chg -2.42%
Cherryview:
add/remove: 1/6 grow/shrink: 2/0 up/down: 90/-272 (-182)
Total: Before=18133, After=17951, chg -1.00%
Lynxpoint:
add/remove: 1/6 grow/shrink: 0/1 up/down: 24/-354 (-330)
Total: Before=7836, After=7506, chg -4.21%
Link: https://lore.kernel.org/r/20230814060311.15945-1-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reuse common functions from pinctrl-intel driver.
While at it, select pinctrl-intel for Intel Lynxpoint driver.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20230814060311.15945-5-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reuse common functions from pinctrl-intel driver.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20230814060311.15945-4-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reuse common functions from pinctrl-intel driver.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20230814060311.15945-3-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Export common pinctrl functions that are used across Intel specific
platform drivers, so that they can be reused.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20230814060311.15945-2-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Raag Jadav <raag.jadav@intel.com> says:
Merrifield and Moorefield pinctrl driver implementations are similar
in terms of how they access the hardware. We can consolidate their
pinctrl functionalities into a common library driver.
This patch set introduces:
1. Intel Tangier driver that supports the common pinctrl functionalities
for Merrifield and Moorefield platforms.
2. Intel Tangier adaptation for Merrifield pinctrl driver.
3. Intel Tangier adaptation for Moorefield pinctrl driver.
Tested on Intel Edison platform.
No deviation observed in the contents of below entries before and after
this patchset.
- /proc/interrupts
- /sys/kernel/debug/gpio
- /sys/kernel/debug/pinctrl/*/pins
Link: https://lore.kernel.org/r/20230814054033.12004-1-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Tangier implements the common pinctrl functionalities for
Merrifield and Moorefield platforms.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Link: https://lore.kernel.org/r/20230814054033.12004-2-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Consolidate common mask operation outside of switch cases and
limit IO operations to positive cases.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
We do not use goto labels in the Intel pin control drivers,
so drop the only one in the entire folder.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Invert if condition and get rid of redundant else.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20230616203356.27343-4-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Add warning for BYT_VAL_REG retrieval failure and continue such case
to avoid unintended reads/writes in pm_ops.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20230616203356.27343-3-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reduce scope of spinlock to IO operations in ->dbg_show() hook
and save a few bytes.
add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-12 (-12)
Function old new delta
byt_gpio_dbg_show 890 878 -12
Total: Before=17029, After=17017, chg -0.07%
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20230616203356.27343-2-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Refine ->irq_set_type() hook and improve its readability by:
- Reducing scope of spinlock by moving unneeded operations out of it.
- Dropping redundant PADCFG0_RXEVCFG_SHIFT and including it directly
into PADCFG0_RXEVCFG_* definitions.
- Utilizing temporary variables for common operations.
- Simplifying if-else-if chain.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Utilize a temporary variable for common shift operation in
->set_mux() hook and improve readability while saving a few bytes.
add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-3 (-3)
Function old new delta
intel_pinmux_set_mux 245 242 -3
Total: Before=10472, After=10469, chg -0.03%
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20230613085054.10976-2-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
This driver adds pinctrl/GPIO support for Intel Meteor Lake-S.
The GPIO controller is based on the next generation GPIO hardware
but still compatible with the one supported by the Intel pinctrl
and GPIO core driver.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Use explicit comparison to BUFCFG_PINMODE_GPIO instead of implying it.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Currently the pin may not be configured as open-drain in some
cases because the argument may be 0 for the boolean types of
the pin configurations. Fix this by ignoring the argument.
With that, allow to actually restore pin to the push-pull mode.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Use explicit comparison to BUFCFG_PINMODE_GPIO instead of implying it.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Currently the pin may not be configured as open-drain in some
cases because the argument may be 0 for the boolean types of
the pin configurations. Fix this by ignoring the argument.
With that, allow to actually restore pin to the push-pull mode.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Currently the getter returns ENOTSUPP on pin configured in
the push-pull mode. Fix this by adding the missed switch case.
Fixes: ccdf81d08d ("pinctrl: cherryview: add option to set open-drain pin config")
Fixes: 6e08d6bbeb ("pinctrl: Add Intel Cherryview/Braswell pin controller support")
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
The semantics of INVALID_HWIRQ is rather localized to IPI usage.
Let's keep it that way.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
The bias setting (pull-up or pull-down) are bit fields and
we never enable them both, hence use BIT() macro to define
them.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Use same formatting strings where it makes sense, so linker
will utilize only a single copy of it, otherwise make the
style similar to the rest of the messages of the close enough
semantics.
add/remove: 1/0 grow/shrink: 2/2 up/down: 91/-110 (-19)
Total: Before=17562, After=17543, chg -0.11%
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
- Add PINCTRL_PINFUNCTION() macro and use it in several
drivers.
New drivers:
- New driver for the StarFive JH7110 SoC "sys" and "aon"
(always-on) pin controllers. (RISC-V.)
- New subdriver for the Qualcomm QDU1000/QRU1000 SoC pin
controller.
- New subdrivers for the Qualcomm SM8550 SoC and LPASS
pin controllers.
- New subdriver for the Qualcomm SA8775P SoC pin controller.
- New subdriver for the Qualcomm IPQ5332 SoC pin controller.
- New (trivial) support for Qualcomm PM8550 and PMR735D PMIC
pin control.
- New subdriver for the Mediatek MT7981 SoC pin controller.
Improvements:
- Several cleanups and refactorings to the Intel drivers.
- Add 4KOhm bias support to the Intel driver.
- Use the NOIRQ_SYSTEM_SLEEP_PM_OPS for the AT91 driver.
- Support general purpose clocks in the Qualcomm MSM8226 SoC.
- Several conversions to use the new I2C .probe_new() call.
- Massive clean-up of the Qualcomm Device Tree YAML schemas.
- Add VIN[45] pins, groups and functions to the Renesas
r8a77950 SoC driver.
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Merge tag 'pinctrl-v6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Nothing special, notably a lot of new Qualcomm hardware is supported,
a RISC-V reference SoC and then some cleanups both in code and device
tree bindings.
Core changes:
- Add PINCTRL_PINFUNCTION() macro and use it in several drivers
New drivers:
- New driver for the StarFive JH7110 SoC "sys" and "aon" (always-on)
pin controllers. (RISC-V.)
- New subdriver for the Qualcomm QDU1000/QRU1000 SoC pin controller
- New subdrivers for the Qualcomm SM8550 SoC and LPASS pin
controllers
- New subdriver for the Qualcomm SA8775P SoC pin controller
- New subdriver for the Qualcomm IPQ5332 SoC pin controller
- New (trivial) support for Qualcomm PM8550 and PMR735D PMIC pin
control
- New subdriver for the Mediatek MT7981 SoC pin controller
Improvements:
- Several cleanups and refactorings to the Intel drivers
- Add 4KOhm bias support to the Intel driver
- Use the NOIRQ_SYSTEM_SLEEP_PM_OPS for the AT91 driver
- Support general purpose clocks in the Qualcomm MSM8226 SoC
- Several conversions to use the new I2C .probe_new() call
- Massive clean-up of the Qualcomm Device Tree YAML schemas
- Add VIN[45] pins, groups and functions to the Renesas r8a77950 SoC
driver"
* tag 'pinctrl-v6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (118 commits)
pinctrl: qcom: Add support for i2c specific pull feature
pinctrl: starfive: Add StarFive JH7110 aon controller driver
pinctrl: starfive: Add StarFive JH7110 sys controller driver
dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl
dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl
pinctrl: add mt7981 pinctrl driver
dt-bindings: pinctrl: add bindings for MT7981 SoC
dt-bindings: pinctrl: rockchip,pinctrl: mark gpio sub nodes of pinctrl as deprecated
pinctrl: qcom: Introduce IPQ5332 TLMM driver
dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl
dt-bindings: pinctrl: qcom: lpass-lpi: correct GPIO name pattern
pinctrl: qcom: pinctrl-sm8550-lpass-lpi: add SM8550 LPASS
dt-bindings: pinctrl: qcom,sm8550-lpass-lpi-pinctrl: add SM8550 LPASS
pinctrl: at91: use devm_kasprintf() to avoid potential leaks
dt-bindings: pinctrl: qcom: correct gpio-ranges in examples
dt-bindings: pinctrl: qcom,msm8994: correct number of GPIOs
dt-bindings: pinctrl: qcom,sdx55: correct GPIO name pattern
dt-bindings: pinctrl: qcom,msm8953: correct GPIO name pattern
dt-bindings: pinctrl: qcom,sm6375: correct GPIO name pattern and example
dt-bindings: pinctrl: qcom,msm8909: correct GPIO name pattern and example
...
If the firmware mangled the register contents too much,
check the saved value for the Direct IRQ mode. If it
matches, we will restore the pin state.
Reported-by: Jim Minter <jimminter@microsoft.com>
Fixes: 6989ea4881 ("pinctrl: intel: Save and restore pins in "direct IRQ" mode")
Tested-by: Jim Minter <jimminter@microsoft.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20230206141558.20916-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The driver has been converted to a generic data type and macro for
the pin function definition, hence get rid of not used members in
the struct intel_function.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Convert driver to use generic data type and hence a new member in
the struct intel_function. No functional change intended.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Convert driver to use generic data type and hence a new member in
the struct intel_function. No functional change intended.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Convert driver to use generic data type and hence a new member in
the struct intel_function. No functional change intended.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Convert driver to use generic data type and hence a new member in
the struct intel_function. No functional change intended.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Convert driver to use generic data type and hence a new member in
the struct intel_function. No functional change intended.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Since pin control provides a generic data type and a macro for
the pin function definition, use them in the Intel driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Instead of using hard coded magic number here and there,
define maximum pad number in the group in newly added
INTEL_PINCTRL_MAX_GPP_SIZE.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
PADCFG0 and PADCFG1 are ordered from MSB to LSB, do the same
for PADCFG2 bit fields. No functional changes intended.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
All versions that have 20k and 5k resistance, i.e. all that
the driver supports, may support ~4k when the above mentioned
are connected in parallel. Add such a support.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Add definitions to all possible biases, i.e. add ~800 Ohms,
~952 Ohms, ~4 kOhms.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
First part is to assign default argument for all cases, since
bias disablement doesn't use it anyway.
Second part is to clear all bits in the bias setting and
depending on the argument and parameter set them as asked.
While at it, add break statement to the default cases.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
For the sake of symmetry with intel_config_get_pull(), add
a default case to the outer switch.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
