Replace the call to shmobile_timer_init() with
clocksource_of_init(). This will allow us to
get rid of shmobile_timer_init().
Signed-off-by: Magnus Damm <damm@opensource.se>
[horms+renesas@verge.net.au: include linux/clocksource.h]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This is sufficient to allow boot of the Lager board with
a console without boards-lager.c compiled into the kernel.
This is an example of a minimal but still useful initialisation
of the board using DT as much as possible.
As such it is the same as the boot of Lager that can be achieved
without a board file. The intention of adding this file
is to facilitate further work to allow board specific devices to be
initialised via DT.
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Update the r8a7790 arch timer setup code to configure the
frequency dynamically at boot time. This means that the arch
timer driver will be able to detect a timer frequency that
has been calculated based on the MD pins instead of a fixed
and potentially incorrect 13 MHz.
With this patch applied the Linux kernel will correctly
support the r8a7790 Lager board that uses a 20 Mhz EXTAL.
The arch timer will operate on 10 MHz and the Linux arch
timer driver will be correctly configured to use 10 MHz.
Without this patch the 20 MHz EXTAL will be used to drive
the arch timer at 10 MHz, but the Linux arch timer driver
will believe it is counting at 13 Mhz.
Reported-by: Ulrich Hecht <ulrich.hecht@gmail.com>
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Ulrich Hecht <ulrich.hecht@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Break out the r8a7790 boot mode code into a separate
function so it can be shared by multiple users.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Update the r8a7790 code to allow using other
timers than Arch timer for clock events.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add clock event support for CMT0 timer channel 0
to the r8a7790 SoC code. On most ARM mach-shmobile
the CMT is hooked up to a 32KHz clock but on r8a7790
a 31.7KHz clock is instead used.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The current temperature may be read using:
cat /sys/class/thermal/thermal_zone0/temp
Based on similar work for the r8a73a4 by Kuninori Morimoto.
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Replace the SoC-specific callback init_machine() with
a NULL to use the default code. This cleans up the code
and reduces the number of lines.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
HSCIF support by Ulrich Hecht.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRyqpMAAoJENfPZGlqN0++KbMP/3XPeCGPyiAvoEYFT68CTUE3
vtyVU5APL7rJ7eCkuxXvBriJ8GRcL95NUwK7kss3kPDpSTkNf4UmVCgrs1mj2gjl
8PxjxGzyeryDl/cILx1EOJYkmhm6TUjbeFrd2uFOxntbhItnCrEAHDwx7AxQhI79
Enz3L0moU1v8rq/MBiyGKh1wD2UFgyzcqbxhsdxhDurgbhElfnccWxjK9DVXxCAP
c9Lyc0GIC5CniI+LITgcbay93/2//5/ytSQTc3gDfbNkVk/8sa4HWyV4XLDNNCAz
EclVD9fLBXHITVtid6c/Nxqnn+6W31LKKsR52XDYs8anT61YxoO6QHzEiXPpzEvF
3NbR9Vv3EpgIe6NXn0JB5GwOvggJxWHNg9/8LspyZujtzS99fLe00L0ICEftfsVp
62wUnvC/477DuXr5e/o8YrSvWxnKq51tqoFthWUEn6FkjoUYC8eNuCAnvKrODf4i
y5FokvDepmhElLFOFWuCDahPeSy512WKtsGNLKzulwLF0zEmpkAitw6gtE044fsk
FLtaA8SpmdgbH0NiLW0jFuNR4w36vPZ2g7mCqWGlkAxMC9jlitfWDvSG+KssqEL6
ObgR3GyuYrHqVgB7vqGztqvZWekBSsQXdk5Y80mN15M+3qO5KwYjKo89U8lWMS4W
zMq5g9o/qW7C9NnHCPA2
=bnU/
-----END PGP SIGNATURE-----
Merge tag 'renesas-sh-sci-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late
Renesas sh-sci updates for v3.11
HSCIF support by Ulrich Hecht.
* tag 'renesas-sh-sci-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
serial: sh-sci: Initialise variables before access in sci_set_termios()
ARM: shmobile: r8a7790: don't use external clock for SCIFs
ARM: shmobile: r8a7790: HSCIF support
serial: sh-sci: HSCIF support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This is an external component and may or may not be there, while the
internal clock always works.
Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Adds support for HSCIF0 and HSCIF1 on the r8a7790.
Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com>
[ horms+renesas@verge.net.au this is the setup-r8a7790.c
which I somehow miss-applied as part of another patch.
The clock-r8a7790.c portion of this patch has already been merged. ]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
These data will be kmemdup()'ed on
platform_device_add_resources() and platform_device_add_data()
This patch removed "const" to avoid section type conflict
with r8a7790_boards_compat_dt
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
"gpio-rcar: Support IRQ_TYPE_EDGE_BOTH" adds support to the R-Car GPIO
driver for IRQ_TYPE_EDGE_BOTH. As hardware support for this feature is
not universal for all SoCs a flag, has_both_edge_trigger, has been
added to the platform data of the driver to allow this feature to be
enabled.
As the r8a7790 SoC hardware supports this feature enable it.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Move GPIOs handling from the PFC device to separate GPIO devices.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Implement a SoC-specific timer init function for
r8a7790 that makes sure the architected timer
is started regardless of boot loader setting.
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the GPIO I/O memory range to the r8a7790 PFC device.
This extra I/O memory range is needed when using the PFC
tables to drive both pin functions (using PINCTRL or
function GPIO for old code) and actual GPIO. The goal is
however to use a separate GPIO driver in the long run
and when that happens this extra I/O memory range can
be removed.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add IRQC interrupt controller support to r8a7790 by
hooking up a single IRQC instances to handle 4 external
IRQ signals. The IRQC controller is tied to SPIs of
the GIC. On r8a7790 the external IRQ pins routing is
handled by the PFC which is excluded from this patch.
Both platform devices and DT devices are added in this
patch. The platform device versions are used to provide
a static interrupt map configuration for board code
written in C.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add SCIF serial port support to the r8a7790 SoC by
adding platform devices for SCIFA0 -> SCIFA2 as well
as SCIFB0 -> SCIFB2 and SCIF0 -> SCIF1 together with
clock bindings. DT device description is excluded at
this point since such bindings are still under
development.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add initial support for the r8a7790 SoC including:
- Single Cortex-A15 CPU Core
- GIC
- Architecture timer
No static virtual mappings are used, all the components
make use of ioremap(). DT_MACHINE_START is still wrapped
in CONFIG_USE_OF to match other mach-shmobile code.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
