This includes:
* L1/L2 cache topology for t600x
* CPUfreq nodes for t8103/t600x
* DT binding for CPUfreq
* Associated MAINTAINERS update
The CPUfreq driver was already merged for 6.2 via its tree.
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Merge tag 'asahi-soc-dt-6.2-v2' of https://github.com/AsahiLinux/linux into soc/dt
Apple SoC DT updates for 6.2 (v2).
This includes:
* L1/L2 cache topology for t600x
* CPUfreq nodes for t8103/t600x
* DT binding for CPUfreq
* Associated MAINTAINERS update
The CPUfreq driver was already merged for 6.2 via its tree.
* tag 'asahi-soc-dt-6.2-v2' of https://github.com/AsahiLinux/linux:
arm64: dts: apple: Add CPU topology & cpufreq nodes for t600x
arm64: dts: apple: Add CPU topology & cpufreq nodes for t8103
dt-bindings: cpufreq: apple,soc-cpufreq: Add binding for Apple SoC cpufreq
MAINTAINERS: Add entries for Apple SoC cpufreq driver
arm64: dts: apple: Add t600x L1/L2 cache properties and nodes
Link: https://lore.kernel.org/r/a9353121-7fed-fde7-6f40-939a65bfeefb@marcan.st
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add the missing CPU topology/capacity information and the cpufreq nodes,
so we can have CPU frequency scaling and the scheduler has the
information it needs to make the correct decisions.
As with t8103, boost states are commented out pending PSCI/etc support
for deep sleep states.
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
Add the missing CPU topology/capacity information and the cpufreq nodes,
so we can have CPU frequency scaling and the scheduler has the
information it needs to make the correct decisions.
Boost states are commented out, as they are not yet available (that
requires CPU deep sleep support, to be eventually done via PSCI).
The driver supports them fine; the hardware will just refuse to ever
go into them at this time, so don't expose them to users until that's
done.
Acked-by: Marc Zyngier <maz@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
for 6.2, please pull the following:
- Rafal describes the timer/watchdog block for the BCM4908 and BCM6858
SoCs
- Krzysztof corrects invalid "reg" properties for the memory nodes that
were off by one digit
- Pierre updates a number of cache Device Tree node properties to be
schema compliant
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Merge tag 'arm-soc/for-6.2/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree updates
for 6.2, please pull the following:
- Rafal describes the timer/watchdog block for the BCM4908 and BCM6858
SoCs
- Krzysztof corrects invalid "reg" properties for the memory nodes that
were off by one digit
- Pierre updates a number of cache Device Tree node properties to be
schema compliant
* tag 'arm-soc/for-6.2/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: Update cache properties for broadcom
arm64: dts: broadcom: trim addresses to 8 digits
arm64: dts: broadcom: bcmbca: bcm6858: add TWD block
arm64: dts: broadcom: bcmbca: bcm4908: add TWD block timer
Link: https://lore.kernel.org/r/20221129191755.542584-2-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Just few addtions including updates to cache information on various
platforms to align well with the bindings, addition of cache information
on FVP Rev C model, addition of SPE to Foundation model and updates to
LED node names.
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Merge tag 'juno-updates-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
Armv8 Juno/FVP updates for v6.2
Just few addtions including updates to cache information on various
platforms to align well with the bindings, addition of cache information
on FVP Rev C model, addition of SPE to Foundation model and updates to
LED node names.
* tag 'juno-updates-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
ARM: dts: vexpress: align LED node names with dtschema
arm64: dts: fvp: Add information about L1 and L2 caches
arm64: dts: fvp: Add SPE to Foundation FVP
arm64: dts: Update cache properties for Arm Ltd platforms
arm64: dts: juno: Add thermal critical trip points
Link: https://lore.kernel.org/r/20221129115111.2464233-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This introduces support for SM4250, SM6115, SM6375 and SDM670 platforms
and Sony Xperia 10 IV, Google Pixel 3a, OnePlus 3, OnePlus 3T, Google
Pazquel and OnePlus Nord N100.
A wide variety of updates to align with DeviceTree bindings across
many/most platforms is introduced, and incorrectly styled comments are
adjusted across the tree.
Apps RSC is added to the cluster-idle power-domain across SM8150,
SM8250, SM8350 and SM8450, to ensure sleep and wake votes are flushed as
the last core is being powered down.
Remoteproc firmware patches are aligned with agreed upon structure used
in linux-firmware across Inforce 6560, Lenovo Miix 630, various Sony
Xperia devices and Samsung Galaxy Book2 (although these are not
available in linux-firmware today).
On IPQ8074 CPU clocks are added, thermal zones are introduced and vqmmc
supply is specified for the HK01 board.
Alcatel OneTouch Idol 3 gains LED nodes and Samsung Galaxy A3U gained
vibrator support.
The application subsystem's IOMMU and the display subsystem is enabled
for MSM8953.
A new CPU frequency table is introduced for MSM8996Pro, to properly
describe it separate of MSM8996. The GPU opp-table is extended as well.
On SC7180 USB is marked as a wakeup source, USB gains required-opps to
ensure that the core voltage rail is voted for as needed. The
description of the fingerprint sensor in Trogdor is corrected.
On SC7280 Wake-on-WLAN is introduced, and PHY parameters for the SNPS
USB PHY is defined across SC7280.
The memory map across Google Herobrine is adjusted, to regain unused
memory on the WiFi SKUs. A LTE SKU of the Evoker board is introduced
and the bard gains touchscreen.
NVME support is disabled on Villager boards, as it's not used.
PCIe support is introduced on SC8280XP, with NVMe, SDX55 (5G) and WiFi
enabled on the Lenovo Thinkpad X13s and Compute Reference Device. ADCs
and thermal zones are intrduced for the same. Lenovo Thinkpad X13s
gains LID switch support.
Fairphone FP3 gains touchscreen support.
Support for Xiaomi Poco F1 variant with EBBG panel.
The round-robin ADC is enabled across DB845c, OnePlus devices and
Pocophone F1 devices.
The displayport controller on SDM845 is introduced.
SM6350 gains SDHCI support and on Sony Xperia 10 III sd-card,
touchscreen and GPI DMA is enabled.
Fairphone FP4 got SD-card support.
UFS PHY register ranges are corrected across SM8150, SM8250, SM8350 and
SM8450.
Sony Xperia 1 II got NFC support and Sony Xperia 5 III got PMIC
regulators defined and USB definition corrected, to enable USB3.
The SDHCI controller is described for SM8450 and microSD support is
enabled for the HDK and QRD devices.
SM8450 also gains camera CCI interface and display clock controller.
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Merge tag 'qcom-arm64-for-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm ARM64 DTS updates for 6.2
This introduces support for SM4250, SM6115, SM6375 and SDM670 platforms
and Sony Xperia 10 IV, Google Pixel 3a, OnePlus 3, OnePlus 3T, Google
Pazquel and OnePlus Nord N100.
A wide variety of updates to align with DeviceTree bindings across
many/most platforms is introduced, and incorrectly styled comments are
adjusted across the tree.
Apps RSC is added to the cluster-idle power-domain across SM8150,
SM8250, SM8350 and SM8450, to ensure sleep and wake votes are flushed as
the last core is being powered down.
Remoteproc firmware patches are aligned with agreed upon structure used
in linux-firmware across Inforce 6560, Lenovo Miix 630, various Sony
Xperia devices and Samsung Galaxy Book2 (although these are not
available in linux-firmware today).
On IPQ8074 CPU clocks are added, thermal zones are introduced and vqmmc
supply is specified for the HK01 board.
Alcatel OneTouch Idol 3 gains LED nodes and Samsung Galaxy A3U gained
vibrator support.
The application subsystem's IOMMU and the display subsystem is enabled
for MSM8953.
A new CPU frequency table is introduced for MSM8996Pro, to properly
describe it separate of MSM8996. The GPU opp-table is extended as well.
On SC7180 USB is marked as a wakeup source, USB gains required-opps to
ensure that the core voltage rail is voted for as needed. The
description of the fingerprint sensor in Trogdor is corrected.
On SC7280 Wake-on-WLAN is introduced, and PHY parameters for the SNPS
USB PHY is defined across SC7280.
The memory map across Google Herobrine is adjusted, to regain unused
memory on the WiFi SKUs. A LTE SKU of the Evoker board is introduced
and the bard gains touchscreen.
NVME support is disabled on Villager boards, as it's not used.
PCIe support is introduced on SC8280XP, with NVMe, SDX55 (5G) and WiFi
enabled on the Lenovo Thinkpad X13s and Compute Reference Device. ADCs
and thermal zones are intrduced for the same. Lenovo Thinkpad X13s
gains LID switch support.
Fairphone FP3 gains touchscreen support.
Support for Xiaomi Poco F1 variant with EBBG panel.
The round-robin ADC is enabled across DB845c, OnePlus devices and
Pocophone F1 devices.
The displayport controller on SDM845 is introduced.
SM6350 gains SDHCI support and on Sony Xperia 10 III sd-card,
touchscreen and GPI DMA is enabled.
Fairphone FP4 got SD-card support.
UFS PHY register ranges are corrected across SM8150, SM8250, SM8350 and
SM8450.
Sony Xperia 1 II got NFC support and Sony Xperia 5 III got PMIC
regulators defined and USB definition corrected, to enable USB3.
The SDHCI controller is described for SM8450 and microSD support is
enabled for the HDK and QRD devices.
SM8450 also gains camera CCI interface and display clock controller.
* tag 'qcom-arm64-for-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (261 commits)
arm64: dts: qcom: sdm845-polaris: Don't duplicate DMA assignment
arm64: dts: qcom: sm8350-sagami: Wire up USB regulators and fix USB3
arm64: dts: qcom: sm8350-sagami: Add most RPMh regulators
arm64: dts: qcom: sc7280: Make herobrine-audio-rt5682 mic dtsi's match more
arm64: dts: qcom: trim addresses to 8 digits
arm64: dts: msm8998: unify PCIe clock order withMSM8996
arm64: dts: msm8998: add MSM8998 specific compatible
arm64: dts: qcom: sc8280xp-x13s: enable WiFi controller
arm64: dts: qcom: sc8280xp-x13s: enable modem
arm64: dts: qcom: sc8280xp-x13s: enable NVMe SSD
arm64: dts: qcom: sc8280xp-crd: enable WiFi controller
arm64: dts: qcom: sc8280xp-crd: enable SDX55 modem
arm64: dts: qcom: sc8280xp-crd: enable NVMe SSD
arm64: dts: qcom: sc8280xp-crd: rename backlight and misc regulators
arm64: dts: qcom: sa8295p-adp: enable PCIe
arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes
arm64: dts: qcom: add sdm670 and pixel 3a device trees
arm64: dts: qcom: sc7280: Add Google Herobrine WIFI SKU dts fragment
arm64: dts: qcom: sc7280: Mark all Qualcomm reference boards as LTE
arm64: dts: qcom: sm7225-fairphone-fp4: Enable SD card
...
Link: https://lore.kernel.org/r/20221124100650.1982448-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
New boards:
- Model A and blade baseboards for the SOQuartz (rk3568) SoM,
- Anberic RG351M, RG353V, RG353VS; Odroid Go Super, Advance gaming devices
- Odroid M1
- Theobroma px30 SoM with baseboard
- Rockchip's own rk3566 demo board
Some core support for per SoC specifics:
- crypto support for rk3399 and rk3328
- second I2S controller for rk3568
- Cache properties for follow the binding for rk3308 and rk3328
Bigger device support updates for:
- SOQuartz: PCIe2, video output, gpu, HDMI sound
- Rock 3A: eth regulator, eth clock input, Wifi+Bt, I2S, PCIe3
As well as some minor extensions for Rock960 (hdmi supplies),
rk3566-roc-pc (PCIe2), Rock 4C+ (thermal support), Pinephone Pro (Wifi+Bt)
* tag 'v6.2-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (51 commits)
arm64: dts: rockchip: update cache properties for rk3308 and rk3328
arm64: dts: rockchip: Add SOQuartz Model A baseboard
dt-bindings: arm: rockchip: Add SOQuartz Model A
arm64: dts: rockchip: Add SOQuartz blade board
dt-bindings: arm: rockchip: Add SOQuartz Blade
arm64: dts: rockchip: Add Anbernic RG351M
arm64: dts: rockchip: Add Odroid Go Super
arm64: dts: rockchip: Add Odroid Go Advance Black Edition
dt-bindings: arm: rockchip: Add more RK3326 devices
arm64: dts: rockchip: Move most of Odroid Go Advance DTS into a DTSI
arm64: dts: rockchip: Add support of regulator for ethernet node on Rock 3A SBC
arm64: dts: rockchip: Add support of external clock to ethernet node on Rock 3A SBC
arm64: dts: rockchip: Add HDMI supplies on Rock960
arm64: dts: rockchip: Add dts for rockchip rk3566 box demo board
dt-bindings: rockchip: Add Rockchip rk3566 box demo board
arm64: dts: rockchip: Enable PCIe 2 on SOQuartz CM4IO
arm64: dts: rockchip: Enable HDMI sound on SOQuartz
arm64: dts: rockchip: Enable video output and HDMI on SOQuartz
arm64: dts: rockchip: Enable GPU on SOQuartz CM4
arm64: dts: rockchip: enable pcie2 on rk3566-roc-pc
...
Link: https://lore.kernel.org/r/4716610.aeNJFYEL58@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The node names should be generic and DT schema expects certain pattern:
altera/socfpga_stratix10_socdk.dtb: leds: 'hps0', 'hps1', 'hps2' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Link: https://lore.kernel.org/r/20221122163208.3810985-3-pierre.gondois@arm.com
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The t600x CPU nodes are missing the cache hierarchy information. The
cache hierarchy on Arm can not be detected and needs to be described in
DT. The OS scheduler can make use of this information for scheduling
decisions.
The cache size information is based on various articles about the
processors. There's also an L3 system level cache (SLC). It's not
described here because SLCs typically have some MMIO interface which
would need to be described.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
Add reserved memory and ARM firmware definitions for optee
memory region in Marvell Armada SoCs to avoid protected memory
access.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@bootlin.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The recently added init_of_cache_level() function checks
these properties. Add them if missing.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
MCP7940MT-I/MNY RTC has connected interrupt line to GPIO2_5.
Fixes: 7109d817db ("arm64: dts: marvell: add DTS for Turris Mox")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
PCIe Slot Power Limit on Turris Mox is 10W.
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
New Features:
J721e:
* PWMs, BeagleBone AI-64 platform.
J721s2:
* Crypto
AM65/AM62:
* General purpose Timer support (system timer is still arch timer)
Fixes:
* Bunch of fixes in crypto usage and GPIO intr
* Minor schema related fixes for audio, addressing etc.
Cleanups:
* Refactor of device tree to "disable" peripherals at SoC level
for nodes that are un-usable without board level properties.
TI K3 devices have large number of peripherals of which only a
smaller subset is actually enabled on platforms. Switching
to this approach enables two benefits: lesser confusion in
creating board level devicetrees as only relevant pinned out
device nodes need enabled, as well as smaller board device
trees as most un-used peripherals don't need to explicitly
disabled.
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Merge tag 'ti-k3-dt-for-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
TI K3 devicetree updates for v6.2
New Features:
J721e:
* PWMs, BeagleBone AI-64 platform.
J721s2:
* Crypto
AM65/AM62:
* General purpose Timer support (system timer is still arch timer)
Fixes:
* Bunch of fixes in crypto usage and GPIO intr
* Minor schema related fixes for audio, addressing etc.
Cleanups:
* Refactor of device tree to "disable" peripherals at SoC level
for nodes that are un-usable without board level properties.
TI K3 devices have large number of peripherals of which only a
smaller subset is actually enabled on platforms. Switching
to this approach enables two benefits: lesser confusion in
creating board level devicetrees as only relevant pinned out
device nodes need enabled, as well as smaller board device
trees as most un-used peripherals don't need to explicitly
disabled.
* tag 'ti-k3-dt-for-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (61 commits)
arm64: dts: ti: Add k3-j721e-beagleboneai64
dt-bindings: arm: ti: Add bindings for BeagleBone AI-64
arm64: dts: ti: k3-j721s2-main: Enable crypto accelerator
arm64: dts: ti: k3-am64-main: Drop RNG clock
arm64: dts: ti: k3-j721e-main: Drop RNG clock
arm64: dts: ti: k3-am65-main: Drop RNG clock
arm64: dts: ti: j721e-common-proc-board: Fix sound node-name
arm64: dts: ti: k3-j721s2: Fix the interrupt ranges property for main & wkup gpio intr
arm64: dts: ti: k3-j7200-mcu-wakeup: Drop dma-coherent in crypto node
arm64: dts: ti: k3-j721e-main: Drop dma-coherent in crypto node
arm64: dts: ti: k3-am65-main: Drop dma-coherent in crypto node
arm64: dts: ti: k3-am62: Add general purpose timers for am62
arm64: dts: ti: k3-am65: Add general purpose timers for am65
arm64: dts: ti: k3-am65: Configure pinctrl for timer IO pads
arm64: dts: ti: Trim addresses to 8 digits
arm64: dts: ti: k3-j721e-sk: Add pinmux for RPi Header
arm64: dts: ti: k3-j721e-main: Add dts nodes for EHRPWMs
arm64: dts: ti: k3-am65: Enable McASP nodes at the board level
arm64: dts: ti: k3-am65: Enable Mailbox nodes at the board level
arm64: dts: ti: k3-am65: Enable PCIe nodes at the board level
...
Link: https://lore.kernel.org/r/20221122190209.jwfj56d6kxpxdkua@untreated
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Link: https://lore.kernel.org/r/20221107155825.1644604-20-pierre.gondois@arm.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch adds the device tree for the "Model A" baseboard for
the SOQuartz CM4 SoM, which is not to be confused with the
Quartz64 Model A, which is the same form factor and SoC, but is
not a CM4 carrier board.
The board features a PCIe 2 x1 slot, USB 2 host ports, CSI/DSI
connectors, an eDP FFC connector, gigabit ethernet, HDMI, and a
12V DC barrel jack. Also present is a microSD card slot, 40-pin
GPIO, and a power and reset button.
Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
[rebase, misc fixes, reword]
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Link: https://lore.kernel.org/r/20221116115337.541601-5-frattaroli.nicolas@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This adds a device tree for the PINE64 SOQuartz blade baseboard,
a 1U rack mountable baseboard for the CM4 form factor with PoE
support designed for the SOQuartz CM4 System-on-Module.
The board takes power from either PoE or a 5V DC input, and allows
for mounting an M.2 SSD.
The board also features one USB 2.0 host port, one HDMI output,
a 3.5mm jack for UART, and the aforementioned gigabit networking
port.
Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
[rebase, squash, reword, misc fixes]
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Link: https://lore.kernel.org/r/20221116115337.541601-3-frattaroli.nicolas@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This device is a clone of Odroid Go Advance, with added PWM motor, internal
gamepad connected on USB instead of just having it be on GPIO + ADC, and
missing battery shunt resistor.
Due to missing shunt resistor and lack of a workaround in rk817_charger
driver rk817_charger is not enabled in dts.
There's also an LED on GPIO 77(I *guess* PB5 on &gpio2),
that is controlled in a weird way:
- It is set to red by setting output value to 1
- Set to green by setting output value to 0
- Set to yellow by setting gpio direction to input
I have no idea how to describe that in DTS, without adding a custom
driver, for now it's just left out.
Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
Link: https://lore.kernel.org/r/20221117215954.4114202-6-maccraft123mc@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This device is another revision of Odroid Go Advance, with added two
volume buttons, a second analog stick and a bigger screen that isn't yet
supported in the mainline kernel.
Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
Link: https://lore.kernel.org/r/20221117215954.4114202-5-maccraft123mc@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
To support more devices that are clones of this device or minor
revisions without duplication move most of go2's dts into a dtsi file.
Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
Link: https://lore.kernel.org/r/20221117215954.4114202-2-maccraft123mc@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add regulator support for ethernet node
Fix following warning.
[ 7.365199] rk_gmac-dwmac fe010000.ethernet: no regulator found
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Acked-by: Michael Riesch <michael.riesch@wolfvision.net>
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20221116200150.4657-4-linux.amoon@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add support of external clock gmac1_clkin which is used as input clock
to ethernet node.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Michael Riesch <michael.riesch@wolfvision.net>
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20221116200150.4657-3-linux.amoon@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This contains many new additions, primarily for Tegra234, as well as a
slew of cleanups for issues flagged by the DT validation tools.
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Merge tag 'tegra-for-6.2-arm64-dt-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
arm64: tegra: Device tree changes for v6.2-rc1
This contains many new additions, primarily for Tegra234, as well as a
slew of cleanups for issues flagged by the DT validation tools.
* tag 'tegra-for-6.2-arm64-dt-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (30 commits)
arm64: tegra: Remove unneeded clock-names for Tegra132 PWM
arm64: tegra: Fix up compatible string for SDMMC1 on Tegra234
arm64: tegra: Remove unused reset-names for QSPI
arm64: tegra: Fixup pinmux node names
arm64: tegra: Remove reset-names for QSPI
arm64: tegra: Use correct compatible string for Tegra234 HDA
arm64: tegra: Use correct compatible string for Tegra194 HDA
arm64: tegra: Use vbus-gpios property
arm64: tegra: Restructure Tegra210 PMC pinmux nodes
arm64: tegra: Update cache properties
arm64: tegra: Remove 'enable-active-low'
arm64: tegra: Add dma-channel-mask in GPCDMA node
arm64: tegra: Fix non-prefetchable aperture of PCIe C3 controller
arm64: tegra: Add missing compatible string to Ethernet USB device
arm64: tegra: Separate AON pinmux from main pinmux on Tegra194
arm64: tegra: Add ECAM aperture info for all the PCIe controllers
arm64: tegra: Remove clock-names from PWM nodes
arm64: tegra: Enable GTE nodes
arm64: tegra: Update console for Jetson Xavier and Orin
arm64: tegra: Enable PWM users on Jetson AGX Orin
...
Link: https://lore.kernel.org/r/20221121171239.2041835-7-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Use the "clk-phase-sd-hs" property for SDMMC
- Remove the "clk-phase" fom the sdmmc_clk that is no longer used
- Clean dtschema for mmc node
- Increase NAND partition for Arria10
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Merge tag 'socfpga_dts_updates_for_v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
SoCFPGA dts updates for v6.2
- Use the "clk-phase-sd-hs" property for SDMMC
- Remove the "clk-phase" fom the sdmmc_clk that is no longer used
- Clean dtschema for mmc node
- Increase NAND partition for Arria10
* tag 'socfpga_dts_updates_for_v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
arm: dts: socfpga: remove "clk-phase" in sdmmc_clk
arm: dts: socfpga: align mmc node names with dtschema
ARM: dts: socfpga: arria10: Increase NAND boot partition size
Link: https://lore.kernel.org/r/20221121163259.341974-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
BeagleBoard.org BeagleBone AI-64 is an open source hardware single
board computer based on the Texas Instruments TDA4VM SoC featuring
dual-core 2.0GHz Arm Cortex-A72 processor, C7x+MMA and 2 C66x
floating-point VLIW DSPs, 3x dual Arm Cortex-R5 co-processors,
2x 6-core Programmable Real-Time Unit and Industrial Communication
SubSystem, PowerVR Rogue 8XE GE8430 3D GPU. The board features 4GB
DDR4, USB3.0 Type-C, 2x USB SS Type-A, miniDisplayPort, 2x 4-lane
CSI, DSI, 16GB eMMC flash, 1G Ethernet, M.2 E-key for WiFi/BT, and
BeagleBone expansion headers.
This board family can be indentified by the BBONEAI-64-B0 in the
at24 eeprom:
[aa 55 33 ee 01 37 00 10 2e 00 42 42 4f 4e 45 41 |.U3..7....BBONEA|]
[49 2d 36 34 2d 42 30 2d 00 00 42 30 30 30 37 38 |I-64-B0-..B00078|]
https://beagleboard.org/ai-64https://git.beagleboard.org/beagleboard/beaglebone-ai-64
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
Reviewed-by: Andrew Davis <afd@ti.com>
CC: Nishanth Menon <nm@ti.com>
CC: Vignesh Raghavendra <vigneshr@ti.com>
CC: Tero Kristo <kristo@kernel.org>
CC: Jason Kridner <jkridner@beagleboard.org>
CC: Drew Fustini <drew@beagleboard.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20221118163139.3592054-2-robertcnelson@gmail.com
This patch adds spi support for MT7986.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221118190126.100895-7-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Move the wed_pcie node to have node aligned by address.
Fixes: 00b9903996 ("arm64: dts: mediatek: mt7986: add support for Wireless Ethernet Dispatch")
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221118190126.100895-2-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
i.MX arm64 device tree update for 6.2:
- New device trees for i.MX8MM based Cloos PHG and WB15 SoM/EVK.
- A set of tqma8mpql/mba8mpxl changes, adding USB Host, PCIe, PWM fan
support.
- Rename DTB overlay source files from .dts to .dtso.
- A series from Frank Li to add USB, ADC, FlexSPI, LPSPI support for
i.MX8DXL.
- A couple of librem5-devkit changes, switching LED to use PWM and using
function and color properties for LED.
- Enable wakeup-source for USB PHY for i.MX8MM/N EVK.
- A set of random changes from Marcel Ziswiler to improve i.MX8M based
Verdin device trees.
- A series from Marek Vasut to update Data Modul i.MX8M Mini eDM SBC and
DH electronics i.MX8M Plus DHCOM, modeling PMIC to SNVS RTC clock
path, dropping QCA clk_out setup, adding bluetooth UART, etc.
- A bunch of changes from Peng Fan to add LPSPI, TPM etc for i.MX93,
update i.MX8MP/N EVK with UART, I2C addition.
- Update cache properties per DeviceTree Specification v0.3.
- Add gpio-ranges property for i.MX8DXL and i.MX8Q LSIO Subsystem.
- Misc small and random changes.
* tag 'imx-dt64-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (60 commits)
arm64: dts: freescale: Rename DTB overlay source files from .dts to .dtso
arm64: dts: imx8mm-evk: add vcc supply for pca6416
arm64: dts: imx8m[m,q]-evk: change to use off-on-delay-us in regulator
arm64: dts: imx8mn-evk: enable uart1
arm64: dts: imx8mn-evk: add i2c gpio recovery settings
arm64: dts: imx8mn-evk: set off-on-delay-us in regulator
arm64: dts: imx8mn-evk: update vdd_soc dvs voltage
arm64: dts: imx8mp-evk: enable I2C2 node
arm64: dts: imx8mp-evk: enable fspi nor on imx8mp evk
arm64: dts: imx8mp-evk: enable uart1/3 ports
ARM64: dts: imx8mp-evk: add pwm support
arm64: dts: imx8mp: add mlmix power domain
arm64: dts: imx8mq: fix dtschema warning for imx7-csi
arm64: dts: Update cache properties for freescale
arm64: dts: imx8mm-phg: Add initial board support
arm64: dts: imx8qxp-ss-lsio: add gpio-ranges property
arm64: dts: imx8qm-ss-lsio: add gpio-ranges property
arm64: dts: imx8dxl-ss-lsio: add gpio-ranges property
arm64: dts: imx8dxl_evk: add lpspi0 support
arm64: dts: imx8dxl: add lpspi support
...
Link: https://lore.kernel.org/r/20221119125733.32719-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The compatible string list for SDHCI on Tegra234 should be
"nvidia,tegra234-sdhci", followed by the "nvidia,tegra186-sdhci"
fallback. Use that consistently for all SDHCI controllers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Tegra QSPI controller uses a single reset line, so there's no need
for a reset-names property. Remove such properties.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Pinmux node names should have a pinmux- prefix and not use underscores.
Fix up some cases that didn't follow those rules.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Tegra QSPI controllers use a single reset control, so reset-names is
not necessary and therefore not specified in the DT bindings. Drop the
property from device tree files to avoid validation warnings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Tegra234 HDA controller is not backwards-compatible with Tegra30, so
drop the corresponding compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Tegra194 HDA controller is not backwards-compatible with Tegra30, so
drop the corresponding compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Instead of using the deprecated vbus-gpio property, switch to using the
more standard vbus-gpios property.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The PMC pinmux configuration nodes need to be part of a top-level pinmux
node. Add that new "pinmux" node and move the configuration nodes into
it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The 'enable-active-low' property is not a valid one.
Only 'enable-active-high' is valid, and when this property is absent
the gpio regulator will act as active low by default.
Remove the invalid 'enable-active-low' property.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add dma-channel-mask property in Tegra GPCDMA device tree node.
The property would help to specify the channels to be used in
kernel and reserve few for the firmware. This was previously
achieved by limiting the channel number to 31 in the driver.
This is wrong and does not align with the hardware. Correct this
and update the interrupts property to list all 32 interrupts.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
