Commit Graph

634102 Commits

Author SHA1 Message Date
Alex Deucher
ec9aaaff66 drm/radeon: clarify why we evict vram twice on suspend
Update the comment to explain why we do this.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:33 -04:00
Alex Deucher
a0a71e49f5 drm/amdgpu: clarify why we evict vram twice on suspend
Update the comment to explain why we do this.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:33 -04:00
Alex Deucher
db9635cc14 drm/amdgpu: used cached gca values for vi_read_register (v2)
Using the cached values has less latency for bare metal
and SR-IOV, and prevents reading back bogus values if the
engine is powergated.

v2: fix typo in tile idx calculation

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:32 -04:00
Alex Deucher
34817db6c7 drm/amdgpu/gfx8: use cached raster config values in csb setup
Simplify the code and properly set the csb for harvest values.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:32 -04:00
Alex Deucher
392f0c775c drm/amdgpu/gfx8: cache rb config values
Needed when for SR-IOV and when PG is enabled.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:31 -04:00
Alex Deucher
e3fa76306f drm/amdgpu: add additional cached gca config variables
We need to cache some additional values to handle SR-IOV
and PG.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:30 -04:00
Christian König
b88c8796d8 drm/amdgpu: use amdgpu_vm_get_pd_bo in the GEM code
Instead of messing with the PD directly.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:30 -04:00
Christian König
073440d262 drm/amdgpu: move VM defines into amdgpu_vm.h
Only cleanup, no intended functional change.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:29 -04:00
Christian König
7802301611 drm/amdgpu: move fence and ring defines into amdgpu_ring.h
Only cleanup, no intended functional change.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:29 -04:00
Christian König
5611350499 drm/amdgpu: move sync handling into a separate header
Only cleanup, no intended functional change.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:28 -04:00
Christian König
914b4dce4f drm/amdgpu: stop using a bo list entry for the VM PTs
Saves us a bit of memory.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:28 -04:00
Christian König
f7da30d979 drm/amdgpu: move PT validation back into VM code v2
Saves a bunch of CPU cycles when swapping things back in and
allows us to split the VM headers into a separate file.

v2: rename parameters

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:27 -04:00
Christian König
a7d64de659 drm/amdgpu: remove adev pointer from struct amdgpu_bo v2
It's completely pointless to have two pointers to the
device in the same structure.

v2: rename function to amdgpu_ttm_adev, fix typos

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:26 -04:00
Tom St Denis
f3fd451263 drm/amd/amdgpu: Enable UVD PG on Tonga
Tested by reading tile/clk bits during load/idle.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:26 -04:00
Tom St Denis
97f40ef049 drm/amd/powerplay: Enable UVD powergating for SMU7
This patch enables detecting VCE/UVD PG features and fixes the
UVD powergate function.

Tested on a Tonga (by reading UVD tile/clk bits during playback/idle).

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:25 -04:00
Christian König
f8991bab1a drm/amdgpu: update the shadow PD together with the real one v2
Far less CPU cycles needed for this approach.

v2: fix typo

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:25 -04:00
Frank Min
42e8cb5001 drm/amdgpu:wptr poll address of gfx8 is needed
for GFX8, gfx ring's wptr_addr is needed by SRIOV & CP for polling.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:24 -04:00
Monk Liu
4c2b2453ef drm/amdgpu:properly fix some JumpTable issues
we found some MEC ucode leads to IB test fail or even
ring test fail if Jump Table of it is not start in
FW bo with page aligned address, fixed by always make
JT address page aligned.

we don't need to patch JT2 for MEC2, because for VI,
MEC2 is a copy of MEC1, thus when converting fw_type
for MEC_JT2 we just return MEC1,hw can use the same
JT for both MEC1 & MEC2.

above two change fixed some ring/ib test failure issue
for some version of MEC ucode.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:23 -04:00
Monk Liu
bed5712e1a drm/amdgpu:add MEC_STORAGE ucode id for sriov
for sriov, SMC need MEC_STORAGE reserved in fw bo.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Frank Min <frank.min@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:23 -04:00
Frank Min
ac00bbf32b drm/amdgpu:add callback in cgs for sriov detect
Signed-off-by: Frank Min <Frank.Min@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:22 -04:00
Frank Min
f501a7e550 drm/amdgpu:fw bo should be in VRAM for SRIOV
for GTT memory SMC can only access it within PF space, which is not
used for SRIOV case, thus for SRIOV case, we let SMC use FB space for
ucode bo.

Signed-off-by: Frank Min <frank.min@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:22 -04:00
Frank Min
01ab960d49 drm/amdgpu:keep bo pinned in prefered domain
Signed-off-by: Frank Min <Frank.Min@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:21 -04:00
Monk Liu
4bc10d168a drm/amdgpu:use smc_index_11 for VI
for VI smc, index_0 to index_8 are all not safe,
they may used by BIOS/FW, and index_11 is reserved
only for driver.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:20 -04:00
Frank Min
e1d99217d0 drm/amdgpu:add one more fiji device id
Signed-off-by: Frank Min <Frank.Min@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:20 -04:00
Baoyou Xie
f8a4c11b0a drm/amd/powerplay: mark symbols static where possible
We get a few warnings when building kernel with W=1:
drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/fiji_smumgr.c:162:5: warning: no previous prototype for 'fiji_setup_pwr_virus' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/fiji_smc.c:2052:5: warning: no previous prototype for 'fiji_program_mem_timing_parameters' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/polaris10_smumgr.c:175:5: warning: no previous prototype for 'polaris10_avfs_event_mgr' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_hwmgr.c:69:10: warning: no previous prototype for 'cz_get_eclk_level' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c:92:26: warning: no previous prototype for 'cast_phw_smu7_power_state' [-Wmissing-prototypes]
....

In fact, these functions are only used in the file in which they are
declared and don't need a declaration, but can be made static.
So this patch marks these functions with 'static'.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:19 -04:00
Baoyou Xie
22e5808eba drm/radeon: mark symbols static where possible
We get 4 warnings when building kernel with W=1:
drivers/gpu/drm/radeon/si.c:7850:5: warning: no previous prototype for 'si_vce_send_vcepll_ctlreq' [-Wmissing-prototypes]
drivers/gpu/drm/radeon/radeon_dp_mst.c:226:21: warning: no previous prototype for 'radeon_mst_best_encoder' [-Wmissing-prototypes]
drivers/gpu/drm/radeon/radeon_dp_mst.c:344:26: warning: no previous prototype for 'radeon_mst_find_connector' [-Wmissing-prototypes]
drivers/gpu/drm/radeon/radeon_dp_mst.c:600:6: warning: no previous prototype for 'radeon_dp_mst_encoder_destroy' [-Wmissing-prototypes]

In fact, these functions are only used in the file in which they are
declared and don't need a declaration, but can be made static.
So this patch marks these functions with 'static'.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:19 -04:00
Baoyou Xie
297b12862d drm/radeon: add missing header dependencies
We get a few warnings when building kernel with W=1:
drivers/gpu/drm/radeon/radeon_clocks.c:35:10: warning: no previous prototype for 'radeon_legacy_get_engine_clock' [-Wmissing-prototypes]
drivers/gpu/drm/radeon/atombios_encoders.c:75:1: warning: no previous prototype for 'atombios_get_backlight_level' [-Wmissing-prototypes]
drivers/gpu/drm/radeon/r600_cs.c:2268:5: warning: no previous prototype for 'r600_cs_parse' [-Wmissing-prototypes]
drivers/gpu/drm/radeon/evergreen_cs.c:2671:5: warning: no previous prototype for 'evergreen_cs_parse' [-Wmissing-prototypes]
....

In fact, these functions are declared
in drivers/gpu/drm/radeon/radeon_asic.h,
so this patch adds missing header dependencies.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:18 -04:00
Junwei Zhang
ef704318d3 drm/amd/amdgpu: bump version for memory query info
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:18 -04:00
Junwei Zhang
e0adf6c86c drm/amd/amdgpu: unify memory query info interface
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:17 -04:00
Christian König
6a7f76e70f drm/amdgpu: add VRAM manager v2
Split VRAM allocations into 4MB blocks.

v2: fix typo in comment, some suggested cleanups
v3: document how to disable the feature, fix rebase issue

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:16 -04:00
Christian König
8892f153c8 drm/amdgpu: enable amdgpu_move_blit to handle multiple MM nodes v2
This allows us to move scattered buffers around.

v2: fix a couple of typos, handle scattered to scattered moves as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:16 -04:00
Christian König
63e0ba40e5 drm/amdgpu: handle multiple MM nodes in the VMs v2
This allows us to map scattered VRAM BOs to the VMs.

v2: fix offset handling, use pfn instead of offset,
    fix PAGE_SIZE != AMDGPU_GPU_PAGE_SIZE case

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:15 -04:00
Christian König
d2e938701a drm/amdgpu: set at least the node size in the gtt manager
Otherwise the new VM code becomes confused.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:15 -04:00
Christian König
56de55a1a8 drm/amdgpu: use explicit limit for VRAM_CONTIGUOUS
Split VRAM won't have a valid offset, so just set an explicit limit
when the flag is given to trigger reallocation if necessary.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:14 -04:00
Christian König
03f48dd5d2 drm/amdgpu: add AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS flag v3
Add a flag noting that a BO must be created using linear VRAM
and set this flag on all in kernel users where appropriate.

Hopefully I haven't missed anything.

v2: add it in a few more places, fix CPU mapping.
v3: rename to VRAM_CONTIGUOUS, fix typo in CS code.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:13 -04:00
Junwei Zhang
cfa32556e5 drm/amd/amdgpu: add info about vram and gtt max allocation size
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:13 -04:00
Junwei Zhang
9f6163e7e3 drm/amd/amdgpu: add info about vram and gtt total size
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:12 -04:00
Alex Deucher
46c9cc11a5 drm/amdgpu/dce6: don't enable HPD Rx interrupts
Not used currently.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:12 -04:00
Alex Deucher
079ea1901b drm/amdgpu/dce6: RMW hpd registers
No need to hard code the entire register to just
set/clear one bit.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:11 -04:00
Alex Deucher
34386043d9 drm/amdgpu/dce6: simplify hpd code
Use an address offset like other dce code.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:10 -04:00
Alex Deucher
d2486d25bd drm/amdgpu/dce11: simplify hpd code
use the hpd enum directly as an index

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:10 -04:00
Alex Deucher
03ae23b93b drm/amdgpu/dce8: RMW hpd registers
No need to hard code the entire register to just
set/clear one bit.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:09 -04:00
Alex Deucher
6753ac2bf4 drm/amdgpu/dce10: simplify hpd code
use the hpd enum directly as an index

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:09 -04:00
Alex Deucher
2285b91cd2 drm/amdgpu/dce8: simplify hpd code
Use an address offset like other dce code.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:08 -04:00
Emily Deng
0f66356d24 drm/amd/amdgpu: For virtual display, enable multi crtcs. (v3)
Enable multi crtcs for virtual display, user can set the number of crtcs
by amdgpu module parameter  virtual_display.

v2: make timers per crtc
v3: agd: simplify implementation

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-By: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:07 -04:00
Alex Deucher
483ef98588 drm/amdgpu: rename amdgpu_whether_enable_virtual_display
to match the other functions in that file.

Reviewed-By: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:07 -04:00
Alex Deucher
87320cafbc Revert "drm/amdgpu: Add virtual connector and encoder macros."
This reverts commit 16925c92db.

This is no longer necessary.

Reviewed-By: Emily Deng <Emily.Deng@amd.com>
2016-10-25 14:38:06 -04:00
Alex Deucher
66264ba804 drm/amdgpu: simplify encoder and connector setup (v2)
No need to emulate all of the stuff for real hw.

v2: warning fix

Reviewed-By: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:06 -04:00
Alex Deucher
9405e47dba drm/amdgpu/virtual_dce: clean up interrupt handling
We handle the virtual interrupts from a timer so no
need to try an look like we are handling IV ring events.

Reviewed-By: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:05 -04:00
Alex Deucher
bf2335a54e drm/amdgpu/virtual_dce: no need to an irq process callback
Virtual crtcs interrupts do not show up in the IV ring,
so it will never be called.

Reviewed-By: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:04 -04:00