Commit Graph

72132 Commits

Author SHA1 Message Date
Matt Coffin
aec1d8703e drm/amdgpu/pm: Account for extra separator characters in sysfs interface
Currently, the the input to the pp_od_clk_voltage sysfs interface has
two adjacent separator characters, i.e. "\n\0", then we try to parse an
argument out of the empty string, whereas we really should just ignore
this case, and treat any number of adjacent separators as one separator
for arguments.

We do this here by simply skipping the argument parsing for all
empy-string arguments.

An example test case would be `echo 's  1 900' > pp_od_clk_voltage`
(note the two spaces after the 's'.

This also solves the issue where the written string ends with both a
newline, and a nul-terminator, '\n\0', as is the case for `echo 's 1
900' > pp_od_clk_voltage` since the recent rebase.

Got lost during code rebase/merge. No need to port this to other
branches.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Matt Coffin <mcoffin13@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-01 11:51:46 -05:00
Evan Quan
ce7c1d0476 Revert "Revert "drm/amdgpu: Fix NULL dereference in dpm sysfs handlers""
This reverts commit 2456c290a7. Got lost
during code rebase/merge. No need to port this to other branches.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-01 11:51:46 -05:00
Lang Yu
cd63989e0e drm/amd/amdkfd: adjust dummy functions' placement
Move all the dummy functions in amdgpu_amdkfd.c to
amdgpu_amdkfd.h as inline functions.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-28 14:58:27 -05:00
Alex Deucher
33cf440d59 drm/amdgpu: disable gpu reset on Vangogh for now
Until the issues in the SMU firmware are fixed.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
2021-01-28 14:58:10 -05:00
Mario Kleiner
efa18405ba drm/amd/display: Fix HDMI deep color output for DCE 6-11.
This fixes corrupted display output in HDMI deep color
10/12 bpc mode at least as observed on AMD Mullins, DCE-8.3.

It will hopefully also provide fixes for other DCE's up to
DCE-11, assuming those will need similar fixes, but i could
not test that for HDMI due to lack of suitable hw, so viewer
discretion is advised.

dce110_stream_encoder_hdmi_set_stream_attribute() is used for
HDMI setup on all DCE's and is missing color_depth assignment.

dce110_program_pix_clk() is used for pixel clock setup on HDMI
for DCE 6-11, and is missing color_depth assignment.

Additionally some of the underlying Atombios specific encoder
and pixelclock setup functions are missing code which is in
the classic amdgpu kms modesetting path and the in the radeon
kms driver for DCE6/DCE8.

encoder_control_digx_v3() - Was missing setup code wrt. amdgpu
and radeon kms classic drivers. Added here, but untested due to
lack of suitable test hw.

encoder_control_digx_v4() - Added missing setup code.
Successfully tested on AMD mullins / DCE-8.3 with HDMI deep color
output at 10 bpc and 12 bpc.

Note that encoder_control_digx_v5() has proper setup code in place
and is used, e.g., by DCE-11.2, but this code wasn't used for deep
color setup due to the missing cntl.color_depth setup in the calling
function for HDMI.

set_pixel_clock_v5() - Missing setup code wrt. classic amdgpu/radeon
kms. Added here, but untested due to lack of hw.

set_pixel_clock_v6() - Missing setup code added. Successfully tested
on AMD mullins DCE-8.3. This fixes corrupted display output at HDMI
deep color output with 10 bpc or 12 bpc.

Fixes: 4562236b3b ("drm/amd/dc: Add dc display driver (v2)")

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25 17:49:47 -05:00
Mario Kleiner
1916866dfa drm/amd/display: Fix 10/12 bpc setup in DCE output bit depth reduction.
In set_clamp(), the comments and definitions for the COLOR_DEPTH_101010
and COLOR_DEPTH_121212 cases directly contradict the code comment which
explains how this should work, whereas the COLOR_DEPTH_888 case
is consistent with the code comments. Comment says the bitmask should
be chosen to align to the top-most 10 or 12 MSB's on a 14 bit bus, but
the implementation contradicts that: 10 bit case sets a mask for 12 bpc
clamping, whereas 12 bit case sets a mask for 14 bpc clamping.

Note that during my limited testing on DCE-8.3 (HDMI deep color)
and DCE-11.2 (DP deep color), this didn't have any obvious ill
effects, neither did fixing it change anything obvious for the
better, so this fix may be inconsequential on DCE, and just
reduce the confusion of innocent bystanders when reading the code
and trying to investigate problems with 10 bpc+ output.

Fixes: 4562236b3b ("drm/amd/dc: Add dc display driver (v2)")

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25 17:49:41 -05:00
Arnd Bergmann
4a517faa34 amdgpu: fix clang build warning
clang warns about the -mhard-float command line arguments
on architectures that do not support this:

clang: error: argument unused during compilation: '-mhard-float' [-Werror,-Wunused-command-line-argument]

Move this into the gcc-specific arguments.

Fixes: e77165bf7b ("drm/amd/display: Add DCN3 blocks to Makefile")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25 17:48:46 -05:00
Dan Carpenter
d3abc78f4f drm/amd/display: Fix a potential NULL dereference
The debug printk dereferences "link->link_enc" before we have ensured
that it is non-NULL.  Fix this potential NULL derefence by moving the
printk after the check.

Fixes: 64ff088242 ("drm/amd/display: Log link/connector info provided in BIOS object table")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25 17:48:02 -05:00
Jonathan Gray
23a63e91c1 drm/amd/display: change license of color_table.c
Change the license of color_table.c to match color_table.h granting
permission to modify and distribute.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25 17:47:57 -05:00
Colin Ian King
5993e79398 drm/amdgpu: Fix masking binary not operator on two mask operations
Currently the ! operator is incorrectly being used to flip bits on
mask values. Fix this by using the bit-wise ~ operator instead.

Addresses-Coverity: ("Logical vs. bitwise operator")
Fixes: 3c9a7b7d6e ("drm/amdgpu: update mmhub mgcg&ls for mmhub_v2_3")
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25 17:47:05 -05:00
Arunpravin
eb3b425166 drm/amd/pm: store and reinstate swsmu user power configurations
store swsmu user power configurations which include
power limit, clock frequencies, fan speed and fan mode
on suspend and reinstate on resume.

V2: Addressed Lijo's review comments
     added a function to set clock interdependencies
     add check on fan control mode to reapply fan speed

V3: Addressed review comments from Alex
     moved store logic and reinstate function call into swSMU

V4: added a logic to keep off storing configurations in suspend

V5: Addressed review comments from Lijo
     add a restore flag
     give restore priority to mclk comparing fclk and socclk

Signed-off-by: Arunpravin <Arunpravin.PaneerSelvam@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25 17:47:00 -05:00
Jingwen Chen
64dcf2f01d drm/amd/amdgpu: add error handling to amdgpu_virt_read_pf2vf_data
[Why]
when vram lost happened in guest, try to write vram can lead to
kernel stuck.

[How]
When the readback data is invalid, don't do write work, directly
reschedule a new work.

Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
Reviewed-by: Monk Liu<monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25 17:46:48 -05:00
Lang Yu
9024fb0815 drm/amd/display: fix 64-bit division issue on 32-bit OS
Replace "/" with div_u64 for 32-bit OS. On 32-bit OS,
the use of "/" for 64-bit division will cause build error,
i.e. "__udivdi3/__divdi3 undefined!".

Fixes: ea7154d8d9 ("drm/amd/display: Update dcn30_apply_idle_power_optimizations() code")
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25 17:45:53 -05:00
Pratik Vishwakarma
d80d3da950 Revert "drm/amd/display: Tune min clk values for MPO for RV"
This reverts commit 57eeaf47a6.
Original issue of flash line when MPO enabled on idle screen
was fixed by raising clocks. This had negative effect of extra
power being drained. With the upstream commit 9d03bb1020
("drm/amd/display: disable dcn10 pipe split by default")
flash line issue was fixed and had positive effect for
battery life. Hence this patch is no more required.

Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25 17:45:21 -05:00
Horace Chen
91fb309d82 drm/amdgpu: race issue when jobs on 2 ring timeout
Fix a racing issue when jobs on 2 rings timeout simultaneously.

If 2 rings timed out at the same time, the
amdgpu_device_gpu_recover will be reentered. Then the
adev->gmc.xgmi.head will be grabbed by 2 local linked list,
which may cause wild pointer issue in iterating.

lock the device earily to prevent the node be added to 2
different lists.

also increase karma for the skipped job since the job is also
timed out and should be guilty.

Signed-off-by: Horace Chen <horace.chen@amd.com>
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25 17:45:16 -05:00
Felix Kuehling
eda1068dc9 drm/amdgpu: Make contiguous pinning optional
Enable pinning of VRAM without forcing it to be contiguous. When memory is
already pinned, make sure it's contiguous if requested.

Suggested-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25 17:45:10 -05:00
Huang Rui
dcb820d185 drm/amdgpu: remove gpu info firmware of green sardine
The ip discovery is supported on green sardine, it doesn't need gpu info
firmware anymore.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21 09:55:23 -05:00
Felix Kuehling
19fef554bd drm/amdkfd: Enable userptr support when KFD is enabled
ROCm user mode depends on userptr support. Without it, KFD is basically
useless.

Make sure HSA_AMD selects the same options as DRM_AMDGPU_USERPTR to avoid
broken configurations where userptr gets enabled but its dependencies are
disabled.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Philip Yang <philip.yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21 09:55:16 -05:00
Huang Rui
e484de44b1 drm/amd/pm: print the timeout of smc message
This patch is to help firmware designer to know the smc message timeout
status.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21 09:55:05 -05:00
Feifei Xu
2b3a1f515f drm/amdgpu:Add pcie gen5 support in pcie capability.
Add PCIE_SPEED_32_0GT and PCIE GEN5 support for amdgpu.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21 09:54:56 -05:00
Jinzhou Su
366468ff6c drm/amdgpu: Allow GfxOff on Vangogh as default
Send allow GfxOff message to SMU to enter GfxOff
mode as default.

Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21 09:54:50 -05:00
Jiapeng Zhong
59f4ededd9 drm/amdgpu: Assign boolean values to a bool variable
Fix the following coccicheck warnings:

./drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c:
1009:6-16: WARNING: Assignment of 0/1 to bool variable.

./drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c:
200:2-10: WARNING: Assignment of 0/1 to bool variable.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Jiapeng Zhong <abaci-bugfix@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21 09:54:46 -05:00
Colin Ian King
a49054353e drm/amd/display: Fix spelling mistake of function name
There are two spelling mistakes of the function name, fix this
by using __func__ instead of a hard coded name string.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21 09:54:41 -05:00
Bhawanpreet Lakha
ea7154d8d9 drm/amd/display: Update dcn30_apply_idle_power_optimizations() code
Update the function for idle optimizations
-remove hardcoded size
-enable no memory-request case
-add cursor copy
-update mall eligibility check case

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21 09:54:34 -05:00
Bhawanpreet Lakha
7fc75382ec drm/amd/display: Dynamic cursor cache size for MALL eligibility check
[Why]
Currently we use the maximum possible cursor cache size when deciding if we
should attempt to enable MALL, but this prevents us from enabling the
feature for certain key use cases.

[How]
 - consider cursor bpp when calculating if the cursor fits

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21 09:54:26 -05:00
Bhawanpreet Lakha
b153d8d7d0 drm/amd/display: Enable programing of MALL watermarks
-Uncomment watermark set d
-This populates the wm table so that it can be sent to PMFW
-This watermark table is used when we are in mall stutter

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21 09:54:18 -05:00
Aaron Liu
3c9a7b7d6e drm/amdgpu: update mmhub mgcg&ls for mmhub_v2_3
Starting from vangogh, the ATCL2 and DAGB0 registers relative
to mgcg/ls has changed.

For MGCG:
Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL.

For MGLS:
Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL.
Add DAGB0_(WR/RD)_CGTT_CLK_CTRL registers.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21 09:54:07 -05:00
Jinzhou Su
860cc26a01 drm/amdgpu: Add RLC_PG_DELAY_3 for Vangogh
Driver should enable the CGPG feature for RLC in safe mode to
prevent any misalignment or conflict in middle of any power
feature entry/exit sequence.
Achieved by setting RLC_PG_CNTL.GFX_POWER_GATING_ENABLE = 0x1,
and RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG
hysteresis value in refclk count.

Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21 09:53:33 -05:00
Prike Liang
d96dd7ef3f drm/amdgpu/pm: no need GPU status set since mmnbif_gpu_BIF_DOORBELL_FENCE_CNTL added in FSDL
In the renoir there is no need GpuChangeState message set to exit gfxoff in the s0i3 resume since
mmnbif_gpu_BIF_DOORBELL_FENCE_CNTL has been added in the s0i3 FSDL.

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21 09:53:22 -05:00
Jinzhou Su
91067d8959 drm/amdgpu: modify GCR_GENERAL_CNTL for Vangogh
GCR_GENERAL_CNTL is defined differently in gc_10_1_0_offset.h and
gc_10_3_0_offset.h. Update GCR_GENERAL_CNTL for Vangogh.

Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:23 -05:00
Jinzhou Su
d3dc8f4d18 drm/amdgpu: Remove GFXOFF MASK for Vangogh
1. Remove PP_GFXOFF_MASK and then GFXOFF can be enabled
    by user space.
 2. GFXOFF is still disabled on Vangogh by default.
 3. When GFXOFF feature on Vangogh landed, will enable
    GFXOFF by default.
 4. GFXOFF can be enabled by debugfs interface amdgpu_gfxoff.

Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:23 -05:00
Aric Cyr
c711879f50 drm/amd/display: 3.2.119
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:22 -05:00
Anthony Koo
f306892b7c drm/amd/display: [FW Promotion] Release 0.0.48
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:22 -05:00
Jake Wang
5383007716 drm/amd/display: Update dram_clock_change_latency for DCN2.1
[WHY]
dram clock change latencies get updated using ddr4 latency table, but
that update does not happen before validation. This value
should not be the default and should be number received from
df for better mode support.
This may cause a PState hang on high refresh panels with short vblanks
such as on 1080p 360hz or 300hz panels.

[HOW]
Update latency from 23.84 to 11.72.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Reviewed-by: Sung Lee <Sung.Lee@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:22 -05:00
Aric Cyr
8aeb42bd2b drm/amd/display: Allow PSTATE chnage when no displays are enabled
[Why]
When no displays are currently enabled, display driver should not
disallow PSTATE switching.

[How]
Allow PSTATE switching if either the active configuration supports it,
or there are no active displays.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:21 -05:00
Bing Guo
4ef37e2703 drm/amd/display: Fix dml20v2_ModeSupportAndSystemConfigurationFull() to check DesiredBPP.
Why:
dml20v2_ModeSupportAndSystemConfigurationFull() didn't check against
DesiredBPP, so it doesn't work correctly when DesiredBPP can't be satisfied.

How:
Port the TruncToValidBPP() version from display_mode_vba_21.c to
display_mode_vba_20v2.c.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Bing Guo <bing.guo@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:21 -05:00
George Shen
64ff088242 drm/amd/display: Log link/connector info provided in BIOS object table
[Why/How]
Add logging statements to assist in debugging
errors in the BIOS object table.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:21 -05:00
Wyatt Wood
16ca2d465d drm/amd/display: Allow dmu_stg to support cached inbox for dmub
[Why]
FW version check doesn't allow dmu_stg to support cached inbox,
which yields much better performance than region 4.

[How]
Check a range of fw versions, rather than a simple greater than check.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:20 -05:00
Bing Guo
69d5c7f398 drm/amd/display: Change function decide_dp_link_settings to avoid infinite looping
Why:
Function decide_dp_link_settings() loops infinitely when required bandwidth
can't be supported.

How:
Check the required bandwidth against verified_link_cap before trying to
find a link setting for it.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Bing Guo <bing.guo@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:20 -05:00
Nicholas Kazlauskas
d740a39c3d drm/amd/display: Fix reset sequence with driver direct DMCUB fw load
[Why]
DMCUB encounters a page fault/double exception with driver direct load
because DMCUB is not held in soft reset after releasing secure reset.

The clean shutdown sequence via GPINT is also not executed in this
sequence which leaves hardware behavior in an indeterminate state.

[How]
Move reset earlier in the sequence.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:19 -05:00
Nicholas Kazlauskas
44a09e3d95 drm/amd/display: Guard against NULL pointer deref when get_i2c_info fails
[Why]
If the BIOS table is invalid or corrupt then get_i2c_info can fail
and we dereference a NULL pointer.

[How]
Check that ddc_pin is not NULL before using it and log an error if it
is because this is unexpected.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:19 -05:00
Nicholas Kazlauskas
eee9647490 drm/amd/display: Allow dmub srv hardware reset before HW init
[Why]
We need hardware reset before hardware init for backdoor loading when
we're reusing the framebuffer memory.

[How]
This doesn't run if the hardware isn't already in reset from software
perspective. The reset function has register level checks so just
remove the software one here.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:19 -05:00
Stylon Wang
a0ffc3fd67 drm/amd/display: Report Freesync to vrr_range debugfs entry in DRM
[Why]
Since Linux 5.9.0, DRM has provided vrr_range debugfs for
all connectors. Reporting Freesync capability to vrr_range
debugfs entry registered in Linux DM no longer works.

[How]
Report min/max vertical frequency to vrr_range debugfs entrry
created by DRM connectors. Remove vrr_range debugfs entry from
Linux DM.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Stylon Wang <stylon.wang@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:18 -05:00
Nicholas Kazlauskas
d2138be383 drm/amd/display: Use hardware sequencer functions for PG control
[Why & How]
These can differ per ASIC or not be present. Don't call the dcn20 ones
directly but rather the ones defined by the ASIC init table.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:18 -05:00
Sung Lee
7a214cd846 drm/amd/display: DCN2X Find Secondary Pipe properly in MPO + ODM Case
[WHY]
Previously as MPO + ODM Combine was not supported, finding secondary pipes
for each case was mutually exclusive. Now that both are supported at the same
time, both cases should be taken into account when finding a secondary pipe.

[HOW]
If a secondary pipe cannot be found based on previous bottom pipe,
search for a second pipe using next_odm_pipe instead.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:18 -05:00
Mike Hsieh
21b882de6a drm/amd/display: disable FEC while using eDP
[Why]
FEC over eDP support is incomplete.

[How]
Disable FEC over eDP.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Mike Hsieh <chun-wei.hsieh@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:17 -05:00
Vladimir Stempen
617ab85401 drm/amd/display: Fixed corruptions on HPDRX link loss restore
[why]
Heavy corruption or blank screen reported on wake,
with 6k display connected and FEC enabled

[how]
When Disable/Enable stream for display pipes on HPDRX,
DC should take into account ODM split pipes.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:17 -05:00
Jingwen Chen
b43ae488ac drm/amd/amdgpu: remove redundant flush_delayed_work
When using cancel_delayed_work_sync, there's no need
to flush_delayed_work first. This sequence can lead to
a redundant loop of work executing.

Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:17 -05:00
Kevin Wang
9f0837e066 drm/amd/pm: remove unused message SMU_MSG_SpareX
the SpareX is reserved by SMU firmware, the driver is never use it.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20 16:38:16 -05:00
Daniel Vetter
a6b8720c2f Merge tag 'amd-drm-next-5.12-2021-01-20' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-5.12-2021-01-20:

amdgpu:
- Fix non-x86 build
- W=1 fixes from Lee Jones
- Enable GPU reset on Navy Flounder
- Kernel doc fixes
- SMU workload profile fixes for APUs
- Display updates
- SR-IOV fixes
- Vangogh SMU feature enablment and bug fixes
- GPU reset support for Vangogh
- Misc cleanups

Conflicts:
	drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c

Resolve the conflict by picking the initialization value from amd from
f03e80d2e8 ("drm/amd/display: Initialize stack variable") over the
one Linus picked in 61d791365b ("drm/amd/display: avoid
uninitialized variable warning"). It shouldn't matter.

From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210120060951.22600-1-alexander.deucher@amd.com
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
2021-01-20 13:08:18 +01:00