Commit Graph

222457 Commits

Author SHA1 Message Date
Chris Wilson
ab5793ad3a drm/i915: Tweak on-error bbaddr parsing for clarity
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-25 15:03:24 +00:00
Chris Wilson
312817a39f drm/i915: Only save and restore fences for UMS
With KMS, we can simply relinquish the fence when we idle the GPU and
reassign it upon first use.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-25 15:03:22 +00:00
Daniel Vetter
c6642782b9 drm/i915: Add a mechanism for pipelining fence register updates
Not employed just yet...

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-25 15:01:39 +00:00
Chris Wilson
caea7476d4 drm/i915: More accurately track last fence usage by the GPU
Based on a patch by Daniel Vetter.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-24 13:30:52 +00:00
Chris Wilson
a7a09aebe8 drm/i915: Rework execbuffer pinning
Avoid evicting buffers that will be used later in the batch in order to
make room for the initial buffers by pinning all bound buffers in a
single pass before binding (and evicting for) fresh buffer.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-24 13:30:51 +00:00
Chris Wilson
919926aeb3 drm/i915: Thread the pipelining ring through the callers.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:19:16 +00:00
Chris Wilson
576ae4b8e4 drm/i915: Extend hangcheck timeout
... reduce the frequency of checking to further reduce the wakeups and
CPU overhead.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:19:15 +00:00
Chris Wilson
dddbc0e525 drm/i915: Remove a defunct BUG_ON
This used to check the precondition that all fences were to be located
in a mappable area, redundant now as those two parameters are combined
into one.

After pinning, we assert that the buffer is bound into the desired
region.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:19:15 +00:00
Chris Wilson
b6913e4bdb drm/i915: Move the implementation details of PIPE_CONTROL to the ringbuffer
The pipe control object is allocated by the device for the sole use of the
render ringbuffer. Move this detail from the general code to the render
ring buffer initialisation.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:19:14 +00:00
Chris Wilson
748ebc6017 drm/i915: Record fence registers on error.
Having seen the effects of erroneous fencing on the batchbuffer, a
useful sanity check is to record the fence registers at the time of an
error.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:19:13 +00:00
Chris Wilson
7bdc9ab00b agp/intel: Remove duplicate const
drivers/char/agp/intel-gtt.c:340:48: warning: duplicate const

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:19:13 +00:00
Chris Wilson
92b88aeb1a drm/i915: Not all mappable regions require GTT fence regions
Combining map_and_fenceable revealed a bug in
i915_gem_object_gtt_size() in that it always computed the appropriate
fence size for the object regardless of tiling state which caused us to
over-allocate linear buffers when binding to the GTT.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:19:13 +00:00
Chris Wilson
05394f3975 drm/i915: Use drm_i915_gem_object as the preferred type
A glorified s/obj_priv/obj/ with a net reduction of over a 100 lines and
many characters!

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:19:10 +00:00
Daniel Vetter
185cbcb304 drm/i915: no more agp for gem
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:14:48 +00:00
Daniel Vetter
4080775b60 intel-gtt: export api for drm/i915
Just some minor shuffling to get rid of any agp traces in the
exported functions.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:14:47 +00:00
Daniel Vetter
7c2e6fdf45 drm/i915: move gtt handling to i915_gem_gtt.c
No more drm_*_agp in i915_gem.c!

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:14:47 +00:00
Daniel Vetter
cb16b67b5c agp: kill agp_rebind_memory
Its only user, intel-gtt.c is now gone.

Cc: Dave Airlie <airlied@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:14:46 +00:00
Daniel Vetter
76aaf22016 drm/i915: restore gtt on resume in the drm instead of in intel-gtt.ko
This still uses the agp functions to actually reinstate the mappings
(with a gross hack to make agp cooperate), but it wires everything
up correctly for the switchover.

The call to agp_rebind_memory can be dropped because all non-kms drivers
do all their rebinding on EnterVT.

v2: Be more paranoid and flush the chipset cache after restoring gtt
mappings.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:14:46 +00:00
Daniel Vetter
93a37f20ea drm/i915: track objects in the gtt
This is required to restore gtt mappings on resume when agp is gone.

The right way to do this would be to make sturct drm_mm_node embeddable
and use the allocation list maintained by the drm memory manager. But
that's a bigger project. Getting rid of the per bo agp_mem will save
more memory than this wastes, anyway.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:14:45 +00:00
Daniel Vetter
f050a8abbd agp: kill agp_flush_chipset and corresponding ioctl
The intel drm calls the chipset functions now directly. Userspace
never called the corresponding ioctl, hence it can be killed, too.

Cc: Dave Airlie <airlied@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:14:45 +00:00
Daniel Vetter
4af72e2865 drm: kill drm_agp_chipset_flush
No longer used.

Cc: Dave Airlie <airlied@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:14:44 +00:00
Daniel Vetter
40ce657510 drm/i915/gtt: call chipset flush directly
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:14:44 +00:00
Daniel Vetter
23ed992a5e drm/i915|intel-gtt: consolidate intel-gtt.h headers
... and a few other defines.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:14:43 +00:00
Daniel Vetter
ff26860fb5 intel-gtt: fold i81x-only dcache support into the generic driver
Now the intel-gtt.c rewrite is complete!

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:14:43 +00:00
Daniel Vetter
820647b97a intel-gtt: switch i81x to the common initialization helpers
Still a separate agp_bridge_driver because of the i81x-only
dedicated vram support.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:14:42 +00:00
Daniel Vetter
625dd9d331 intel-gtt: switch i81x to the write_entry helpers
Initialization is still done with the old code with a few
added things sprinkled in to make the intel_fake_agp helper
functions work.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:14:42 +00:00
Daniel Vetter
24a6b387af intel-gtt: kill unneeded sandybridge memory types
Used for the now dead agp type_to_mask stuff.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:14:42 +00:00
Daniel Vetter
b47cf66f31 intel-gtt: drop dcache support for i830 and later
i830_check_flags already disallows it, so no need to implement it
in the write_entry function. Seems to be a remnant from i810 support.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:14:41 +00:00
Chris Wilson
e384eafc1c Merge branch 'drm-intel-fixes' into drm-intel-next 2010-11-23 20:13:13 +00:00
Chris Wilson
bcf50e2775 drm/i915: Handle pagefaults in execbuffer user relocations
Currently if we hit a pagefault when applying a user relocation for the
execbuffer, we bail and return EFAULT to the application. Instead, we
need to unwind, drop the dev->struct_mutex, copy all the relocation
entries to a vmalloc array (to avoid any potential circular deadlocks
when resolving the pagefault), retake the mutex and then apply the
relocations.  Afterwards, we need to again drop the lock and copy the
vmalloc array back to userspace.

v2: Incorporate feedback from Daniel Vetter.

Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2010-11-23 20:11:43 +00:00
Chris Wilson
faa60c4174 drm/i915: Contract the magic IPS constants into a direct LUT
... and no need to perform a linear search for the index.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 15:43:40 +00:00
Chris Wilson
c64f7ba5f1 agp/intel: Remove confusion of stolen entries not stolen memory
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 15:43:18 +00:00
Chris Wilson
1b6064d79b agp/intel: Remove the artificial cap on stolen size
Now that the stolen memory does not also steal entries from the GTT, we
can use all the memory the BIOS set aside for the GPU.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 15:42:59 +00:00
Chris Wilson
fe669bf88e drm/i915: Compute physical addresses from base of stolen memory
The GATT is a write-only set of registers, reading from them in the
manner of i915_gtt_to_phys() is supposed to be undefined. However a
simple solution exists as we allocate linear memory from the stolen
area, we can simply add the block offset to the base register. As a
side-effect we recover all the unused stolen GTT entries and so enlarge
our aperture.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 15:42:56 +00:00
Chris Wilson
0b0b053a39 drm/i915/panel: Restore saved value of BLC_PWM_CTL
After a GPU reset, the backlight controller registers may be also reset
to 0. In that case we should restore those to the original values
programmed by the BIOS. Note that we still lack the code to handle the
case where the BIOS failed to program those registers at all...

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 09:54:17 +00:00
Chris Wilson
3685092b71 drm/i915: Avoid oops when capturing NULL ring for inactive pinned buffers
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 08:49:38 +00:00
Chris Wilson
da79de97d2 drm/i915/sdvo: Only enable HDMI encodings only if the commandset is supported
As we conflated intel_sdvo->is_hdmi with both having HDMI support on the
ADD along with having HDMI support on the monitor, we would attempt to
use HDMI encodings even if the interface did not support those commands.

Reported-by: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
Reviewed-by: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
2010-11-22 13:27:29 +00:00
Keith Packard
5f75377db4 drm/i915: Fix restore of 965 fence regs since the register tracing change.
We were reading our 64-bit value in I915_READ64 and returning 32 bits
of it.  The restoration of fence regs at resume then had a zero end
value, and the fence had no effect.

Version 2: Split register access functions into per-size versions

Sharing code between different sizes seemed reasonable when we only
needed a single copy, but as 64-bit access requires its own version,
it makes sense to just split them out for each size.

Reported-by: Peter Clifton <pcjc2@cam.ac.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
[ickle: use a macro to create the various read/write routines]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-22 09:26:22 +00:00
Eric Anholt
cff458c210 drm/i915: Add support for GPU reset on gen6.
This has proven sufficient to recover from a hang of the GPU using the
gem_bad_blit test while at the KMS console then starting X.  When
attempting the same during an X session, the timer doesn't appear to
trigger.

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-22 09:02:07 +00:00
Eric Anholt
75a6898ffd drm/i915: Also reinit the BSD and BLT rings after a GPU reset.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-22 09:01:55 +00:00
Eric Anholt
df9c204285 drm/i915: Correct a comment about the use of the workqueue.
It isn't used for the hangcheck, which does its work right from the
timer trigger, but hangcheck can lead to error state recording, which
is run off of the workqueue.

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-22 08:58:01 +00:00
Chris Wilson
a940a75a9a Merge branch 'drm-intel-next' of arrandale:git/linux-2.6 into drm-intel-next 2010-11-22 08:56:33 +00:00
Chris Wilson
e624ae8e0d Merge branch 'drm-intel-fixes' into drm-intel-next
Conflicts:
	drivers/gpu/drm/i915/i915_gem.c
2010-11-22 08:51:36 +00:00
Chris Wilson
4ab0fbd3a2 Merge remote branch 'linus' into drm-intel-fixes 2010-11-22 08:47:43 +00:00
Chris Wilson
c4a1d9e4dc drm/i915: Capture interesting display registers on error
When trying to diagnose mysterious errors on resume, capture the
display register contents as well.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-22 08:08:19 +00:00
Chris Wilson
c724e8a940 drm/i915: Capture pinned buffers on error
The pinned buffers are useful for diagnosing errors in setting up state
for the chipset, which may not necessarily be 'active' at the time of
the error, e.g. the cursor buffer object.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-22 08:07:02 +00:00
Linus Torvalds
3561d43fd2 Linux 2.6.37-rc3 2010-11-21 15:18:56 -08:00
Chris Wilson
f3c91c1dea drm/i915: Only save/restore cursor regs if !KMS
Under KMS, restoring the cursor is handled upon modeswitch in order to
avoid enabling an undefined set of registers. At the moment, the cursor
is restored before the aperture and modes are fully setup causing some
invalid access during resume, such as:

  PGTBL_ER: 0x00040000
    Invalid GTT entry during Cursor Fetch

Fix this by only performing cursor register save/restore under UMS where
it is done in the correct sequence.

Reported-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-21 09:56:00 +00:00
Chris Wilson
d1d788302e drm/i915: Prevent integer overflow when validating the execbuffer
Commit 2549d6c2 removed the vmalloc used for temporary storage of the
relocation lists used during execbuffer. However, our use of vmalloc was
being protected by an integer overflow check which we do want to
preserve!

Reported-by: Dan Carpenter <error27@gmail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-21 09:30:58 +00:00
Linus Torvalds
b86db47442 Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4
* 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4:
  ext4: Add EXT4_IOC_TRIM ioctl to handle batched discard
  fs: Do not dispatch FITRIM through separate super_operation
  ext4: ext4_fill_super shouldn't return 0 on corruption
  jbd2: fix /proc/fs/jbd2/<dev> when using an external journal
  ext4: missing unlock in ext4_clear_request_list()
  ext4: fix setting random pages PageUptodate
2010-11-19 19:46:45 -08:00