The highlights for the driver support this time are
- Qualcomm platforms gain support for the Qualcomm Secure Execution
Environment firmware interface to access EFI variables on certain
devices, and new features for multiple platform and firmware drivers.
- Arm FF-A firmware support gains support for v1.1 specification features,
in particular notification and memory transaction descriptor changes.
- SCMI firmware support now support v3.2 features for clock and DVFS
configuration and a new transport for Qualcomm platforms.
- Minor cleanups and bugfixes are added to pretty much all the active
platforms: qualcomm, broadcom, dove, ti-k3, rockchip, sifive, amlogic,
atmel, tegra, aspeed, vexpress, mediatek, samsung and more.
In particular, this contains portions of the treewide conversion to
use __counted_by annotations and the device_get_match_data helper.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmVC10IACgkQYKtH/8kJ
UifFoQ//Tw7aux88EA2UkyL2Wulv80NwRQn3tQlxI/6ltjBX64yeQ6Y8OzmYdSYK
20NEpbU7VWOFftN+D6Jp1HLrvfi0OV9uJn3WiTX3ChgDXixpOXo4TYgNNTlb9uZ4
MrSTG3NkS27m/oTaCmYprOObgSNLq1FRCGIP7w4U9gyMk9N9FSKMpSJjlH06qPz6
WBLTaIwPgBsyrLfCdxfA1y7AFCAHVxQJO4bp0VWSIalTrneGTeQrd2FgYMUesQ2e
fIUNCaU4mpmj8XnQ/W19Wsek8FRB+fOh0hn/Gl+iHYibpxusIsn7bkdZ5BOJn2J0
OY3C1biopaaxXcZ+wmnX9X0ieZ3TDsHzYOEf0zmNGzMZaZkV8kQt4/Ykv77xz6Gc
4Bl6JI5QZ4rTZvlHYGMYxhy3hKuB31mO2rHbei7eR7J7UmjzWcl5P6HYfCgj7wzH
crIWj1IR1Nx6Dt/wXf3HlRcEiAEJ2D0M3KIFjAVT239TsxacBfDrRk+YedF2bKbn
WMYfVM6jJnPOykGg/gMRlttS/o/7TqHBl3y/900Idiijcm3cRPbQ+uKfkpHXftN/
2vOtsw7pzEg7QQI9GVrb4drTrLvYJ7GQOi4o0twXTCshlXUk2V684jvHt0emFkdX
ew9Zft4YLAYSmuJ3XqGhhMP63FsHKMlB1aSTKKPeswdIJmrdO80=
=QIut
-----END PGP SIGNATURE-----
Merge tag 'soc-drivers-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"The highlights for the driver support this time are
- Qualcomm platforms gain support for the Qualcomm Secure Execution
Environment firmware interface to access EFI variables on certain
devices, and new features for multiple platform and firmware
drivers.
- Arm FF-A firmware support gains support for v1.1 specification
features, in particular notification and memory transaction
descriptor changes.
- SCMI firmware support now support v3.2 features for clock and DVFS
configuration and a new transport for Qualcomm platforms.
- Minor cleanups and bugfixes are added to pretty much all the active
platforms: qualcomm, broadcom, dove, ti-k3, rockchip, sifive,
amlogic, atmel, tegra, aspeed, vexpress, mediatek, samsung and
more.
In particular, this contains portions of the treewide conversion to
use __counted_by annotations and the device_get_match_data helper"
* tag 'soc-drivers-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (156 commits)
soc: qcom: pmic_glink_altmode: Print return value on error
firmware: qcom: scm: remove unneeded 'extern' specifiers
firmware: qcom: scm: add a missing forward declaration for struct device
firmware: qcom: move Qualcomm code into its own directory
soc: samsung: exynos-chipid: Convert to platform remove callback returning void
soc: qcom: apr: Add __counted_by for struct apr_rx_buf and use struct_size()
soc: qcom: pmic_glink: fix connector type to be DisplayPort
soc: ti: k3-socinfo: Avoid overriding return value
soc: ti: k3-socinfo: Fix typo in bitfield documentation
soc: ti: knav_qmss_queue: Use device_get_match_data()
firmware: ti_sci: Use device_get_match_data()
firmware: qcom: qseecom: add missing include guards
soc/pxa: ssp: Convert to platform remove callback returning void
soc/mediatek: mtk-mmsys: Convert to platform remove callback returning void
soc/mediatek: mtk-devapc: Convert to platform remove callback returning void
soc/loongson: loongson2_guts: Convert to platform remove callback returning void
soc/litex: litex_soc_ctrl: Convert to platform remove callback returning void
soc/ixp4xx: ixp4xx-qmgr: Convert to platform remove callback returning void
soc/ixp4xx: ixp4xx-npe: Convert to platform remove callback returning void
soc/hisilicon: kunpeng_hccs: Convert to platform remove callback returning void
...
clk framework changes for the merge window. The core framework changes
are only improving the debugfs interface to allow phase adjustments and
report which consumers of a clk there are. These are most likely only of
interest to kernel developers.
On the clk driver side, it's a ghastly amount of updates with only a
handful of new clk drivers. We have a couple new clk drivers for
Qualcomm, per usual, and a driver for Renesas, Amlogic, and TI
respectively. The updates are spread throughout the clk drivers. Some
highlights are fixing kunit tests for different configurations like
lockdep and big-endian, avoiding integer overflow in rate settable clks,
moving clk_hw_onecell_data to the end of allocations so that drivers
don't corrupt their private data, and migrating clk drivers to the
regmap maple tree. Otherwise it's the usual fixes to clk drivers that
only come along with testing the drivers on real hardware.
New Drivers:
- Add clock driver for TWL6032
- Initial support for the Qualcomm SM4450 Global Clock Controller and
SM4450 RPMh clock controllers
- Add Camera Clock Controller on Qualcomm SM8550
- Add support for the Renesas RZ/G3S (R9A08G045) SoC
- Add Amlogic s4 main clock controller support
Updates:
- Make clk kunit tests work with lockdep
- Fix clk gate kunit test for big-endian
- Convert more than a handful of clk drivers to use regmap maple tree
- Consider the CLK_FRAC_DIVIDER_ZERO_BASED in fractional divider clk
implementation
- Add consumer info to clk debugfs
- Fix various clk drivers that have clk_hw_onecell_data not at the end
of an allocation
- Drop CLK_SET_RATE_PARENT for clocks with fixed-rate GPLLs across a
variety of Qualcomm IPQ platforms
- Add missing parent of APCS PLL on Qualcomm IPQ6018
- Add I2C QUP6 clk on Qualcomm IPQ6018 but mark it critical to avoid
problems with RPM
- Implement safe source switching for a53pll and use on Qualcomm
IPQ5332
- Add support for Stromer Plus PLLs to Qualcomm clk driver
- Switch Qualcomm SM8550 Video and GPU clock controllers to use OLE PLL
configure method
- Non critical fixes to halt bit checks in Qualcomm clk drivers
- Add SMMU GDSC for Qualcomm MSM8998
- Fix possible integer overflow in Qualcomm RCG frequency calculation
code
- Remove RPM managed clks from Qualcomm MSM8996 GCC driver
- Add HFPLL configuration for the three HFPLLs in Qualcomm MSM8976
- Switch Qualcomm MSM8996 CBF clock driver's remove function to return
void
- Fix missing dependency for s4 clock controllers
- Select MXC_CLK when building in the CLK_IMX8QXP
- Fixes for error handling paths in i.MX8 ACM driver
- Move the clocks check in i.MX8 ACM driver in order to log any error
- Drop the unused return value of clk_imx_acm_detach_pm_domains
- Drop non-existant IMX8MP_CLK_AUDIOMIX_PDM_ROOT clock
- Fix error handling in i.MX8MQ clock driver
- Allow a different LCDIF1 clock parent if DT describes it for i.MX6SX
- Keep the SCU resource table sorted in the i.MX8DXL rsrc driver
- Move the elcdif PLL clock registration above lcd_clk, as it is its
parent
- Correct some ENET specific clocks for i.MX8DXL platform
- Drop the VPU_UART and VPUCORE from i.MX8QM as latest HW revision
doesn't have them
- Remove "de-featured" MLB support from i.MX8QM/QXP/DXL platforms
- Skip registering clocks owned by Cortex-A partition SCU-based
platforms
- Add CAN_1/2 to i.MX8QM and M4_0, PI_0_PWM_0 and PI_0_I2C_0 to
i.MX8QXP resources
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmVBac4RHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSUFvg//RG8n63D7wCnCX8AONmbvUzkuF5F3plX7
1oNbHShAWV1ifu5OSaNW06MHw9UP0YD8HogfniWtVC+AmtC0WxS297+TeIlAwobV
fs8XpHpTHiQlHbc4Me1p8Q2QkZRRLoZh1+QLK+J1tiVfh3IBOQ64CyQC/bC0S40B
S470uPcB3duR1fv2IN4EgEojh9b1re2Z1KtqPYQQ+dmB9FifaCL0aF4QPGeG89IK
LYub+OnPdtrOsSxuJSTyck+PLBM2Tr1ikgyEPyo5m/YoJIOI8V/IpB0aIgfbtJL/
xAha95iY2kRLjS2hNWwXLDHXr3g7MG9cuIPUm7qApmrQutmlpf1nXg2GkCeHaLd+
DYtk9qwGObmtBTLzNfezamjaFSQngB0xbhP3dqcvqwmZ7j2voFRKLRUKD5+xWnOl
67yneGSsPRjDJNdgAtONfr/8KU6aRgHJxSILmj+VjfEbYY8BHq1hFgSnHB54l/vq
1RtJxep64vejbhteg2lZFCWLQLHiTETBy+pALhfLG1GKhI7J5A8/vHT/oKXUFZm2
5eUanyMpZJPRzGUZEb1uCarMDjBun/8qPq2tAO9q20di/OEDWWB6egdTzPOkU+Tm
Uz3Z8FxCmqDYsSIaNd6Akahxae0pBMbygxlYdA939zOGaKUGdcaX66395jKjFkJ1
v4XYpsQNBhk=
=ZxE7
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk driver updates from Stephen Boyd:
"Herein lies a smallish collection of clk driver updates and some core
clk framework changes for the merge window. The core framework changes
are only improving the debugfs interface to allow phase adjustments
and report which consumers of a clk there are. These are most likely
only of interest to kernel developers.
On the clk driver side, it's a ghastly amount of updates with only a
handful of new clk drivers. We have a couple new clk drivers for
Qualcomm, per usual, and a driver for Renesas, Amlogic, and TI
respectively. The updates are spread throughout the clk drivers.
Some highlights are fixing kunit tests for different configurations
like lockdep and big-endian, avoiding integer overflow in rate
settable clks, moving clk_hw_onecell_data to the end of allocations so
that drivers don't corrupt their private data, and migrating clk
drivers to the regmap maple tree. Otherwise it's the usual fixes to
clk drivers that only come along with testing the drivers on real
hardware.
New Drivers:
- Add clock driver for TWL6032
- Initial support for the Qualcomm SM4450 Global Clock Controller and
SM4450 RPMh clock controllers
- Add Camera Clock Controller on Qualcomm SM8550
- Add support for the Renesas RZ/G3S (R9A08G045) SoC
- Add Amlogic s4 main clock controller support
Updates:
- Make clk kunit tests work with lockdep
- Fix clk gate kunit test for big-endian
- Convert more than a handful of clk drivers to use regmap maple tree
- Consider the CLK_FRAC_DIVIDER_ZERO_BASED in fractional divider clk
implementation
- Add consumer info to clk debugfs
- Fix various clk drivers that have clk_hw_onecell_data not at the
end of an allocation
- Drop CLK_SET_RATE_PARENT for clocks with fixed-rate GPLLs across a
variety of Qualcomm IPQ platforms
- Add missing parent of APCS PLL on Qualcomm IPQ6018
- Add I2C QUP6 clk on Qualcomm IPQ6018 but mark it critical to avoid
problems with RPM
- Implement safe source switching for a53pll and use on Qualcomm
IPQ5332
- Add support for Stromer Plus PLLs to Qualcomm clk driver
- Switch Qualcomm SM8550 Video and GPU clock controllers to use OLE
PLL configure method
- Non critical fixes to halt bit checks in Qualcomm clk drivers
- Add SMMU GDSC for Qualcomm MSM8998
- Fix possible integer overflow in Qualcomm RCG frequency calculation
code
- Remove RPM managed clks from Qualcomm MSM8996 GCC driver
- Add HFPLL configuration for the three HFPLLs in Qualcomm MSM8976
- Switch Qualcomm MSM8996 CBF clock driver's remove function to
return void
- Fix missing dependency for s4 clock controllers
- Select MXC_CLK when building in the CLK_IMX8QXP
- Fixes for error handling paths in i.MX8 ACM driver
- Move the clocks check in i.MX8 ACM driver in order to log any error
- Drop the unused return value of clk_imx_acm_detach_pm_domains
- Drop non-existant IMX8MP_CLK_AUDIOMIX_PDM_ROOT clock
- Fix error handling in i.MX8MQ clock driver
- Allow a different LCDIF1 clock parent if DT describes it for
i.MX6SX
- Keep the SCU resource table sorted in the i.MX8DXL rsrc driver
- Move the elcdif PLL clock registration above lcd_clk, as it is its
parent
- Correct some ENET specific clocks for i.MX8DXL platform
- Drop the VPU_UART and VPUCORE from i.MX8QM as latest HW revision
doesn't have them
- Remove "de-featured" MLB support from i.MX8QM/QXP/DXL platforms
- Skip registering clocks owned by Cortex-A partition SCU-based
platforms
- Add CAN_1/2 to i.MX8QM and M4_0, PI_0_PWM_0 and PI_0_I2C_0 to
i.MX8QXP resources"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (128 commits)
clk: Fix clk gate kunit test on big-endian CPUs
clk: si521xx: Increase stack based print buffer size in probe
clk: mediatek: fix double free in mtk_clk_register_pllfh()
clk: socfpga: agilex: Add bounds-checking coverage for struct stratix10_clock_data
clk: socfpga: Fix undefined behavior bug in struct stratix10_clock_data
clk: sifive: Allow building the driver as a module
clk: analogbits: Allow building the library as a module
clk: sprd: Composite driver support offset config
clk: Allow phase adjustment from debugfs
clk: Show active consumers of clocks in debugfs
clk: Use device_get_match_data()
clk: visconti: Add bounds-checking coverage for struct visconti_pll_provider
clk: visconti: Fix undefined behavior bug in struct visconti_pll_provider
clk: cdce925: Extend match support for OF tables
clk: si570: Simplify probe
clk: si5351: Simplify probe
clk: rs9: Use i2c_get_match_data() instead of device_get_match_data()
clk: clk-si544: Simplify probe() and is_valid_frequency()
clk: si521xx: Use i2c_get_match_data() instead of device_get_match_data()
clk: meson: S4: select CONFIG_COMMON_CLK_MESON_CLKC_UTILS
...
- Make clk kunit tests work with lockdep
- Fix clk gate kunit test for big-endian
- Convert more than a handful of clk drivers to use regmap maple tree
- Consider the CLK_FRAC_DIVIDER_ZERO_BASED in fractional divider clk
implementation
* clk-renesas: (23 commits)
clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2
clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()
clk: renesas: Add minimal boot support for RZ/G3S SoC
clk: renesas: rzg2l: Add divider clock for RZ/G3S
clk: renesas: rzg2l: Refactor SD mux driver
clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header
clk: renesas: rzg2l: Add struct clk_hw_data
clk: renesas: rzg2l: Add support for RZ/G3S PLL
clk: renesas: rzg2l: Remove critical area
clk: renesas: rzg2l: Fix computation formula
clk: renesas: rzg2l: Trust value returned by hardware
clk: renesas: rzg2l: Lock around writes to mux register
clk: renesas: rzg2l: Wait for status bit of SD mux before continuing
clk: renesas: rcar-gen3: Extend SDnH divider table
dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoC
clk: renesas: r8a7795: Constify r8a7795_*_clks
clk: renesas: r9a06g032: Name anonymous structs
clk: renesas: r9a06g032: Fix kerneldoc warning
clk: renesas: rzg2l: Use u32 for flag and mux_flags
clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields
...
* clk-kunit:
clk: Fix clk gate kunit test on big-endian CPUs
clk: Parameterize clk_leaf_mux_set_rate_parent
clk: Drive clk_leaf_mux_set_rate_parent test from clk_ops
* clk-regmap:
clk: versaclock7: Convert to use maple tree register cache
clk: versaclock5: Convert to use maple tree register cache
clk: versaclock3: Convert to use maple tree register cache
clk: versaclock3: Remove redundant _is_writeable()
clk: si570: Convert to use maple tree register cache
clk: si544: Convert to use maple tree register cache
clk: si5351: Convert to use maple tree register cache
clk: si5341: Convert to use maple tree register cache
clk: si514: Convert to use maple tree register cache
clk: cdce925: Convert to use maple tree register cache
* clk-frac-divider:
clk: fractional-divider: tests: Add test suite for edge cases
clk: fractional-divider: Improve approximation when zero based and export
- Add consumer info to clk debugfs
- Fix various clk drivers that have clk_hw_onecell_data not at the end
of an allocation
* clk-debugfs:
clk: Allow phase adjustment from debugfs
clk: Show active consumers of clocks in debugfs
* clk-spreadtrum:
clk: sprd: Composite driver support offset config
* clk-sifive:
clk: sifive: Allow building the driver as a module
clk: analogbits: Allow building the library as a module
* clk-counted:
clk: socfpga: agilex: Add bounds-checking coverage for struct stratix10_clock_data
clk: socfpga: Fix undefined behavior bug in struct stratix10_clock_data
clk: visconti: Add bounds-checking coverage for struct visconti_pll_provider
clk: visconti: Fix undefined behavior bug in struct visconti_pll_provider
* clk-qcom: (36 commits)
clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider
clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks
clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks
clk: qcom: gcc-ipq6018: add QUP6 I2C clock
clk: qcom: apss-ipq6018: ipq5332: add safe source switch for a53pll
clk: qcom: apss-ipq-pll: Fix 'l' value for ipq5332_pll_config
clk: qcom: apss-ipq-pll: Use stromer plus ops for stromer plus pll
clk: qcom: clk-alpha-pll: introduce stromer plus ops
clk: qcom: config IPQ_APSS_6018 should depend on QCOM_SMEM
clk: qcom: videocc-sm8550: switch to clk_lucid_ole_pll_configure
clk: qcom: gpucc-sm8550: switch to clk_lucid_ole_pll_configure
clk: qcom: Replace of_device.h with explicit includes
clk: qcom: smd-rpm: Move CPUSS_GNoC clock to interconnect
clk: qcom: cbf-msm8996: Convert to platform remove callback returning void
clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_src
clk: qcom: Add GCC driver support for SM4450
dt-bindings: clock: qcom: Add GCC clocks for SM4450
...
- Avoid an oops in possible_parent_show() by checking for no parent
properly when a DT index based lookup is used
- Handle errors returned from divider_ro_round_rate() in
clk_stm32_composite_determine_rate()
- Fix clk_ops::determine_rate() implementation of socfpga's gateclk_ops
that was ruining uart output because the divider was forgotten about
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmU8aqARHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSV9Ew/+LbRC35Dp9liQnF/kpggdfvr1QKDP+bWz
m6Kp9+ZQ6xWcVDV+0Fjbrs/0+QB5R8PS9U/GIQTGcMce0QJwoOnK2eWf22h1H59i
h6nHAUBuDURAotPOIITKn/1McLkznvW+6XUOJ/yBFCsjlqspYlnR222RXOqZrhH1
k/p1LE0dCXeiR07oJSoCsfVA5+ZzoFMRhpijoqjqOwMraMcX34CY3adOdM0WDvvH
j10+9L0Bg5I/Y2NrP5ZfO2zmVVDFRrXuEfB6FlB54o9UDFLydCv6M96S1G4jmFcE
s51mhoVhnxM+DG2Z9DNivPM5e8s1Q3yzvZko045kl86PqNwPw+LiezXwPSGcckKq
5eD6+08yKXgDlHzvCj5/hXO3X/1+HthdxCXXim4/oe+1PYn0tm3gYbyJ/RNMbHRP
x7fYslZXB0rIOV5owO2UfYWqZ3SGpxe+WHdEOnfxyePmx4tVPEccNGDyV4BFBDBE
hUrDrnoJBT6rKFYyvt7V0s5y11tdNOA0/TrzkZuwXNPDWeBLGGpEm0iHcBakrGjP
TWHgFYYdABxwIgcB6aMvzfj1n3vETQKWpCd0nBI73RKz+ZP9ZmVTThSe17yCSjoj
PhozYiv09gZ0ZfJWj6WHj/roJKErkM+Vk+9aC6dM8N3/CyJ5GofXUSf9lrquqBoy
/BFyI4siNO4=
=Hghf
-----END PGP SIGNATURE-----
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"Three fixes, one for the clk framework and two for clk drivers:
- Avoid an oops in possible_parent_show() by checking for no parent
properly when a DT index based lookup is used
- Handle errors returned from divider_ro_round_rate() in
clk_stm32_composite_determine_rate()
- Fix clk_ops::determine_rate() implementation of socfpga's
gateclk_ops that was ruining uart output because the divider
was forgotten about"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: stm32: Fix a signedness issue in clk_stm32_composite_determine_rate()
clk: Sanitize possible_parent_show to Handle Return Value of of_clk_get_parent_name
clk: socfpga: gate: Account for the divider in determine_rate
The clk gate kunit test checks that the implementation of the basic clk
gate reads and writes the proper bits in an MMIO register. The
implementation of the basic clk gate type uses writel() and readl()
which operate on little-endian registers. This test fails on big-endian
CPUs because the clk gate implementation writes to 'fake_reg' with
writel(), which converts the value to be written to little-endian before
storing the value in the fake register. When the test checks the bits in
the fake register on a big-endian machine it falsely assumes the format
of the register is also big-endian, when it is really always
little-endian. Suffice to say things don't work very well.
Mark 'fake_reg' as __le32 and push through endian accessor fixes
wherever the value is inspected to make this test endian agnostic.
There's a CLK_GATE_BIG_ENDIAN flag for big-endian MMIO devices, which
this test isn't using. A follow-up patch will test with and without that
flag.
Reported-by: Boqun Feng <boqun.feng@gmail.com>
Closes: https://lore.kernel.org/r/ZTLH5o0GlFBYsAHq@boqun-archlinux
Tested-by: Boqun Feng <boqun.feng@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20231027225821.95833-1-sboyd@kernel.org
Increase the size of temporary print buffer on stack to fix the
following warnings reported by LKP.
Since all the input parameters of snprintf() are under control
of this driver, it is not possible to trigger and overflow here,
but since the print buffer is on stack and discarded once driver
probe() finishes, it is not an issue to increase it by 10 bytes
and fix the warning in the process. Make it so.
"
drivers/clk/clk-si521xx.c: In function 'si521xx_probe':
>> drivers/clk/clk-si521xx.c:318:26: warning: '%d' directive output may be truncated writing between 1 and 10 bytes into a region of size 2 [-Wformat-truncation=]
snprintf(name, 6, "DIFF%d", i);
^~
drivers/clk/clk-si521xx.c:318:21: note: directive argument in the range [0, 2147483647]
snprintf(name, 6, "DIFF%d", i);
^~~~~~~~
drivers/clk/clk-si521xx.c:318:3: note: 'snprintf' output between 6 and 15 bytes into a destination of size 6
snprintf(name, 6, "DIFF%d", i);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
"
Fixes: edc12763a3 ("clk: si521xx: Clock driver for Skyworks Si521xx I2C PCIe clock generators")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202310260412.AGASjFN4-lkp@intel.com/
Signed-off-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20231027085840.30098-1-marex@denx.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The mtk_clk_register_pll_ops() currently frees the "pll" parameter.
The function has two callers, mtk_clk_register_pll() and
mtk_clk_register_pllfh(). The first one, the _pll() function relies on
the free, but for the second _pllfh() function it causes a double free
bug.
Really the frees should be done in the caller because that's where
the allocation is.
Fixes: d7964de8a8 ("clk: mediatek: Add new clock driver to handle FHCTL hardware")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://lore.kernel.org/r/cd7fa365-28cc-4c34-ac64-6da57c98baa6@moroto.mountain
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
In order to gain the bounds-checking coverage that __counted_by provides
to flexible-array members at run-time via CONFIG_UBSAN_BOUNDS (for array
indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family functions),
we must make sure that the counter member, in this case `num`, is updated
before the first access to the flex-array member, in this case array `hws`.
commit f316cdff8d ("clk: Annotate struct clk_hw_onecell_data with
__counted_by") introduced `__counted_by` for `struct clk_hw_onecell_data`
together with changes to relocate some of assignments of counter `num`
before `hws` is accessed:
include/linux/clk-provider.h:
1380 struct clk_hw_onecell_data {
1381 unsigned int num;
1382 struct clk_hw *hws[] __counted_by(num);
1383 };
However, this structure is used as a member in other structs, in this
case in `struct sstratix10_clock_data`:
drivers/clk/socfpga/stratix10-clk.h:
9 struct stratix10_clock_data {
10 void __iomem *base;
11
12 /* Must be last */
13 struct clk_hw_onecell_data clk_data;
14 };
Hence, we need to move the assignments to `clk_data->clk_data.num` after
allocations for `struct stratix10_clock_data` and before accessing the
flexible array `clk_data->clk_data.hws`. And, as assignments for both
`clk_data->clk_data.num` and `clk_data->base` are originally adjacent to
each other, relocate both assignments together.
Reviewed-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Link: https://lore.kernel.org/r/385c516c498e07eb9a521107e16a7efd26e86ea5.1698117815.git.gustavoars@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
`struct clk_hw_onecell_data` is a flexible structure, which means that
it contains flexible-array member at the bottom, in this case array
`hws`:
include/linux/clk-provider.h:
1380 struct clk_hw_onecell_data {
1381 unsigned int num;
1382 struct clk_hw *hws[] __counted_by(num);
1383 };
This could potentially lead to an overwrite of the objects following
`clk_data` in `struct stratix10_clock_data`, in this case
`void __iomem *base;` at run-time:
drivers/clk/socfpga/stratix10-clk.h:
9 struct stratix10_clock_data {
10 struct clk_hw_onecell_data clk_data;
11 void __iomem *base;
12 };
There are currently three different places where memory is allocated for
`struct stratix10_clock_data`, including the flex-array `hws` in
`struct clk_hw_onecell_data`:
drivers/clk/socfpga/clk-agilex.c:
469 clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
470 num_clks), GFP_KERNEL);
drivers/clk/socfpga/clk-agilex.c:
509 clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
510 num_clks), GFP_KERNEL);
drivers/clk/socfpga/clk-s10.c:
400 clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
401 num_clks), GFP_KERNEL);
I'll use just one of them to describe the issue. See below.
Notice that a total of 440 bytes are allocated for flexible-array member
`hws` at line 469:
include/dt-bindings/clock/agilex-clock.h:
70 #define AGILEX_NUM_CLKS 55
drivers/clk/socfpga/clk-agilex.c:
459 struct stratix10_clock_data *clk_data;
460 void __iomem *base;
...
466
467 num_clks = AGILEX_NUM_CLKS;
468
469 clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
470 num_clks), GFP_KERNEL);
`struct_size(clk_data, clk_data.hws, num_clks)` above translates to
sizeof(struct stratix10_clock_data) + sizeof(struct clk_hw *) * 55 ==
16 + 8 * 55 == 16 + 440
^^^
|
allocated bytes for flex-array `hws`
474 for (i = 0; i < num_clks; i++)
475 clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
476
477 clk_data->base = base;
and then some data is written into both `hws` and `base` objects.
Fix this by placing the declaration of object `clk_data` at the end of
`struct stratix10_clock_data`. Also, add a comment to make it clear
that this object must always be last in the structure.
-Wflex-array-member-not-at-end is coming in GCC-14, and we are getting
ready to enable it globally.
Fixes: ba7e258425 ("clk: socfpga: Convert to s10/agilex/n5x to use clk_hw")
Cc: stable@vger.kernel.org
Reviewed-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Link: https://lore.kernel.org/r/1da736106d8e0806aeafa6e471a13ced490eae22.1698117815.git.gustavoars@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This library is only used by the SiFive PRCI driver. When that driver is
built as a module, it makes sense to build this library as a module too.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Link: https://lore.kernel.org/r/20230725004248.381868-1-samuel.holland@sifive.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The composite interface support the offset configuration,
which is used to support mux and div in different registers.
Because some sprd projects, the divider has different
addresses from mux for one composite clk.
Signed-off-by: Zhifeng Tang <zhifeng.tang@unisoc.com>
Reviewed-by: Chunyan Zhang <zhang.lyra@gmail.com>
Link: https://lore.kernel.org/r/20230913115211.11512-1-zhifeng.tang@unisoc.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
For testing it may be useful to manually adjust a clock's phase. Add
support for writing to the existing clk_phase debugfs file, with the
written value clamped to [0, 360) to match the behaviour of the
clk_set_phase() function.
This is a dangerous feature, so use the existing define
CLOCK_ALLOW_WRITE_DEBUGFS to allow it only if the source is modified.
Signed-off-by: John Keeping <john@metanate.com>
Link: https://lore.kernel.org/r/20230420103805.125246-1-john@metanate.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Use preferred device_get_match_data() instead of of_match_device() to
get the driver match data. With this, adjust the includes to explicitly
include the correct headers.
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20231006213959.334439-1-robh@kernel.org
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #msm part
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # Samsung
Acked-by: David Lechner <david@lechnology.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
In order to gain the bounds-checking coverage that __counted_by provides
to flexible-array members at run-time via CONFIG_UBSAN_BOUNDS (for array
indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family functions),
we must make sure that the counter member, in this particular case `num`,
is updated before the first access to the flex-array member, in this
particular case array `hws`. See below:
commit f316cdff8d ("clk: Annotate struct clk_hw_onecell_data with
__counted_by") introduced `__counted_by` for `struct clk_hw_onecell_data`
together with changes to relocate some of assignments of counter `num`
before `hws` is accessed:
include/linux/clk-provider.h:
1380 struct clk_hw_onecell_data {
1381 unsigned int num;
1382 struct clk_hw *hws[] __counted_by(num);
1383 };
However, this structure is used as a member in other structs, in this
case in `struct visconti_pll_provider`:
drivers/clk/visconti/pll.h:
16 struct visconti_pll_provider {
17 void __iomem *reg_base;
18 struct device_node *node;
19
20 /* Must be last */
21 struct clk_hw_onecell_data clk_data;
22 };
Hence, we need to move the assignments to `ctx->clk_data.num` after
allocation for `struct visconti_pll_provider` and before accessing the
flexible array `ctx->clk_data.hws`. And, as assignments for all members
in `struct visconti_pll_provider` are originally adjacent to each other,
relocate all assignments together, so we don't split up
`ctx->clk_data.hws = nr_plls` from the rest. :)
Reviewed-by: Kees Cook <keescook@chromium.org>
Acked-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Link: https://lore.kernel.org/r/e3189f3e40e8723b6d794fb2260e2e9ab6b960bd.1697492890.git.gustavoars@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
`struct clk_hw_onecell_data` is a flexible structure, which means that
it contains flexible-array member at the bottom, in this case array
`hws`:
include/linux/clk-provider.h:
1380 struct clk_hw_onecell_data {
1381 unsigned int num;
1382 struct clk_hw *hws[] __counted_by(num);
1383 };
This could potentially lead to an overwrite of the objects following
`clk_data` in `struct visconti_pll_provider`, in this case
`struct device_node *node;`, at run-time:
drivers/clk/visconti/pll.h:
16 struct visconti_pll_provider {
17 void __iomem *reg_base;
18 struct clk_hw_onecell_data clk_data;
19 struct device_node *node;
20 };
Notice that a total of 56 bytes are allocated for flexible-array `hws`
at line 328. See below:
include/dt-bindings/clock/toshiba,tmpv770x.h:
14 #define TMPV770X_NR_PLL 7
drivers/clk/visconti/pll-tmpv770x.c:
69 ctx = visconti_init_pll(np, reg_base, TMPV770X_NR_PLL);
drivers/clk/visconti/pll.c:
321 struct visconti_pll_provider * __init visconti_init_pll(struct device_node *np,
322 void __iomem *base,
323 unsigned long nr_plls)
324 {
325 struct visconti_pll_provider *ctx;
...
328 ctx = kzalloc(struct_size(ctx, clk_data.hws, nr_plls), GFP_KERNEL);
`struct_size(ctx, clk_data.hws, nr_plls)` above translates to
sizeof(struct visconti_pll_provider) + sizeof(struct clk_hw *) * 7 ==
24 + 8 * 7 == 24 + 56
^^^^
|
allocated bytes for flex array `hws`
$ pahole -C visconti_pll_provider drivers/clk/visconti/pll.o
struct visconti_pll_provider {
void * reg_base; /* 0 8 */
struct clk_hw_onecell_data clk_data; /* 8 8 */
struct device_node * node; /* 16 8 */
/* size: 24, cachelines: 1, members: 3 */
/* last cacheline: 24 bytes */
};
And then, after the allocation, some data is written into all members
of `struct visconti_pll_provider`:
332 for (i = 0; i < nr_plls; ++i)
333 ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
334
335 ctx->node = np;
336 ctx->reg_base = base;
337 ctx->clk_data.num = nr_plls;
Fix all these by placing the declaration of object `clk_data` at the
end of `struct visconti_pll_provider`. Also, add a comment to make it
clear that this object must always be last in the structure, and
prevent this bug from being introduced again in the future.
-Wflex-array-member-not-at-end is coming in GCC-14, and we are getting
ready to enable it globally.
Fixes: b4cbe606dc ("clk: visconti: Add support common clock driver and reset driver")
Cc: stable@vger.kernel.org
Reviewed-by: Kees Cook <keescook@chromium.org>
Acked-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Link: https://lore.kernel.org/r/57a831d94ee2b3889b11525d4ad500356f89576f.1697492890.git.gustavoars@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The driver has an OF match table, still, it uses an ID lookup table for
retrieving match data. Currently, the driver is working on the
assumption that an I2C device registered via OF will always match a
legacy I2C device ID. The correct approach is to have an OF device ID
table using i2c_get_match_data() if the devices are registered via OF/ID.
Unify the OF/ID table by using struct clk_cdce925_chip_info
as match data for both these tables and replace the ID lookup table for
the match data by i2c_get_match_data().
Split the array clk_cdce925_chip_info_tbl[] as individual variables, and
make lines shorter by referring to e.g. &clk_cdce913_info instead of
&clk_cdce925_chip_info_tbl[CDCE913].
Drop enum related to chip type as there is no user.
While at it, remove the trailing comma in the terminator entry for the OF
table making code robust against (theoretical) misrebases or other similar
things where the new entry goes _after_ the termination without the
compiler noticing.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20230909150516.10353-1-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The driver has an OF match table, still, it uses an ID lookup table for
retrieving match data. Currently, the driver is working on the
assumption that an I2C device registered via OF will always match a
legacy I2C device ID. The correct approach is to have an OF device ID
table using i2c_get_match_data() if the devices are registered via OF/ID.
Unify the OF/ID table by adding struct clk_si570_info as match data
instead of clk_si570_variant and replace the ID lookup table for
the match data by i2c_get_match_data(). This allows to simplify
probe().
Drop enum clk_si570_variant as there is no user.
While at it, remove the trailing comma in the terminator entry for the OF
table making code robust against (theoretical) misrebases or other similar
things where the new entry goes _after_ the termination without the
compiler noticing.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20230909164738.47708-1-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The driver has an OF match table, still, it uses an ID lookup table for
retrieving match data. Currently, the driver is working on the
assumption that an I2C device registered via OF will always match a
legacy I2C device ID. The correct approach is to have an OF device ID
table using i2c_get_match_data() if the devices are registered via OF/ID.
Simplify probe() by replacing ID lookup table for retrieving match data
with i2c_get_match_data().
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20230909162047.41845-1-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The device_get_match_data(), is to get match data for firmware interfaces
such as just OF/ACPI. This driver has I2C matching table as well. Use
i2c_get_match_data() to get match data for I2C, ACPI and DT-based
matching.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20230909160218.33078-1-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The driver has an OF match table, still, it uses an ID lookup table for
retrieving match data. Currently, the driver is working on the
assumption that an I2C device registered via OF will always match a
legacy I2C device ID. The correct approach is to have an OF device ID
table using i2c_get_match_data() if the devices are registered via OF/ID.
Unify the OF/ID table by using max_freq as match data instead of
enum si544_speed_grade and replace the ID lookup table for
the match data by i2c_get_match_data(). This allows to simplify both
probe() and is_valid_frequency().
Drop enum si544_speed_grade as there is no user.
While at it, remove the trailing comma in the terminator entry for the OF
table making code robust against (theoretical) misrebases or other similar
things where the new entry goes _after_ the termination without the
compiler noticing.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20230909155418.24426-1-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The device_get_match_data(), is to get match data for firmware interfaces
such as just OF/ACPI. This driver has I2C matching table as well. Use
i2c_get_match_data() to get match data for I2C, ACPI and DT-based
matching.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20230909152847.16216-1-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Without this, the newly added drivers fail to link:
aarch64-linux-ld: drivers/clk/meson/s4-pll.o: in function `meson_s4_pll_probe':
s4-pll.c:(.text+0x13c): undefined reference to `meson_clk_hw_get'
aarch64-linux-ld: drivers/clk/meson/s4-peripherals.o: in function `meson_s4_periphs_probe':
s4-peripherals.c:(.text+0xb0): undefined reference to `meson_clk_hw_get'
Fixes: e787c9c55e ("clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver")
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20231023102810.4001943-1-arnd@kernel.org
[jbrunet: use 12 char for the Fixes as recommended ]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
While the kernel is booting up, APSS PLL will be running at 800MHz with
GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
configured and select the rate based on the opp table and the source will
be changed to APSS_PLL_EARLY.
Without this patch, CPU Freq driver reports that CPU is running at 24MHz
instead of the 800MHz.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-7-c8ceb1a37680@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
GPLL clock rates are fixed and shouldn't be scaled based on the
request from dependent clocks. Doing so will result in the unexpected
behaviour. So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks.
Fixes: 3d89d52970 ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC")
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-5-c8ceb1a37680@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
GPLL clock rates are fixed and shouldn't be scaled based on the request
from dependent clocks. Doing so will result in the unexpected behaviour.
So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks.
----
Changes in V2:
- No changes
Fixes: d75b82cff4 ("clk: qcom: Add Global Clock Controller driver for IPQ9574")
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-4-c8ceb1a37680@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
GPLL clock rates are fixed and shouldn't be scaled based on the
request from dependent clocks. Doing so will result in the unexpected
behaviour. So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks.
----
Changes in V2:
- New patch
Fixes: e3fdbef1ba ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018")
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-3-c8ceb1a37680@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
GPLL, NSS crypto PLL clock rates are fixed and shouldn't be scaled based
on the request from dependent clocks. Doing so will result in the
unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the PLL
clocks.
Cc: stable@vger.kernel.org
Fixes: d9db07f088 ("clk: qcom: Add ipq6018 Global Clock Controller support")
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-2-c8ceb1a37680@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
GPLL, NSS crypto PLL clock rates are fixed and shouldn't be scaled based
on the request from dependent clocks. Doing so will result in the
unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the PLL
clocks.
Cc: stable@vger.kernel.org
Fixes: b8e7e51962 ("clk: qcom: ipq8074: add remaining PLL’s")
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-1-c8ceb1a37680@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
QUP6 I2C clock is listed in the dt bindings but it was never included in
the GCC driver.
So lets add support for it, it is marked as criticial as it is used by RPM
to communicate to the external PMIC over I2C so this clock must not be
disabled.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231021115545.229060-1-robimarko@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Stromer Plus PLL found on IPQ53xx doesn't support dynamic
frequency scaling. To achieve the same, we need to park the APPS
PLL source to GPLL0, re configure the PLL and then switch the
source to APSS_PLL_EARLY.
To support this, register a clock notifier to get the PRE_RATE
and POST_RATE notification. Change the APSS PLL source to GPLL0
when PRE_RATE notification is received, then configure the PLL
and then change back the source to APSS_PLL_EARLY.
Additionally, not all SKUs of IPQ53xx support scaling. Hence,
do the above to the SKUs that support scaling.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/49422d258d67d33a2547fbb7f4f6e72d489c2301.1697781921.git.quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The earlier 'l' value of 0x3e is for 1.5GHz. Not all SKUs support
this frequency. Hence set it to 0x2d to get 1.1GHz which is
supported in all SKUs.
The frequency can still increase above this initial configuration
made here when the cpufreq driver picks a different OPP.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Fixes: c7ef7fbb1c ("clk: qcom: apss-ipq-pll: add support for IPQ5332")
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/00e6be6cb9cee56628123a64ade118d0a752018b.1697781921.git.quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The set rate and determine rate operations are different between
Stromer and Stromer Plus PLLs. Since the programming sequence is
different, the PLLs dont get configured properly and random,
inexplicable crash/freeze is seen. Hence, use stromer plus ops
for ipq_pll_stromer_plus.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Fixes: c7ef7fbb1c ("clk: qcom: apss-ipq-pll: add support for IPQ5332")
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/c86ecaa23dc4f39650bcf4a3bd54a617a932e4fd.1697781921.git.quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Stromer plus APSS PLL does not support dynamic frequency scaling.
To switch between frequencies, we have to shut down the PLL,
configure the L and ALPHA values and turn on again. So introduce the
separate set of ops for Stromer Plus PLL.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/2affa6c63ff0c4342230623a7d4eef02ec7c02d4.1697781921.git.quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Instead of manually specifying the RINGOSC_CAL_L and CAL_L values in the
alpha_pll_config.l field, use the proper clk_lucid_ole_pll_configure()
function to configure the PLL.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231016084356.1301854-2-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Instead of manually specifying the RINGOSC_CAL_L and CAL_L values in the
alpha_pll_config.l field, use the proper clk_lucid_ole_pll_configure()
function to configure the PLL.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231016084356.1301854-1-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other and pull in various other headers. In
preparation to fix this, adjust the includes for what is actually needed.
of_device.h isn't needed, but mod_devicetable.h and platform_device.h were
implicitly included by it.
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20231010205710.1585232-1-robh@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new() which already returns void. Eventually after all drivers
are converted, .remove_new() is renamed to .remove().
qcom_msm8996_cbf_icc_remove() returned zero unconditionally. After
changing this function to return void instead, the driver can be
converted trivially to use .remove_new().
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20230911151548.672485-1-u.kleine-koenig@pengutronix.de
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The TWL6032 has some clock outputs which are controlled like
fixed-voltage regulators, in some drivers for these chips
found in the wild, just the regulator api is abused for controlling
them, so simply use something similar to the regulator functions.
Due to a lack of hardware available for testing, leave out the
TWL6030-specific part of those functions.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Link: https://lore.kernel.org/r/20230916100515.1650336-5-andreas@kemnade.info
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the check for the return value of mtk_alloc_clk_data() in order to
avoid NULL pointer dereference.
Fixes: e986211827 ("clk: mediatek: Add MT2701 clock support")
Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn>
Link: https://lore.kernel.org/r/20230901024658.23405-1-jiasheng@iscas.ac.cn
Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the check for the return value of mtk_alloc_clk_data() in order to
avoid NULL pointer dereference.
Fixes: 3b5e748615 ("clk: mediatek: add clock support for MT7629 SoC")
Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn>
Link: https://lore.kernel.org/r/20230912093407.21505-5-jiasheng@iscas.ac.cn
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the check for the return value of mtk_alloc_clk_data() in order to
avoid NULL pointer dereference.
Fixes: 3b5e748615 ("clk: mediatek: add clock support for MT7629 SoC")
Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn>
Link: https://lore.kernel.org/r/20230912093407.21505-4-jiasheng@iscas.ac.cn
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the check for the return value of mtk_alloc_clk_data() in order to
avoid NULL pointer dereference.
Fixes: 96596aa066 ("clk: mediatek: add clk support for MT6797")
Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn>
Link: https://lore.kernel.org/r/20230912093407.21505-3-jiasheng@iscas.ac.cn
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the check for the return value of mtk_alloc_clk_data() in order to
avoid NULL pointer dereference.
Fixes: 710774e048 ("clk: mediatek: Add MT6779 clock support")
Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn>
Link: https://lore.kernel.org/r/20230912093407.21505-2-jiasheng@iscas.ac.cn
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
