Pull crypto fixes from Herbert Xu:
"This fixes a compiler warning introduced by a previous fix, as well as
two crash bugs on ARM"
* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6:
crypto: sha512/arm - fix crash bug in Thumb2 build
crypto: sha256/arm - fix crash bug in Thumb2 build
crypto: ccree - add missing inline qualifier
This is a follow-up to the y2038 syscall patches already merged in the tip
tree. As the final 32-bit RISC-V syscall ABI is still being decided on,
this is the last chance to make a few corrections to leave out interfaces
based on 32-bit time_t along with the old off_t and rlimit types.
The series achieves this in a few steps:
- A couple of bug fixes for minor regressions I introduced
in the original series
- A couple of older patches from Yury Norov that I had never
merged in the past, these fix up the openat/open_by_handle_at and
getrlimit/setrlimit syscalls to disallow the old versions of off_t
and rlimit.
- Hiding the deprecated system calls behind an #ifdef in
include/uapi/asm-generic/unistd.h
- Change arch/riscv to drop all these ABIs.
Originally, the plan was to also leave these out on C-Sky, but that now
has a glibc port that uses the older interfaces, so we need to leave
them in place.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJcdEhGAAoJEGCrR//JCVInQuUQAN+mRFzRXAqhbpb63/vYGJei
nmDqB+SoxzaIKAIGAVIdMGUoFxBrY1oyS4m6/a9lzQ9G4aSkr0PruZnUID+vIo2h
rj+3FBlB/c9nvW+NG8iEtVadlRbTmoRILCWpvgIuLNd6fwvNzP3V4uu6a1QRIMx4
aUCWQfhzv18kW1EAPIroPA1gEL2HKbhDdEuN2V0SKnsKNiWkHQeswWQFAYpLgT36
eZ+L52lh+miEdtBxycxJ5lh3KsWO4dPImh+QHONZgeB9iS8v47K0R6ONKm4NMeQV
5KW55pepUq1uQUdEU9KRrh2krMih2IJbOQoN2lvb2ao5UG6erHbj0N55RQym5gSC
+TrvP3dnqfohh9hWdHDwME+5OTeOM+8SUMRnaZBJKuywzo7W1ceLpf+KZjwlk2s5
AgEX67fKrUbtBfTgVhzlYhJLWcgSD1yt64ed5SF15c5M3JZhkK8cd50dB9pM2/YB
o9VbijkYwb2KyCNUiV3nghgiiqcROvOIO7PK6z3XFFiRm/Gn2CgNZyZa7c4+Vgrr
PM/DmDvCdFqYnqBOlV2ilCLigKGN0JgwzMXnbQU77d71Yg7Bco8e/yqSucSilp2d
lEv44extu9FINWXIqvWEjRqdSq+sNgj21VSp6Zu/GaTgNCQKac2wsAZtnQgnslko
knKwwp525fjqnJEDd1aH
=/iFA
-----END PGP SIGNATURE-----
Merge tag 'y2038-syscall-abi' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/playground into timers/2038
Pull additional syscall ABI cleanup for y2038 from Arnd Bergmann:
This is a follow-up to the y2038 syscall patches already merged in the tip
tree. As the final 32-bit RISC-V syscall ABI is still being decided on,
this is the last chance to make a few corrections to leave out interfaces
based on 32-bit time_t along with the old off_t and rlimit types.
The series achieves this in a few steps:
- A couple of bug fixes for minor regressions I introduced
in the original series
- A couple of older patches from Yury Norov that I had never
merged in the past, these fix up the openat/open_by_handle_at and
getrlimit/setrlimit syscalls to disallow the old versions of off_t
and rlimit.
- Hiding the deprecated system calls behind an #ifdef in
include/uapi/asm-generic/unistd.h
- Change arch/riscv to drop all these ABIs.
Originally, the plan was to also leave these out on C-Sky, but that now
has a glibc port that uses the older interfaces, so we need to leave
them in place.
To access PRBARn, where n is referenced as a binary number:
MRC p15, 0, <Rt>, c6, c8+n[3:1], 4*n[0] ; Read PRBARn into Rt
MCR p15, 0, <Rt>, c6, c8+n[3:1], 4*n[0] ; Write Rt into PRBARn
To access PRLARn, where n is referenced as a binary number:
MRC p15, 0, <Rt>, c6, c8+n[3:1], 4*n[0]+1 ; Read PRLARn into Rt
MCR p15, 0, <Rt>, c6, c8+n[3:1], 4*n[0]+1 ; Write Rt into PRLARn
For PR{B,L}AR4, n is 4, n[0] is 0, n[3:1] is 2, while current encoding
done with n[0] set to 1 which is wrong. Use proper encoding instead.
Fixes: 046835b4aa ("ARM: 8757/1: NOMMU: Support PMSAv8 MPU")
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
arm64 has got relaxation on GIC version check at early boot stage due
to update of the GIC architecture let's align ARM with that.
To help backports (even though the code was correct at the time of writing)
Fixes: e59941b9b3 ("ARM: 8527/1: virt: enable GICv3 system registers")
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
MCPM does a soft reset of the CPUs and uses common cpu_resume() routine to
perform low-level platform initialization. This results in a try to install
HYP stubs for the second time for each CPU and results in false HYP/SVC
mode mismatch detection. The HYP stubs are already installed at the
beginning of the kernel initialization on the boot CPU (head.S) or in the
secondary_startup() for other CPUs. To fix this issue MCPM code should use
a cpu_resume() routine without HYP stubs installation.
This change fixes HYP/SVC mode mismatch on Samsung Exynos5422-based Odroid
XU3/XU4/HC1 boards.
Fixes: 3721924c81 ("ARM: 8081/1: MCPM: provide infrastructure to allow for MCPM loopback")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Use unified assembler syntax (UAL) in inline assembler. Divided
syntax is considered deprecated. This will also allow to build
the kernel using LLVM's integrated assembler.
When compiling non-Thumb2 GCC always emits a ".syntax divided"
at the beginning of the inline assembly which makes the
assembler fail. Since GCC 5 there is the -masm-syntax-unified
GCC option which make GCC assume unified syntax asm and hence
emits ".syntax unified" even in ARM mode. However, the option
is broken since GCC version 6 (see GCC PR88648 [1]). Work
around by adding ".syntax unified" as part of the inline
assembly.
[0] https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html#index-masm-syntax-unified
[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88648
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Use unified assembler syntax (UAL) in assembly files. Divided
syntax is considered deprecated. This will also allow to build
the kernel using LLVM's integrated assembler.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Use unified assembler syntax (UAL) in headers. Divided syntax is
considered deprecated. This will also allow to build the kernel
using LLVM's integrated assembler.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Use unified assembler syntax (UAL) in macros. Divided syntax is
considered deprecated. This will also allow to build the kernel
using LLVM's integrated assembler.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Mostly unwind is done with irqs enabled however SLUB may call it with
irqs disabled while creating a new SLUB cache.
I had system freeze while loading a module which called
kmem_cache_create() on init. That means SLUB's __slab_alloc() disabled
interrupts and then
->new_slab_objects()
->new_slab()
->setup_object()
->setup_object_debug()
->init_tracking()
->set_track()
->save_stack_trace()
->save_stack_trace_tsk()
->walk_stackframe()
->unwind_frame()
->unwind_find_idx()
=>spin_lock_irqsave(&unwind_lock);
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
When running kprobe on -rt kernel, the below bug is caught:
|BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:931
|in_atomic(): 1, irqs_disabled(): 128, pid: 14, name: migration/0
|Preemption disabled at:[<802f2b98>] cpu_stopper_thread+0xc0/0x140
|CPU: 0 PID: 14 Comm: migration/0 Tainted: G O 4.8.3-rt2 #1
|Hardware name: Freescale LS1021A
|[<8025a43c>] (___might_sleep)
|[<80b5b324>] (rt_spin_lock)
|[<80b5c31c>] (__patch_text_real)
|[<80b5c3ac>] (patch_text_stop_machine)
|[<802f2920>] (multi_cpu_stop)
Since patch_text_stop_machine() is called in stop_machine() which
disables IRQ, sleepable lock should be not used in this atomic context,
so replace patch_lock to raw lock.
Signed-off-by: Yang Shi <yang.shi@linaro.org>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
commit 137cd7100e
"ARM: dts: Enable Gemini flash access" contained a bug
by disabling the display controller, while the whole
idea with the patch was to enable flash access AND
the display controller, simultaneously. Fix it up.
Fixes: 137cd7100e ("ARM: dts: Enable Gemini flash access")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Three conflicts, one of which, for marvell10g.c is non-trivial and
requires some follow-up from Heiner or someone else.
The issue is that Heiner converted the marvell10g driver over to
use the generic c45 code as much as possible.
However, in 'net' a bug fix appeared which makes sure that a new
local mask (MDIO_AN_10GBT_CTRL_ADV_NBT_MASK) with value 0x01e0
is cleared.
Signed-off-by: David S. Miller <davem@davemloft.net>
Only a handful of device tree fixes, all simple enough:
NVIDIA Tegra:
- Fix a regression for booting on chromebooks
TI OMAP:
- Two fixes PHY mode on am335x reference boards
Marvell mvebu:
- A regression fix for Armada XP NAND flash controllers
- An incorrect reset signal on the clearfog board
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJccHWeAAoJEGCrR//JCVInLQAQAIKQEEQXxPn1fnXH5oH7n/Yn
aALv0zoRKx5ybgQvp15hkdD/H7AUt01ADopCvgOxh0EkheIOEZdtb/FCaRPzaYhC
TrrZhqI6+w0rcMwUzpaDU+90/rxkh6oeIs95lfTkHaZV0ZdbWqwwvX/JuQcPJOh2
tQXwfNMv4WZetvAFrJHr9L+7/CebgQaOe/Me78wq/bjKEROShaF6j6lQMTeZwX6C
Jp75cI5gCktqg4ZDQ2NEE8O9Tng4uzIpoVlCptFc38XGKnRZMexZZlZWpMwTeQg1
QmNmyTal6gbY5tDs3AGg3diSPFQ1nwUiMk2pWvGkkRo5hkNP80lNCouu8F99r/Ub
QoPRcKzGyBwLj0MwpHBoO5gI1X4mgfZDpL71SdS81p8q3rpnt/W2HU+CTAgnEpAi
aILCMmRzes3jpNHREUQc5X3dTwfHW8MBW/Bia6XnidqmUw5GoRq+98rCOKFpg2HQ
m68yDZlOq2odATmaa4xASVfTwccm8jIyQwZVWFPLyekZ9kzMcdYmAI7lGGofJAbg
SkRXDHsAQ21pDoUZY3C0lE49kPKoTNrt4bsihG0I3hM09moF6ryqmymgAy82mzsD
e/ZVG2w1E0CS4vKjKq7BEof3PZ6wSdfaYOFzS7v9bXAeBSdRVE/qjzi/aBgAKD8J
KpDRnh2huOMvPTO5bDKC
=nXrB
-----END PGP SIGNATURE-----
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Arnd Bergmann:
"Only a handful of device tree fixes, all simple enough:
NVIDIA Tegra:
- Fix a regression for booting on chromebooks
TI OMAP:
- Two fixes PHY mode on am335x reference boards
Marvell mvebu:
- A regression fix for Armada XP NAND flash controllers
- An incorrect reset signal on the clearfog board"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
ARM: tegra: Restore DT ABI on Tegra124 Chromebooks
ARM: dts: am335x-evm: Fix PHY mode for ethernet
ARM: dts: am335x-evmsk: Fix PHY mode for ethernet
arm64: dts: clearfog-gt-8k: fix SGMII PHY reset signal
ARM: dts: armada-xp: fix Armada XP boards NAND description
With the device tree changes configuring CPSW with a proper PHY driver,
we want to deprecate the old driver to avoid new users for it.
Note that this driver is based on the related dts changes.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlxwEQ8RHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXOt8Q/7BPvd7UTQy/BK41M1A4NXLX4ojxx+DhEs
vMmGGgRfhfkaVOlN1IWF+A1TgqgUDXfIiAANspZ18hsxNvMihZPklofKO71LM5dm
FjGk4lfLZT2yiFfN03CfgqHJOrph+T2LZ05FOWi8iYwEEvMYVYiCfUjuv/gN2tPT
uMOP8bpibbehNkJSPRDIhpXAlgR1VDFGZU8SKAsxRY69RrgwTy9Pzy4IUHijmKEY
pTX6oF8XR5aXOELRCOX3gBN4YZCz+KmI+KurQjo/pYmVUyAv7uBQrypbevbDNiRW
Qya0Sco3YhGHvkTZDGnrTAZ+ocaG7PzEIiqTUP0YY+AD9MsTrMI6bTq6rp/BU01w
YucV2C0gJdlU9HRhyS0vXAd/n3slNdU9UCtvN7Ezn0zDfhLFpJL0Wf9u4unPWefm
x9vp069fdJOES+Vh3n14FEwzH54do+N918MatX01hj6zkmy67ilJrXR2j8NItxxn
6VxLI7v9Lit5Q6LqEfFdEQ3Pfbfi03HLpg559lFAngzdGbHtLYKunWX05ngcBVo3
WLz+7K/GzsRI3nE/6xjDmwXB6hF5yUJZlcpWSQwzlRWgsPva3TZv5s2yp1rDDbW9
uolMu8fO62PKai1c2l0AyJRwYM7AmWARWd+JFUmcBLdbPNG9mLDYrkqBwRMujqqG
/3dKR8vG5Rw=
=1Hb4
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.1/cpsw-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/late
One change to deprecate old CPSW Ethernet PHY mode selection driver
With the device tree changes configuring CPSW with a proper PHY driver,
we want to deprecate the old driver to avoid new users for it.
Note that this driver is based on the related dts changes.
* tag 'omap-for-v5.1/cpsw-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
net: ethernet: ti: cpsw: deprecate cpsw-phy-sel driver
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This switches the ARM Integrator to use the new PL11x DRM
driver. We need CMA enabled to get coherent allocations
at all times. The dumb VGA DAC bridge is needed for
the VGA output on the reference designs, and backlight
is needed when using an external display.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- A number of pre-nested code rework
- Direct physical timer assignment on VHE systems
- kvm_call_hyp type safety enforcement
- Set/Way cache sanitisation for 32bit guests
- Build system cleanups
- A bunch of janitorial fixes
-----BEGIN PGP SIGNATURE-----
iQJJBAABCgAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAlxwH3EVHG1hcmMuenlu
Z2llckBhcm0uY29tAAoJECPQ0LrRPXpD9j4P/i1lIUKfg/bxGw46wwoqF1MjOEPD
uDQ6irms65FfqFkUkIPaU1du51UcI9nwncUPeJh+E3g2wp2f5EXsAp7tksARfIWU
YCLLez5AiuYH6Otrs7YxLm8L/Sqqc3DacGWuyOamXmdWM9wZlv7F295Yfo5nX8zk
IhksfBQH4/KvOPxkzbY6yy1StKOreuXQuboecrcfUP0lxwaUcbqxHMuynP7DneCv
EHNo5TUjK975xH4jS/K61Ji9FmTlA/PgGqgn+EOw5KXGnKlphFBaTrzuE7vPLveR
XPV1VeNEuEitH/+qVhZr8k2Du+3kKqQA8Ikxv6SasYAnqyVFTPPPMtUEgZXTLpHa
6D4kIc+5jxgxF6Dyk3PKnjoNHPolCApj/uPCcTiD8dyY4smpJQ3+gxGiJkX68e92
EkJlBj0Hn4xgudHi9UWLP+eZHT+v3L8mvVLP9N9oqapwc0x4g9YqJVbJMyAnT5Pw
pLPSKTx9ApmyAEkdzRHjB89gG5cwjUzmx5BF7gASYSmTS9el9r5Kaaxx8zCmMt1R
gM1TF7rBrgyW5s+bsIBf2rqk+5WAxag+FmeCQwghuNc+uhNfboRgoJzx7qFTpxeX
KFS86QmQPRMWGR0klXgW1+hNOD8ACnqCOPGB+3d41ql3bgQ0otLItvj4RoA44JYG
0Guq7o9EZNUYqDzA
=iEs0
-----END PGP SIGNATURE-----
Merge tag 'kvmarm-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into kvm-next
KVM/arm updates for Linux v5.1
- A number of pre-nested code rework
- Direct physical timer assignment on VHE systems
- kvm_call_hyp type safety enforcement
- Set/Way cache sanitisation for 32bit guests
- Build system cleanups
- A bunch of janitorial fixes
Fix PHY reset signal on clearfog gt 8K (Armada 8040 based)
Fix NAND description on Armada XP boards which was broken since a few
release
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCXG/EtQAKCRALBhiOFHI7
1VPDAJ9DSFQaCmlSRwC/jO1HvchB+y9sxACcDQioH28bCYQt3SYp7K87D1ow8wE=
=b5Ed
-----END PGP SIGNATURE-----
Merge tag 'mvebu-fixes-5.0-2' of git://git.infradead.org/linux-mvebu into arm/fixes
mvebu fixes for 5.0 (part 2)
Fix PHY reset signal on clearfog gt 8K (Armada 8040 based)
Fix NAND description on Armada XP boards which was broken since a few
release
* tag 'mvebu-fixes-5.0-2' of git://git.infradead.org/linux-mvebu:
arm64: dts: clearfog-gt-8k: fix SGMII PHY reset signal
ARM: dts: armada-xp: fix Armada XP boards NAND description
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
We now have a proper PHY driver with drivers/phy/ti/phy-gmii-sel.c to
configure the CPSW PHY. These changes update all CPSW users to use the
new driver that already got merged during v5.0 merge window.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlxtm/MRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXN7MxAAlYPHcWbjBc1tDEDZ68MvkhJHeL1jgacC
CRILC/B6iRXQjo1GiHMPD7TLeAWPkzn6s6ZpwZIy0bosLxBhVTFk2goTvZ4PufiV
my1J5zWd8cMB7IDr8xUzMqQ1QD9LmUGXmbIq1xsne5ChCxsElgg6TonsI6ZronBg
eaa/vfiIHmcwSHW7gXWKND29scVzdWI3WgVVj0mlRC1FJRR9G6D7LWlz+18+RiSj
dm5je/tu0Qq1gGNsHlUeMPhoeF7Kx2nBefSNp1NIkHOhk0sgnkfd7VLlFpFi3P0n
SN3sFL4U9JUOh37mdADek/hQ069jHai6KegaP1oK9uhrKV1n90/b8tjVRdUakaAV
PjebAcPxVwIcGk7VE9tf+Dif6HVD+f4HGlAgQ9BiPNnmOCvZ2YkhhH2Sb7MeAmw3
8k4rYpwd+Bb/IRde05iKGU+MRh/LVviwG3llcFealuFG+oPKu/JsEiLbsuGKgNdL
7KdgakkDiecbqDIDx5haXBNfPJEdMxTvmoyFooWHsK6ldA0RJVxKMJTLXx2jLShX
zoBak9LU6eCZBFCbolMw0rUlVr1jUqx9jqnAYEUNL0rI8FRW3kIB6dQL0gxD8bfh
X0RiC1LfOTgiSI8J1iRqNNF2qXEAadkwpiy4XHuV/N1GC8lpPuBHP6j0mWpddHpV
VhNeRAE1Jcg=
=W5Fk
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.1/dt-cpsw-phy' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt
Device tree changes to make CPSW Ethernet use proper phy driver
We now have a proper PHY driver with drivers/phy/ti/phy-gmii-sel.c to
configure the CPSW PHY. These changes update all CPSW users to use the
new driver that already got merged during v5.0 merge window.
* tag 'omap-for-v5.1/dt-cpsw-phy' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
dt-bindings: net: ti: deprecate cpsw-phy-sel bindings
ARM: dts: am335x: switch to use phy-gmii-sel
ARM: dts: am4372: switch to use phy-gmii-sel
ARM: dts: dm814x: switch to use phy-gmii-sel
ARM: dts: dra7: switch to use phy-gmii-sel
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Recent changes with commit cd28d1d6e5: ("net: phy: at803x: Disable phy
delay for RGMII mode") broke Ethernet on am335x-evmsk, and turns out some
device driver fixes are needed.
Even without the driver fixes, am335x needs to run in rgmii-id mode instead
rgmii-txid mode. Things have been working based on luck as the broken driver
has been configuring rgmii-id mode. Let's fix that as that way things work
as they're supposed to work from hardware wiring point of view.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlxtiWwRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXMczhAArsN8/tziFRZcwD8rFIURAXU5SIsbkUhM
7cFvrJqtpfr0ae3G9fdEc/mox0lu3fnyMoGI5+FvKpFJvrW3zvXWYKVs+LJJyZNS
OAE42kYb5yVeUwnFxX8NPSL2v7xMxj576gnyMtgv1L3u1UPEwkjytNuo4z4u08lK
wlBDu/puH0U9hDef5fXPtmpSRPWhfw/4Bm2hj39KulqUPQ6pUnWgHyBg4mqmWYUa
9PS9nZXUAi0iXhCfh2lhAnSw2brYpW5Z76CI2FRcVHOhJ0aQG2+2ojkYVi7IZz6p
egwfOrPj8Xt98EnGBMe3LKmq5m2WVZNAG/G/tzpZGcZRrdWYHpTn5Ua2vPTMzo1R
1N+T8dM0ykkDZ3mKaAI7ixc/sQDXWGQWshzFkik3nKL6EdXpjtaI9yAtfShGiGKE
0g8JByLQ33QwY5yKh+bRbyPt8BO0pJ9cECapBc/UkdmTZ8LrN4co43wFP37aZRv8
fmPJcqlfRni1YMjY9LgFL23mZHgFYdUv4UUqpfczGs9d6RLZM5WodxFod8BGjS2W
kL0ZmTJOecO4mvpUlUYxnSQBhG4FuW3OA266KClSc9rM5PTZzP54BQhyqpzjc/HL
oWNxTpMwAUx7aXUO1TmWinahpZwNt2Ts/PY/8LqHr/6+Q3db39tV17xsGTp7lFjm
W0H8S4UkUQw=
=6JkK
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.0/fixes-rc7-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes
Two am335x ethernet phy mode fixes for v5.0-rc cycle
Recent changes with commit cd28d1d6e5: ("net: phy: at803x: Disable phy
delay for RGMII mode") broke Ethernet on am335x-evmsk, and turns out some
device driver fixes are needed.
Even without the driver fixes, am335x needs to run in rgmii-id mode instead
rgmii-txid mode. Things have been working based on luck as the broken driver
has been configuring rgmii-id mode. Let's fix that as that way things work
as they're supposed to work from hardware wiring point of view.
* tag 'omap-for-v5.0/fixes-rc7-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am335x-evm: Fix PHY mode for ethernet
ARM: dts: am335x-evmsk: Fix PHY mode for ethernet
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Make the arm ctr-aes-ce algorithm update the IV buffer to contain the
next counter after processing a partial final block, rather than leave
it as the last counter. This makes ctr-aes-ce pass the updated AES-CTR
tests. This change also makes the code match the arm64 version in
arch/arm64/crypto/aes-modes.S more closely.
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The SHA512 code we adopted from the OpenSSL project uses a rather
peculiar way to take the address of the round constant table: it
takes the address of the sha256_block_data_order() routine, and
substracts a constant known quantity to arrive at the base of the
table, which is emitted by the same assembler code right before
the routine's entry point.
However, recent versions of binutils have helpfully changed the
behavior of references emitted via an ADR instruction when running
in Thumb2 mode: it now takes the Thumb execution mode bit into
account, which is bit 0 af the address. This means the produced
table address also has bit 0 set, and so we end up with an address
value pointing 1 byte past the start of the table, which results
in crashes such as
Unable to handle kernel paging request at virtual address bf825000
pgd = 42f44b11
[bf825000] *pgd=80000040206003, *pmd=5f1bd003, *pte=00000000
Internal error: Oops: 207 [#1] PREEMPT SMP THUMB2
Modules linked in: sha256_arm(+) sha1_arm_ce sha1_arm ...
CPU: 7 PID: 396 Comm: cryptomgr_test Not tainted 5.0.0-rc6+ #144
Hardware name: QEMU KVM Virtual Machine, BIOS 0.0.0 02/06/2015
PC is at sha256_block_data_order+0xaaa/0xb30 [sha256_arm]
LR is at __this_module+0x17fd/0xffffe800 [sha256_arm]
pc : [<bf820bca>] lr : [<bf824ffd>] psr: 800b0033
sp : ebc8bbe8 ip : faaabe1c fp : 2fdd3433
r10: 4c5f1692 r9 : e43037df r8 : b04b0a5a
r7 : c369d722 r6 : 39c3693e r5 : 7a013189 r4 : 1580d26b
r3 : 8762a9b0 r2 : eea9c2cd r1 : 3e9ab536 r0 : 1dea4ae7
Flags: Nzcv IRQs on FIQs on Mode SVC_32 ISA Thumb Segment user
Control: 70c5383d Table: 6b8467c0 DAC: dbadc0de
Process cryptomgr_test (pid: 396, stack limit = 0x69e1fe23)
Stack: (0xebc8bbe8 to 0xebc8c000)
...
unwind: Unknown symbol address bf820bca
unwind: Index not found bf820bca
Code: 441a ea80 40f9 440a (f85e) 3b04
---[ end trace e560cce92700ef8a ]---
Given that this affects older kernels as well, in case they are built
with a recent toolchain, apply a minimal backportable fix, which is
to emit another non-code label at the start of the routine, and
reference that instead. (This is similar to the current upstream state
of this file in OpenSSL)
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The SHA256 code we adopted from the OpenSSL project uses a rather
peculiar way to take the address of the round constant table: it
takes the address of the sha256_block_data_order() routine, and
substracts a constant known quantity to arrive at the base of the
table, which is emitted by the same assembler code right before
the routine's entry point.
However, recent versions of binutils have helpfully changed the
behavior of references emitted via an ADR instruction when running
in Thumb2 mode: it now takes the Thumb execution mode bit into
account, which is bit 0 af the address. This means the produced
table address also has bit 0 set, and so we end up with an address
value pointing 1 byte past the start of the table, which results
in crashes such as
Unable to handle kernel paging request at virtual address bf825000
pgd = 42f44b11
[bf825000] *pgd=80000040206003, *pmd=5f1bd003, *pte=00000000
Internal error: Oops: 207 [#1] PREEMPT SMP THUMB2
Modules linked in: sha256_arm(+) sha1_arm_ce sha1_arm ...
CPU: 7 PID: 396 Comm: cryptomgr_test Not tainted 5.0.0-rc6+ #144
Hardware name: QEMU KVM Virtual Machine, BIOS 0.0.0 02/06/2015
PC is at sha256_block_data_order+0xaaa/0xb30 [sha256_arm]
LR is at __this_module+0x17fd/0xffffe800 [sha256_arm]
pc : [<bf820bca>] lr : [<bf824ffd>] psr: 800b0033
sp : ebc8bbe8 ip : faaabe1c fp : 2fdd3433
r10: 4c5f1692 r9 : e43037df r8 : b04b0a5a
r7 : c369d722 r6 : 39c3693e r5 : 7a013189 r4 : 1580d26b
r3 : 8762a9b0 r2 : eea9c2cd r1 : 3e9ab536 r0 : 1dea4ae7
Flags: Nzcv IRQs on FIQs on Mode SVC_32 ISA Thumb Segment user
Control: 70c5383d Table: 6b8467c0 DAC: dbadc0de
Process cryptomgr_test (pid: 396, stack limit = 0x69e1fe23)
Stack: (0xebc8bbe8 to 0xebc8c000)
...
unwind: Unknown symbol address bf820bca
unwind: Index not found bf820bca
Code: 441a ea80 40f9 440a (f85e) 3b04
---[ end trace e560cce92700ef8a ]---
Given that this affects older kernels as well, in case they are built
with a recent toolchain, apply a minimal backportable fix, which is
to emit another non-code label at the start of the routine, and
reference that instead. (This is similar to the current upstream state
of this file in OpenSSL)
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Switch to use phy-gmii-sel PHY instead of cpsw-phy-sel.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Switch to use phy-gmii-sel PHY instead of cpsw-phy-sel.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Switch to use phy-gmii-sel PHY instead of cpsw-phy-sel.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Switch to use phy-gmii-sel PHY instead of cpsw-phy-sel.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
-------------------------------------
This pull request gets rid of mach-davinci private interrupt controller
implmentations (aintc and cp_initc) and moves them to drivers/irqchip.
mach/irqs.h usage outside of mach-davinci has been rid of.
The driver changes (input and irqchip) have been acked by respective
maintainers.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJcbB7FAAoJEGFBu2jqvgRNwUAP/Ri35UejS+fPVHa/zMjPGSwh
AcWQvkKQFqrBbBmuUiQeXR54UE1it8zH0NstcXJ5GDP88bFg+cEL6g2In56Ke+JE
OGEY+7dmzp3/XJK+UtAqTNl3lT1lwss/pVO1OZYn19K3eB/+gdMInTv9x7eJmO1u
c/gE3DKPii/ftpgF3DqR/+68eVXnqMd4b/C/TSQekQVnHKzZSrwMTPmPgVFWiaEq
+3gdYk6v0lVoBExEF/dmwQ5/gGzSlwV0V5pFP70y6/2Mm9pm0NRQUoF7Xg4E2IyI
2OwZbf3qRMtADdUqC0van3M/L3fZaIoVDEK21FFLuyXNa0mHGOjrsyDqzbKlGxTw
rIpNzm069iNnUVMDl0aWJC//DzkcJRNFDiSNlGuxDtuC3N7eVowQAblLGj7Q2nGw
+Uv/7Babe+uQ0E0SyjNjyJuAiT62lo668Q2oNyYvgs/xStsWAg3eqClPP2V99cv/
Lwznz179pSnGWjofdYg4+d6xrw/68Ji1q2dijqMTmG9WSwcuAvaGl5ZzQbSCpCTe
0gp3pE8nbC+FRUL6XcWzxfKCjvfHr3pBsmfJPSlfC39DT/hdRWt7Fi/B6XAZHfE3
N76bCj7In+cp3fRPzudqDUimN3DvSpBTFT9US1hEolEKzDF4DijEE+AA7TqT0IDV
qH+AdYATkAMWkrL0uF8U
=VjX6
-----END PGP SIGNATURE-----
Merge tag 'davinci-for-v5.1/soc-part3' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into arm/late
DaVinci SoC updates for v5.1 (part 3)
-------------------------------------
This pull request gets rid of mach-davinci private interrupt controller
implmentations (aintc and cp_initc) and moves them to drivers/irqchip.
mach/irqs.h usage outside of mach-davinci has been rid of.
The driver changes (input and irqchip) have been acked by respective
maintainers.
* tag 'davinci-for-v5.1/soc-part3' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: (57 commits)
ARM: davinci: remove intc related fields from davinci_soc_info
irqchip: davinci-cp-intc: move the driver to drivers/irqchip
ARM: davinci: cp-intc: remove redundant comments
ARM: davinci: cp-intc: drop GPL license boilerplate
ARM: davinci: cp-intc: use readl/writel_relaxed()
ARM: davinci: cp-intc: unify error handling
ARM: davinci: cp-intc: improve coding style
ARM: davinci: cp-intc: request the memory region before remapping it
ARM: davinci: cp-intc: use the new-style config structure
ARM: davinci: cp-intc: convert all hex numbers to lowercase
ARM: davinci: cp-intc: use a common prefix for all symbols
ARM: davinci: cp-intc: add the new config structures for da8xx SoCs
irqchip: davinci-cp-intc: add a new config structure
ARM: davinci: cp-intc: add a wrapper around cp_intc_init()
ARM: davinci: cp-intc: remove cp_intc.h
irqchip: davinci-aintc: move the driver to drivers/irqchip
ARM: davinci: aintc: remove unnecessary includes
ARM: davinci: aintc: remove the timer-specific irq_set_handler()
ARM: davinci: aintc: request memory region before remapping it
ARM: davinci: aintc: unify error handling
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
1. Enable ADC on Odroid HC1 board.
2. Fix clkout register failure on Exynos3250.
3. Allow using earlycon on Arndale board.
4. Disable ARM PMU on Odroid XU3 Lite because it is locked by Trusted
Firmware.
5. Add support for secondary DAI to Odroid XU3 and XU4 boards.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAlxsT7EQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD13TbD/0eQCYKTS63O9mUBlclpcpaKHt4WnzOfxDC
ww3JIrjk/lc4bW7rx0s5I70cLxYVMWMZmJYWQsR75QgTwWzECz561KvQAaNCngfh
OAaIsY1h0wwULGhsL4LJP91zlfxrx31YpnvIT3wtKmxATUBLpcbUbH0AHmhwLmaD
wRtdFdN9UeaD7gOAakRcS5OGjli7wEju+eO4QP0VZDfxsuAGvPDmeueHJ3B8PDtM
nLCUdzCqbe0JgY8AUAfNB6JkpDHf4SCzCc0wiwqslYFEWFbLgkeCZR2oTpTeo+St
WLcxTZCK4qC3pzpQV2bLTNhDlpRZon50kQnWV5OVdKihbtRvNuCstC8PIWTZL8ny
TL/f9xwka4wNehhA+mkblNF1geAvESxbKfXnY+grZiEdzjGwHAABVwGUoDkCao0I
SyO85lzdQ0M/I2t562EN/RK8uHhBhIWCoD8mMVteyrDLKXtpEkH2Jw5naznlaFQN
Moq2hY598NHi3oDMz1A9yy6YJSKUP36k8biVkTBBwaXkkrs3sKNJ6lyHiuEvpaTx
fslqaMWRfLv99CRnZvjGzNnZ0rdDB+jHV8a9G7GFX83AEt9a1/wcEdK2VWqn05B2
tGAyf+sayH0JTr+xfmRPn/B185s0ef2+ZuxEWamJxGIpOxMA0Azjntb6ZcVGQz/I
5sa2wTQItQ==
=vbXr
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung DTS ARM changes for v5.1, part 2
1. Enable ADC on Odroid HC1 board.
2. Fix clkout register failure on Exynos3250.
3. Allow using earlycon on Arndale board.
4. Disable ARM PMU on Odroid XU3 Lite because it is locked by Trusted
Firmware.
5. Add support for secondary DAI to Odroid XU3 and XU4 boards.
* tag 'samsung-dt-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: Add support for secondary DAI to Odroid XU4
ARM: dts: exynos: Add support for secondary DAI to Odroid XU3
ARM: dts: exynos: Disable ARM PMU on Odroid XU3-lite
ARM: dts: exynos: Add stdout path property to Arndale board
ARM: dts: exynos: Add minimal clkout parameters to Exynos3250 PMU
ARM: dts: exynos: Enable ADC on Odroid HC1
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Commit 482997699e ("ARM: tegra: Fix unit_address_vs_reg DTC warnings
for /memory") inadventently broke device tree ABI by adding a unit-
address to the "/memory" node because the device tree compiler flagged
the missing unit-address as a warning.
Tegra124 Chromebooks (a.k.a. Nyan) use a bootloader that relies on the
full name of the memory node in device tree being exactly "/memory". It
can be argued whether this was a good decision or not, and some other
bootloaders (such as U-Boot) do accept a unit-address in the name of the
node, but the device tree is an ABI and we can't break existing setups
just because the device tree compiler considers it bad practice to omit
the unit-address nowadays.
This partially reverts the offending commit and restores device tree ABI
compatibility.
Fixes: 482997699e ("ARM: tegra: Fix unit_address_vs_reg DTC warnings for /memory")
Reported-by: Tristan Bastian <tristan-c.bastian@gmx.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tested-by: Tristan Bastian <tristan-c.bastian@gmx.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
All users of dma_declare_coherent want their allocations to be
exclusive, so default to exclusive allocations.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This API is primarily used through DT entries, but two architectures
and two drivers call it directly. So instead of selecting the config
symbol for random architectures pull it in implicitly for the actual
users. Also rename the Kconfig option to describe the feature better.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Paul Burton <paul.burton@mips.com> # MIPS
Acked-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
marvell,dsa properties has been removed from kirkwood-rd88f6281.dtsi
while cleanuping the dsa binding, but the dsa reference in
kirkwood-rd88f6281-z0.dts has been missed causing the following errors:
arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts:21.4-16: Warning (reg_format): /dsa/switch@0:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1)
arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts:23.5-15: Warning (reg_format): /dsa/switch@0/port@4:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
arch/arm/boot/dts/kirkwood-rd88f6281-z0.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
arch/arm/boot/dts/kirkwood-rd88f6281-z0.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
arch/arm/boot/dts/kirkwood-rd88f6281-z0.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts:20.12-26.5: Warning (avoid_default_addr_size): /dsa/switch@0: Relying on default #address-cells value
arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts:20.12-26.5: Warning (avoid_default_addr_size): /dsa/switch@0: Relying on default #size-cells value
arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts:22.11-25.6: Warning (avoid_default_addr_size): /dsa/switch@0/port@4: Relying on default #address-cells value
arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts:22.11-25.6: Warning (avoid_default_addr_size): /dsa/switch@0/port@4: Relying on default #size-cells value
So remove the dsa reference too in order to fix this issue.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Currently, the Kbuild core manipulates header search paths in a crazy
way [1].
To fix this mess, I want all Makefiles to add explicit $(srctree)/ to
the search paths in the srctree. Some Makefiles are already written in
that way, but not all. The goal of this work is to make the notation
consistent, and finally get rid of the gross hacks.
Having whitespaces after -I does not matter since commit 48f6e3cf5b
("kbuild: do not drop -I without parameter").
[1]: https://patchwork.kernel.org/patch/9632347/
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
The header search path -I. in kernel Makefiles is very suspicious;
it allows the compiler to search for headers in the top of $(srctree),
where obviously no header file exists.
I was able to build without these extra header search paths.
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Move this little function to the header files for arm/arm64 so other
code can make use of it directly.
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
VHE systems don't have to emulate the physical timer, we can simply
assign the EL1 physical timer directly to the VM as the host always
uses the EL2 timers.
In order to minimize the amount of cruft, AArch32 gets definitions for
the physical timer too, but is should be generally unused on this
architecture.
Co-written with Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
At the moment we have separate system register emulation handlers for
each timer register. Actually they are quite similar, and we rely on
kvm_arm_timer_[gs]et_reg() for the actual emulation anyways, so let's
just merge all of those handlers into one function, which just marshalls
the arguments and then hands off to a set of common accessors.
This makes extending the emulation to include EL2 timers much easier.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Fixed 32-bit VM breakage and reduced to reworking existing code]
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
[Fixed 32bit host, general cleanup]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
We previously incorrectly named the define for this system register.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
In preparation for nested virtualization where we are going to have more
than a single VMID per VM, let's factor out the VMID data into a
separate VMID data structure and change the VMID allocator to operate on
this new structure instead of using a struct kvm.
This also means that udate_vttbr now becomes update_vmid, and that the
vttbr itself is generated on the fly based on the stage 2 page table
base address and the vmid.
We cache the physical address of the pgd when allocating the pgd to
avoid doing the calculation on every entry to the guest and to avoid
calling into potentially non-hyp-mapped code from hyp/EL2.
If we wanted to merge the VMID allocator with the arm64 ASID allocator
at some point in the future, it should actually become easier to do that
after this patch.
Note that to avoid mapping the kvm_vmid_bits variable into hyp, we
simply forego the masking of the vmid value in kvm_get_vttbr and rely on
update_vmid to always assign a valid vmid value (within the supported
range).
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
[maz: minor cleanups]
Reviewed-by: Julien Thierry <julien.thierry@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
We currently eagerly save/restore MPIDR. It turns out to be
slightly pointless:
- On the host, this value is known as soon as we're scheduled on a
physical CPU
- In the guest, this value cannot change, as it is set by KVM
(and this is a read-only register)
The result of the above is that we can perfectly avoid the eager
saving of MPIDR_EL1, and only keep the restore. We just have
to setup the host contexts appropriately at boot time.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
Just like on arm64, and for the same reasons, kvm_call_hyp removes
any form of type safety when calling into HYP. But we can still
try to tell the compiler what we're trying to achieve.
Here, we can add code that would do the function call if it wasn't
guarded by an always-false predicate. Hopefully, the compiler is
dumb enough to do the type checking and clever enough to not emit
the corresponding code...
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
Until now, we haven't differentiated between HYP calls that
have a return value and those who don't. As we're about to
change this, introduce kvm_call_hyp_ret(), and change all
call sites that actually make use of a return value.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
The PHY must add both tx and rx delay and not only on the tx clock.
The board uses AR8031_AL1A PHY where the rx delay is enabled by default,
the tx dealy is disabled.
The reason why rgmii-txid worked because the rx delay was not disabled by
the driver so essentially we ended up with rgmii-id PHY mode.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The PHY must add both tx and rx delay and not only on the tx clock.
The board uses AR8031_AL1A PHY where the rx delay is enabled by default,
the tx dealy is disabled.
The reason why rgmii-txid worked because the rx delay was not disabled by
the driver so essentially we ended up with rgmii-id PHY mode.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit 3b79919946 ("ARM: dts:
armada-370-xp: update NAND node with new bindings") updated some
Marvell Armada DT description to use the new NAND controller bindings,
but did it incorrectly for a number of boards: armada-xp-gp,
armada-xp-db and armada-xp-lenovo-ix4-300d. Due to this, the NAND is
no longer detected on those platforms.
This commit fixes that by properly using the new NAND DT binding. This
commit was runtime-tested on Armada XP GP, the two other platforms are
only compile-tested.
Fixes: 3b79919946 ("ARM: dts: armada-370-xp: update NAND node with new bindings")
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The fields related to the two davinci interrupt controllers are no
longer used. Remove them.
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The cp-intc driver has now been cleaned up. Move it to drivers/irqchip
where it belongs.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
We don't need comments explaining what functions with obvious names do.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Replace the GPLv2 license boilerplate with an SPDX identifier and add
myself as a second author.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Replace all calls to __raw_readl() & __raw_writel() with readl_relaxed()
and writel_relaxed() respectively. It's safe to do as there's no
endianness conversion being done in the code.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Instead of dumping stack traces, just print a specific error message
in aintc driver.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Drop tabs from variable initialization. Arrange variables in reverse
christmas-tree order. Add a newline before a return.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add a missing call to request_mem_region() before calling ioremap() to
make sure it's not been requested by another user.
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Modify the cp-intc driver to take all its configuration from the new
config structure. Stop referencing davinci_soc_info in any way.
Move the declaration for davinci_cp_intc_init() to
irq-davinci-cp-intc.h and make it take the new config structure as
parameter. Convert all users to the new version.
Also: since the two da8xx SoCs default all irq priorities to 7, just
drop the priority configuration at all and hardcode the channels to 7.
It will simplify the driver code and make our lives easier when it
comes to device-tree support.
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Use lowercase letters in hexadecimal numbers in the cp-intc driver as
is done in most of the kernel code base.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
In preparation for moving the driver to drivers/irqchip do some
cleanup: use a common prefix for all symbols.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add the new-style config structures for da8xx SoCs. They will be used
once we make the cp-intc driver stop using davinci_soc_info.
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
We're going to extend the cp_intc_init() function with a config
structure so we can drop the intc-related fields from davinci_soc_info.
Once we do it, we won't be able to use this routine directly as the
init_irq callback. Wrap the calls in additional helpers that don't
take parameters and can be assigned to init_irq.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
There's no need to have a local header for cp-intc. Move the only
declaration for a public function to common.h. Move all register
offsets into the driver source file and drop all unused defines.
Make cp_intc_of_init() static.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The aintc driver has now been cleaned up. Move it to drivers/irqchip
where it belongs. There's no device-tree support for any dm* board so
there's no IRQCHIP_OF_DECLARE() - there's only the exported init
function called from machine code.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
These includes are no longer required. Remove them.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
I've been unable to figure out exactly why, but the IRQ_TINT1_TINT34
interrupt is being handled as level irq and it's configured in the
irq chip driver instead of set by the irq_set_type() callback.
Since this is probably some legacy hack for out-of-tree code - remove it.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add a missing call to request_mem_region() before calling ioremap() to
make sure the region is not being used by anyone else.
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Instead of dumping stack traces, just print a specific error message
in aintc driver.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Modify the aintc driver to take all its configuration from the new
config structure. Stop referencing davinci_soc_info in any way.
Move the declaration for davinci_aintc_init() to irq-davinci-aintc.h
and make it take the new config structure as parameter. Convert all
users to the new version.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add the new-style config structures for dm* SoCs. They will be used
once we make the aintc driver stop using davinci_soc_info.
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Raplace all calls to __raw_writel() with writel_relaxed().
It's safe to do as there's no endianness conversion being
done in the code.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Since no offset goes past 0xff - let's drop the 00 prefix for better
readability. While we're at it: convert all hex numbers to lower-case.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
In preparation for moving the driver to drivers/irqchip do some
cleanup: use a common prefix for all symbols.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
We're going to extend the davinci_irq_init() function with a config
structure so we can drop the intc-related fields from davinci_soc_info.
Once we do it, we won't be able to use this routine directly as the
init_irq callback. Wrap the calls in additional helpers that don't
take parameters and can be assigned to init_irq.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Replace the GPLv2 or later license boilerplate with an SPDX identifier.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The existence of irqs.h in mach-davinci/include/mach only makes sense
without SPARSE_IRQ as it's then expected to define NR_IRQS and is
included from asm/irq.h. As we now support SPARSE_IRQ, this header can
be moved to mach-davinci and used as the source of HW interrupt numbers.
While updating the includes in various files - also rearrange the
headers by directory (linux/asm/mach).
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Everything is in place now for SPARSE_IRQ. Select it and set
DAVINCI_INTC_START to NR_IRQS.
We now need to include mach/irqs.h in a couple places as it is no
longer indirectly included after selecting SPARSE_IRQ.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Once we select SPARSE_IRQ, the interrupt numbers defined in mach/irqs.h
will only signify the hardware interrupt offsets, not the interrupt
numbers seen by linux. Introduce a wrapper macro that translates the
hwirq number to virtual numbers. For now it's just a dummy. Use that
macro when specifying the interrupts in resources for platform devices.
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
davinci_intc_base is defined globally in common.c. Define separate
local variables for the aintc and cp-intc drivers and remove the
global one.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
We now use the generic ARM irq handler on davinci. There are no more
users that check davinci_intc_type. Remove the variable and all its
references.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
In order to support SPARSE_IRQ we first need to make davinci use the
generic irq handler for ARM. Translate the legacy assembly to C and
put the irq handlers into their respective drivers (aintc and cp-intc).
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
We need to create an irq domain if we want to select SPARSE_IRQ. The
cp-intc driver already supports it, but aintc doesn't. Use the helpers
provided by the generic irq chip abstraction.
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The intc_host_map field in struct davinci_soc_info is not used by any
board. Remove it as part of the interrupt support cleanup.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Pull cpufreq drivers material for v5.1 from Viresh Kumar:
"This contains:
- Minor cleanups for pcc, longhaul, powerenv and speedstep drivers (Yangtao Li).
- Moving configuration data out of mach directory for davinci (Bartosz Golaszewski)."
* 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm:
cpufreq: davinci: move configuration to include/linux/platform_data
cpufreq: speedstep: convert BUG() to BUG_ON()
cpufreq: powernv: fix missing check of return value in init_powernv_pstates()
cpufreq: longhaul: remove unneeded semicolon
cpufreq: pcc-cpufreq: remove unneeded semicolon
All new 32-bit architectures should have 64-bit userspace off_t type, but
existing architectures has 32-bit ones.
To enforce the rule, new config option is added to arch/Kconfig that defaults
ARCH_32BIT_OFF_T to be disabled for new 32-bit architectures. All existing
32-bit architectures enable it explicitly.
New option affects force_o_largefile() behaviour. Namely, if userspace
off_t is 64-bits long, we have no reason to reject user to open big files.
Note that even if architectures has only 64-bit off_t in the kernel
(arc, c6x, h8300, hexagon, nios2, openrisc, and unicore32),
a libc may use 32-bit off_t, and therefore want to limit the file size
to 4GB unless specified differently in the open flags.
Signed-off-by: Yury Norov <ynorov@caviumnetworks.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Yury Norov <ynorov@marvell.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch extends DAPM routing and adds secondary CPU DAI entry
to support the secondary audio PCM interface on Odroid XU4.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This patch extends DAPM routing and adds secondary CPU DAI entry
to support the secondary audio PCM interface on Odroid XU3.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
ARM Performance Monitoring Units (PMUs) are permanently disabled in the
Exynos5422 SoC version used on Odroid XU3-lite boards. Disable them in
boards dtb to avoid confusing user and getting following warning on boot:
hw-breakpoint: Failed to enable monitor mode on CPU 0
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
- Dietmar Eggemann noticed an issue with IRQ migration during CPU hotplug
stress testing.
- Mathieu Desnoyers noticed that a previous fix broke optimised kprobes.
- Robin Murphy noticed a case where we were not clearing the dma_ops.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIVAwUAXGVW//TnkBvkraxkAQK8wg/8D8TzU4nuO7r/0n6YXS6quJz15VRmK6uu
c+geOFmQ5VOWYJZDJ94IWEjXd/W1X6JpN94zL+xefJ5Ct38YBjhyYqq41HGoxAtV
YjwXZAY6kkjMR8HBW+Xkhn0WcefE+QjMNPjUQUtpfLTvQpiaBC94zCeiw6ttxBv5
fkSlYUq1OGf8i75bBHBg7Nj2UFMn2so/1dYOr3OejVAq+b/r82D4bm0ykXiHFzrH
RDT+VKcSjsxFCFBPqN/76Lf4rUTZqgIsl3h/LRBdvOGo3M/7t26ByJZ4p9nYgsDh
VfeitZCxUHRIBoBjqPA+uAhb5G/Ya4Qf+fyauuQuMMRxpnjACCxG5OekG/+UMZEK
4/8mhO8u33bphqHB+b6e6LRPke+EHC+quj3CLYgxyY6PKzSBk1tUSiGhxIbmR0Yw
a4VtY31832BN5BSyCJvfYdl/+brs+Nujhjbzd66+3EvU0zgPISuXXBwfWkqmwshU
S+Yj/BVo/wCwnGsqY6UFqtdEBL9J+Oe1J6I3Y6hzPd27egv7IIFWCGkL+gWPxWtd
YbbgdfU3dL7fTw5j6Es6mdFkz+uWwWSfTs1ImB4EAYQzNgkJrfxJrbA6v1PfzLDP
5sFMB3W8fwPfT7Qq11QpjEywn1+fi/JFrWLsW2xUAFVd79HPIbsEf8eZQF5OA0Qw
4jDzQqOr9Sc=
=KSCg
-----END PGP SIGNATURE-----
Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm
Pull ARM fixes from Russell King:
"A few ARM fixes:
- Dietmar Eggemann noticed an issue with IRQ migration during CPU
hotplug stress testing.
- Mathieu Desnoyers noticed that a previous fix broke optimised
kprobes.
- Robin Murphy noticed a case where we were not clearing the dma_ops"
* tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm:
ARM: 8835/1: dma-mapping: Clear DMA ops on teardown
ARM: 8834/1: Fix: kprobes: optimized kprobes illegal instruction
ARM: 8824/1: fix a migrating irq bug when hotplug cpu
Replace bootargs and kernel console parameter with 'stdout-path' property
in 'chosen' node to instruct kernel which serial driver should be used
for the kernel console and logs. This allows to enable earlycon messages
by adding just 'earlycon' parameter to kernel command line.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Add minimal parameters needed by the Exynos CLKOUT driver to Exynos3250
PMU node. This fixes the following warning on boot:
exynos_clkout_init: failed to register clkout clock
Fixes: d19bb397e1 ("ARM: dts: exynos: Update PMU node with CLKOUT related data")
Cc: <stable@vger.kernel.org>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Odroid HC1 uses the exynos5422-odroid-core.dtsi file as a base. All
other Exynos5422 Odroids use the "common". The ADC node was defined
only in the latter.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
from the Edison tablet and a chosen node for veyron devices.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlxp5qUQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgXsjCACcvu8DsAywvD4A1Ifnj1LCwIfzzTk7Njle
NMtg4xGJDgjuTWYZMWUeIf7/te/sRX5w1T9a+yURxU7q7+aFhquKSIfhncqpKzeI
0glWTsOuIVaQSjn4+R5as6KPOxgWrBLZOolu39HmDnmaAjDn6hb5/NTm+lxSSrQO
R/IJuMSbHL++vPNsP7415hYuZf+5uwFkbOeE7b3nU4zhPFa5IO7WNQlzytf3o4+M
4YqZ+C3eA9/M0izFN2UOvkqKIgHp6ZGGzE1fpcbrM74OqyreZh9CuuBnGbOmSD4N
medTwJEVnuKJRFSmAyXuEUP8+M+RAQOrPZOop/HtvHdRhhfHvrCE
=HTA/
-----END PGP SIGNATURE-----
Merge tag 'v5.1-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
A number of improvements for rv1108 boards, removal of an obsolete property
from the Edison tablet and a chosen node for veyron devices.
* tag 'v5.1-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: add chosen node on veyron devices
ARM: dts: rockchip: remove cap-mmc-highspeed from rk3188-bqedison2qc mmc1 node
ARM: dts: rockchip: Use the correct regulator properties on rv1108-evb
ARM: dts: rockchip: Use the correct regulator properties on rv1108-elgin
ARM: dts: rockchip: Fix vcc5/6-supply representation on rv1108-elgin
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The header containing the configuration structure for davinci cpufreq
driver lives in mach-davinci/include/mach/. This is fine for now but
if we want to make davinci part of the multi_v5 build, no code external
to mach-davinci should include machine-specific headers.
Move the configuration structure to include/linux/platform_data.
While we're at it: convert the GPL-2.0 boilerplate to a proper SPDX
license identifier.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
- support for a new variant of pca953x
- documentation fix from Wolfram
- some tegra186 name changes
- two minor fixes for madera and altera-a10sr
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEFp3rbAvDxGAT0sefEacuoBRx13IFAlxleLcACgkQEacuoBRx
13I45Q//YMGUYzkMjOL+lp2DYnnVhVNqrF4hoLjinWVrnhZ6gqu88RgV2Cea4Pta
oxVxnSsE8LK7kY8VZ8tcBmIqLLkQAJdSVtqkeSoZF2vhWBAbE9ZaSOYb17SIkSXK
Ok16lZgZ+ZWOM5EjEvuRpB/qYGjX2glD5/Y2Kl7+wsX1W6U2pXasP0IjhcvDU8mJ
NXNgfkr6kluMUqHJyqKo8eT/P3Hdv0CK9GsN2vGyfJenCdTSd7EC6KuhWAivi+fG
/lf1bVuc2cCiXjxdSOXx+Yz7SjNe56viTaqnn/K6OlfLgErjKnRW+AxPkTZXNtDi
pfMMpPXiwPcbQR2wrXG/7OMmJ1kUsfWoIUCx5RDwhF1KbEQVqgaSITLylk+4Yp/3
eM0fYsQ+KvOdAnWKSgfxBhaaiO7z5XDdrnkSHBDoiBrm07BqBgK/v3Rivzf2GMEv
QvM4OBfThS9I8skV5BaOBRDfHZs4N0EU/vhsW9gt50urtlSM0vSYx6kdMq/8R0k4
NkJT43u+1vi5koMljBAsZYZiyXOQ2B+PlfpTMfMu+93QH8wlu9mOt1r3YTQyA1Xf
jiOK8M2yQKP5g7RuPM6MtMsqlZKDM5nAlSf7S280Z3+vBd+LaELbXvT2/JL5ViGU
hfH/gaNwUGUYd8EsWvfhHVdPAAecDCwxfKyKEnFGhMrtunTgwfI=
=nV64
-----END PGP SIGNATURE-----
Merge tag 'gpio-v5.1-updates-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel
gpio updates for v5.1
- support for a new variant of pca953x
- documentation fix from Wolfram
- some tegra186 name changes
- two minor fixes for madera and altera-a10sr
of x86 bug fixes.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQEcBAABAgAGBQJcaQI4AAoJEL/70l94x66DOPwH/0d7JDl2Qr3+1B20hv2++35C
RyG8bMayJq0AATRcjuaFXKiKikZ3NyMHHxaLRwhtcZggU+2FlykEwIKIHvv3L9bj
Rs/YNtIRI21qDSFtOmKnAYnSm10QkngJw7sd5ExHnMTiuCoca3f8EjKnatFgMlzv
UMdMTe9UaMGAl9IKveW56xneR1MDYFG8x69Uu9Si7LkIdMgEAstuJGcTQAt9TzO/
AvbckcN9MKfVCjwvnzsTMaKQMttSHHpOh50gaLlAzPubqfVaqTkSmCvN22+UAk/H
t248x3bHOCO1u1HdHC/sxf8z6HIOFD692eBRmrm5LjBsUFdktUPj7q0U8r9MEK4=
=oHHm
-----END PGP SIGNATURE-----
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM fixes from Paolo Bonzini:
"A somewhat bigger ARM update, and the usual smattering of x86 bug
fixes"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
kvm: vmx: Fix entry number check for add_atomic_switch_msr()
KVM: x86: Recompute PID.ON when clearing PID.SN
KVM: nVMX: Restore a preemption timer consistency check
x86/kvm/nVMX: read from MSR_IA32_VMX_PROCBASED_CTLS2 only when it is available
KVM: arm64: Forbid kprobing of the VHE world-switch code
KVM: arm64: Relax the restriction on using stage2 PUD huge mapping
arm: KVM: Add missing kvm_stage2_has_pmd() helper
KVM: arm/arm64: vgic: Always initialize the group of private IRQs
arm/arm64: KVM: Don't panic on failure to properly reset system registers
arm/arm64: KVM: Allow a VCPU to fully reset itself
KVM: arm/arm64: Reset the VCPU without preemption and vcpu state loaded
arm64: KVM: Don't generate UNDEF when LORegion feature is present
KVM: arm/arm64: vgic: Make vgic_cpu->ap_list_lock a raw_spinlock
KVM: arm/arm64: vgic: Make vgic_dist->lpi_list_lock a raw_spinlock
KVM: arm/arm64: vgic: Make vgic_irq->irq_lock a raw_spinlock
In order to use earlycon, the stdout-path property needs to be set
in the chosen node. All veyron devices use uart2 for debugging, so
add it to the core veyron dtsi.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The mmc1 pins are used for SDIO with a wifi chip.
The function mmc_sdio_switch_hs() only checks for MMC_CAP_SD_HIGHSPEED and
not for MMC_CAP_MMC_HIGHSPEED, so cap-mmc-highspeed can be removed.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The netfilter conflicts were rather simple overlapping
changes.
However, the cls_tcindex.c stuff was a bit more complex.
On the 'net' side, Cong is fixing several races and memory
leaks. Whilst on the 'net-next' side we have Vlad adding
the rtnl-ness support.
What I've decided to do, in order to resolve this, is revert the
conversion over to using a workqueue that Cong did, bringing us back
to pure RCU. I did it this way because I believe that either Cong's
races don't apply with have Vlad did things, or Cong will have to
implement the race fix slightly differently.
Signed-off-by: David S. Miller <davem@davemloft.net>
A fix from Russell that took a while to get applied into fixes as
I thought Russell is merging this one.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlxdqikRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXNnUhAAiroTD0SiwEj5CJU4YmECuBrk9vLonbM8
8AF4RLtXb2hRIWV/uUEyRMctaHcPlMD2JFp96pie/cJng/6Ba8KlW1u780QZokOt
iMTQ7CgWooqkFRF5xcOYsoY/MTivTUnZTR7jpWIIOtMKBul6xureqvwx7spBsERu
PICl7oTep109jPB2gF4omcw4oS2iuSTo2M+q068Ut62OhBHdUowu3pE8z7bBPmbq
9vGYs+vTPvwC7r61hIYr+ROdjjvegA01caC1r+pG6bm0t0L56/hpjO2x1uZaYcVF
n63K56Jd1/eeZJ+9qupwekMPWd5JnQhVspNu8Jb3XcgAhGZE62eC4gTCj8yRMCC+
ThDZ2GIjHqL8lzz2EWLeXq0Xy0HLbNOPkNTZoK2Gej2lRy67gvAH1lQy+T3kKzQU
39dzC6kyMOhNM3i/rnBBqEHL4KyWvwZV2vsZtMbF2Kz5pJ1Sbttr0LrqrO/+ANJo
VUQAo9rscjU0OExX9DUtu/M6WHH5UrpglEZVn29MBmQU5R7qJ+dZH9ADmchWn3Rb
G42JUZMCja0BWsmlHJ5KCiUU6AHDecxNPVe13IT36WnGoU/Z1tSuSbhkZz3Inltu
9d+fqeZ2Um4difa3QEq1j/2n+mMrQZfvAO1govNHxsDkEKvYOs52WNCR1kpRT+3w
2RZtP9QxzT0=
=0LSw
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.0/fixes-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes
Fix omap4 and later lost cpu1 interrupts for periodic timer
A fix from Russell that took a while to get applied into fixes as
I thought Russell is merging this one.
* tag 'omap-for-v5.0/fixes-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: fix lack of timer interrupts on CPU1 after hotplug
ARM: lpc32xx: platform updates for v5.1
Here are the changes for ARM NXP LPC32xx platform files:
* removed a superfluous record to kernel log buffer under OOM condition,
* use kmemdup() helper instead of kmalloc()/memcpy() pair,
* removed platform data of ARM PL180 SD/MMC and ARM PL111 LCD controllers,
since now both are handled in devicetree files.
* tag 'lpc32xx-soc-for-5.1' of https://github.com/vzapolskiy/linux-lpc32xx:
ARM: lpc32xx: remove platform data of ARM PL111 LCD controller
ARM: lpc32xx: remove platform data of ARM PL180 SD/MMC controller
ARM: lpc32xx: Use kmemdup to replace duplicating its implementation
ARM: lpc32xx: Delete an error message for a failed memory allocation in lpc32xx_pm_enter()
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
ARM: tegra: Core changes for v5.1-rc1
This contains three fixes for resume from LP1 on Tegra30.
* tag 'tegra-for-5.1-arm-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Restore memory arbitration on resume from LP1 on Tegra30+
ARM: tegra: Fix DRAM refresh-interval clobbering on resume from LP1 on Tegra30
ARM: tegra: Fix missed EMC registers latching on resume from LP1 on Tegra30+
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Samsung mach/soc changes for v5.1
Two fixes: one for handling timeout while booting secondary CPU of
Exynos and second for S3C24xx DVS notifier.
* tag 'samsung-soc-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: exynos: Fix timeout when booting secondary CPUs
ARM: s3c24xx: Fix boolean expressions in osiris_dvs_notify
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
DaVinci SoC updates for v5.1 (part 2)
This pull request contains changes needed to help get rid of
hard-coded GPIO base value passed from DaVinci platform data.
The OHCI related changes also help by moving over-current support
from board-files to OHCI driver making future DT-coversion easy.
The OHCI parts are acked by its maintainer.
* tag 'davinci-for-v5.1/soc-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
usb: ohci-da8xx: remove unused callbacks from platform data
ARM: davinci: da830-evm: remove legacy usb helpers
ARM: davinci: omapl138-hawk: remove legacy usb helpers
usb: ohci-da8xx: add vbus and overcurrent gpios
ARM: davinci: da830-evm: use gpio lookup entries for usb gpios
ARM: davinci: omapl138-hawk: use gpio lookup entries for usb gpios
usb: ohci-da8xx: add a helper pointer to &pdev->dev
usb: ohci-da8xx: add a new line after local variables
ARM: davinci: da850-evm: use GPIO hogs instead of the legacy API
ARM: davinci: mityomapl138: use device properties for at24 eeprom
ARM: davinci: mityomapl138: use nvmem notifiers
ARM: davinci: remove dead code related to MAC address reading
ARM: davinci: sffsdr: use device properties for at24 eeprom
ARM: davinci: sffsdr: fix the at24 eeprom device name
ARM: davinci: dm646x-evm: use device properties for at24 eeprom
ARM: davinci: dm644x-evm: use device properties for at24 eeprom
ARM: davinci: da830-evm: use device properties for at24 eeprom
ARM: davinci: dm365-evm: use device properties for at24 eeprom
ARM: davinci: mityomapl138: don't read the MAC address from machine code
ARM: davinci: da850-evm: remove dead MTD code
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
i.MX SoC changes for 5.1:
- Support cpuidle for i.MX7ULP, states WFI, WAIT and STOP get added.
- Support SoC revision detecting for i.MX7ULP by reading JTAG_ID
register from SIM module.
- Select PM and GPCv2 irqchip driver options for i.MX8 support, as they
are essential for building an i.MX8 based system.
- Skip build of ssi-fiq code if SND_SOC_IMX_PCM_FIQ is not enabled.
* tag 'imx-soc-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: imx8mq: select PM support
arm64: imx8mq: select GPCv2 irqchip driver
ARM: imx: add i.MX7ULP SoC revision support
ARM: imx: add i.MX7ULP cpuidle support
ARM: imx: don't build ssi-fiq if not required
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This is the pxa changes for 5.1 cycle:
- the last step of raumfeld board conversion to devicetree is here,
ie. the platform_data file removal
The previous cycle dealt with devicetree inclusion already.
- an empty file removal
* tag 'pxa-for-5.1' of https://github.com/rjarzmik/linux:
ARM: pxa: remove unused empty mach/pxa25x-udc.h file
ARM: pxa: remove raumfeld board files and defconfig
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
for 5.1, please pull the following:
- Stefan updates the BCM2835 SoC driver with downstream properties and
uses that to implement a reboot notifier to tell the VC4 firmware when
Linux on the ARM CPU is rebooting
- Eric adds a proper power domain driver for the BCM283x SoCs and
updates a bunch of drivers to have a better and clearer Device Tree
definition to support power domains/breaking up of functionality. This
requires converting the existing watchdog driver into a MFD and then
breaking up the functionality into separate drivers and finally
updating the DTS files to leverage the power domains information.
- Wei provides a fix for making a symbol static
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAlxV0IYACgkQh9CWnEQH
BwQIHA//TL12EfHws6C64EKspqsg9NE5/+K3HRRJbgwtuBQ/n6oYBMyJx+6x6Nwc
7QjuCkZ/VWKxy0Fn+ToGnX0JgrQL5kND3Cm0d8cyZ0VJ6juppizyAa1YkFplShSr
l0XlYaJo1HrB3hBd/+YbGZnLp9flbii5d3MIcy8ZoWmN7zLeHnQbHaf8jcbJC+Iw
Mal8ojk2ru0rMimMQieTiPzWwiec08wtSIYs2590rOVWFyhGIn/KmHqpG6iYjdwj
oQbr86R0jMPCb/g3SXRttxW8wFbtYdmILdkzhOaEd4JyJEwUCNDciM3E04OyE9VN
fNMc1l0zh7dfyo9bFRpgS6AAxYQVj3led+B1NGtpnjDPybVWU10gipGdgFt9UPRE
pJnS1LcPbAJ1FdbcYFU0TsiViWLZehm2cbc4rPYvqKp1Y+82FJZTYyu0GmBOUwB6
jpM5ZVvET8k3nw6ImeE3jjT3kBfF31u552+iO4RQvKHRm/GBMtyTDrFZVUwgqMFE
NEKnj3/VLSCxP3dnQImw1ro2493piZNdlBEs6mAugFUGqcb+40KOtOOpWiGMFH7h
BZN0kj128ryG/YCVKDOnZSbYRLhpxc1VcVYJ3rYJgn8mrFFmNo/fjDgaRogrJN/s
LmCiSIqsmuy8f36/IWd+aHk6ex5yskJe7x5M/7tlmz03oXg1viQ=
=t5+u
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.1/drivers' of https://github.com/Broadcom/stblinux into arm/drivers
This pull request contains Broadcom ARM/ARM64/MIPS based SoCs changes
for 5.1, please pull the following:
- Stefan updates the BCM2835 SoC driver with downstream properties and
uses that to implement a reboot notifier to tell the VC4 firmware when
Linux on the ARM CPU is rebooting
- Eric adds a proper power domain driver for the BCM283x SoCs and
updates a bunch of drivers to have a better and clearer Device Tree
definition to support power domains/breaking up of functionality. This
requires converting the existing watchdog driver into a MFD and then
breaking up the functionality into separate drivers and finally
updating the DTS files to leverage the power domains information.
- Wei provides a fix for making a symbol static
* tag 'arm-soc/for-5.1/drivers' of https://github.com/Broadcom/stblinux:
ARM: bcm283x: Switch V3D over to using the PM driver instead of firmware.
ARM: bcm283x: Extend the WDT DT node out to cover the whole PM block. (v4)
soc: bcm: bcm2835-pm: Make local symbol static
soc: bcm: Make PM driver default for BCM2835
soc: bcm: bcm2835-pm: Add support for power domains under a new binding.
bcm2835-pm: Move bcm2835-watchdog's DT probe to an MFD.
dt-bindings: soc: Add a new binding for the BCM2835 PM node. (v4)
firmware: raspberrypi: notify VC4 firmware of a reboot
soc: bcm2835: sync firmware properties with downstream
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This adds the include/linux/reset directory to MAINTAINERS for reset
specific headers and adds headers for sunxi and socfpga in there to
get rid of a few extern function declarations.
There is a new reset driver for the Broadcom STB reset controller and
the i.MX7 system reset controller driver is extended to support i.MX8MQ
as well. Finally, there is a new header with reset id constants for
the Meson G12A SoC, which has a reset controller identical to Meson AXG
and thus can reuse its driver and DT bindings.
-----BEGIN PGP SIGNATURE-----
iI0EABYIADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCXF2yeRcccC56YWJlbEBw
ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwH8jAP9OQaMl5llVXuHSFOwiqkJ2I09p
oROxu3dI/A4q7d5T8QD/Xuo4piSAdoT5YZyHp16NUafW3L1//wqTvxk0ubeTsgA=
=EIyo
-----END PGP SIGNATURE-----
Merge tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux into arm/drivers
Reset controller changes for v5.1
This adds the include/linux/reset directory to MAINTAINERS for reset
specific headers and adds headers for sunxi and socfpga in there to
get rid of a few extern function declarations.
There is a new reset driver for the Broadcom STB reset controller and
the i.MX7 system reset controller driver is extended to support i.MX8MQ
as well. Finally, there is a new header with reset id constants for
the Meson G12A SoC, which has a reset controller identical to Meson AXG
and thus can reuse its driver and DT bindings.
* tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux:
dt-bindings: reset: meson: add g12a bindings
reset: imx7: Add support for i.MX8MQ IP block variant
reset: imx7: Add plubming to support multiple IP variants
reset: Add Broadcom STB SW_INIT reset controller driver
dt-bindings: reset: Add document for Broadcom STB reset controller
reset: socfpga: declare socfpga_reset_init in a header file
reset: sunxi: declare sun6i_reset_init in a header file
MAINTAINERS: use include/linux/reset for reset controller related headers
dt-bindings: reset: imx7: Document usage on i.MX8MQ SoCs
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable more drivers in s5pv210 defconfig for Aries family of mobile
devices (e.g. Samsung Galaxy S).
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAlxUl8gQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD18OtD/9i7gE27i3Rb5DZXDIf7JY0gnpYR0WGE+Bw
boWRS8N/hADRAGWPVzy6Hu9fJZjkaOAYZbnHwtcznB+NeQQd3gWyQUpjCHOwFtKN
cQsT3680E9qI3VmoBEpVgzGGrOlLOxodRZkE3rNlL5pcFK3SPZkq43noSN1IwYLf
bHRP155awQ9VXtWQLwuOqb6rhLz38Mhm5TfzibY6D8pFS+UJBFWiMdX45W5jfRBv
xImKnWFQQo3HVyiayWJOQUein2BXfxCJhDpqUh7NL4C7NhbqodCjuPUszopxWK71
dnZGpupjLY0muTGWrgDZEwkUwYB33hqUoNtWrjj3KEI7SlVBkDw5mN6WO/POSoE5
MfcWdL8Io9voOlzWNzoNXUQOU7ep4fUZS7aRfXpnZWnING6aoNAnCXLs6wiEmoCX
elMra2aaN7M2I73wS3eIKiWtr5lbBnBnivCjeMMxdIeRviz8TLVk11OEl97w1soP
DGKBvLcjOi7q3pejCSDVEj07NIMUZSHm1z88SKpVOfaykBbOdRbkY8KNschr5dUJ
F9UdpuhZTSBFLWhctjU37Wb1eMJfZtewG1bfmbY+XLgP3297Q+zHFrmcpa9QL1eR
PmLeURK8ahJpSFjrukHjn7KyaM10Bl0OT3nSPfhZYh6sowRAeroCU2uvpnp3/Ziu
NrXUhxNWsw==
=78iS
-----END PGP SIGNATURE-----
Merge tag 'samsung-defconfig-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/defconfig
Samsung defconfig changes for v5.1
Enable more drivers in s5pv210 defconfig for Aries family of mobile
devices (e.g. Samsung Galaxy S).
* tag 'samsung-defconfig-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: s5pv210_defconfig: Enable cpufreq
ARM: s5pv210_defconfig: Enable more drivers present on Samsung Aries
ARM: s5pv210_defconfig: Run make savedefconfig
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
updates for 5.1, please pull the following:
- Stefan enables the MMAL-based V4L2 camera driver for the Raspberry Pi
devices
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAlxVzrwACgkQh9CWnEQH
BwRa3Q/9H9IeE0Q5KwQ37zMiC/s25z8VByAQ9qchJB0kjGXs8vIQAeMwi8x08zvc
gyq+EX7y3Q+U7yEkqOTMFT/rxP/wLnsIX6EBGodcFr4ZZVWpIX9Sm9i8y4+inP+S
doxXyrFspdXZMv3VzZPayzEHZRnaP7cdeNhbMwrEgirQjIR+/zdY/0THjswUp/Vs
nb95mj4hZUOQmK4Es9PqxiNavwZ/yI0CxzAzd9v2s3IKLvb0+D89rlQ46tPwyirL
wSzvReyGl0Am15IICPFKv39wEBwUU2DlBHa8S5LvkDXMa/ydQvdQ6t2Vh1FeIjNJ
WRtev+waQskTeeoxOktJIpZbkEQqJPCxWdvYo1QmDHFVk84e98/YwGhdZcDe/LtB
XBa/GpyCEgWmX0LaRuDRuJNGSnz5qkGG+Fi39m50SAotvWMZFxBMp+2pko8XaxPf
UnDQLry4AVsvm+e8lN+HZkwbFT4tmvFNCvFyV7C28Os1efGP3d16ccerNfi029GX
2lb2CQzQ35QjkIVEAyqs7SpT+RkZxxRWdL5eryhq1/5ZKS8gbOcY/EQ0phKo4/QW
VaD/UnbQJLkc32vADta+wSnu/zuk4SyZkuSivYbJQepcXJGA5VIliLFxyPoMCem2
4AkxblWtzlZIzSEHsbC9iBWyKKP+5VeF2sYd0uo1fj+p2UZBPGg=
=uhZ9
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.1/defconfig' of https://github.com/Broadcom/stblinux into arm/defconfig
This pull request contains Broadcom ARM-based SoCs defconfig file
updates for 5.1, please pull the following:
- Stefan enables the MMAL-based V4L2 camera driver for the Raspberry Pi
devices
* tag 'arm-soc/for-5.1/defconfig' of https://github.com/Broadcom/stblinux:
ARM: bcm2835_defconfig: Enable BCM2835 MMAL-based V4L2 camera driver
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Here are the changes for ARM NXP LPC32xx and ARM NXP LPC18xx/LPC43xx
defconfig files:
* LPC18xx/LPC43xx and LPC32xx defconfig files got updates to match
savedefconfig,
* PL11x LCD controller driver on both LPC18xx/LPC43xx and LPC32xx
has been switched from fbdev to DRM one,
* drivers of GPIO controllers not found on LPC32xx boards are disabled,
* LPC32xx gets enabled additional sane debugging options: panic on oops,
sysrq, dynamic debug, timestamps in kernel log buffer and built GDB
scripts,
* LPC32xx gets enabled NFSv4 support,
* LPC32xx gets enabled a number of used drivers: DRM simple panel,
fixed voltage regulator and generic SRAM drivers,
* Option to have a serial console on HS UART on LPC32xx is enabled.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEETKMJMWSwX7CFTVIOqj3i2jwlOWUFAlxXSwEACgkQqj3i2jwl
OWVKAw//QSv3Bl/CoPHJfYJwgAfslN+nqQg9TXC9ygEIS4t0oeWd/W7MZeLUfRdj
RyRWAmtJ3eoeNsz1lnhSaAd2sgqJOlL36zDq5k+pLnFPXp7jKlpU7wI4xq/T4HuY
auyqywG9VfjIrcNjNcoGMDe+cJNTfbcr+epF45MLQLu+4JxdS2A7IKDibaC/Mq1J
JDHslte/lf3/ShlDC5cNU3EMmV9gdB4NmFixWGTRXxJzE9U63r+7wtwy+dV/e8KN
hCgybm1Lk039Zjd0pfB6S8N8CLeuhtcAAcJSWuFrsUXQbzhOy7b5hx+qfTyBd0bW
RnyajbqD9KTV1YYHFL3sJoK3HnvUO4Vk9/QzJarAFop7xoY/pO07aVnGGVc3UsmH
uHW0527XVXyV9yxymXB4yvLcnwzcUj8kww6kWFiaAJJQl9p9JPB2W5Lnqayqy2Br
A7YqdG34/aeMPPe93CFTQV+MKRiSriYZ2gVpgQi1tD3kNji6Xh+VEb8EUcTPnYc8
z0edolwNNNw/dvyeyoOl6HSTHf6Nykivfxs+WJwKIXFZRbtxlRa0zPJjv1ua8BR/
Per/EhyFpQWM4YioiaVoI+YZk3ZoLOSBdRnuW+PvAEx8ET4jU+fP1PxHlsbv/1fD
w/plHUDWbNTvZ9yn6zTBmkfFGrvHNInbpJuOmfTJ+EE+Pvk/YUE=
=nR4K
-----END PGP SIGNATURE-----
Merge tag 'lpc32xx-defconfig-for-5.1' of https://github.com/vzapolskiy/linux-lpc32xx into arm/defconfig
ARM: lpc32xx: defconfig updates for v5.1
Here are the changes for ARM NXP LPC32xx and ARM NXP LPC18xx/LPC43xx
defconfig files:
* LPC18xx/LPC43xx and LPC32xx defconfig files got updates to match
savedefconfig,
* PL11x LCD controller driver on both LPC18xx/LPC43xx and LPC32xx
has been switched from fbdev to DRM one,
* drivers of GPIO controllers not found on LPC32xx boards are disabled,
* LPC32xx gets enabled additional sane debugging options: panic on oops,
sysrq, dynamic debug, timestamps in kernel log buffer and built GDB
scripts,
* LPC32xx gets enabled NFSv4 support,
* LPC32xx gets enabled a number of used drivers: DRM simple panel,
fixed voltage regulator and generic SRAM drivers,
* Option to have a serial console on HS UART on LPC32xx is enabled.
* tag 'lpc32xx-defconfig-for-5.1' of https://github.com/vzapolskiy/linux-lpc32xx:
ARM: defconfig: lpc32xx: enable DRM simple panel driver
ARM: defconfig: lpc32xx: enable fixed voltage regulator support
ARM: defconfig: lpc32xx: disable superfluous GPIO controllers
ARM: defconfig: lpc32xx: enable generic SRAM driver
ARM: defconfig: lpc32xx: enable serial console on HS UART
ARM: defconfig: lpc32xx: enable panic on oops option
ARM: defconfig: lpc32xx: enable build options for basic debugging
ARM: defconfig: lpc32xx: enable NFSv4 support
ARM: defconfig: Switch LPC32xx to use PL11x DRM driver
ARM: defconfig: Update LPC32xx defconfig
ARM: defconfig: Switch LPC18xx to use PL11x DRM driver
ARM: defconfig: Update LPC18xx defconfig
shmobile and multi_v7 defconfig
* Enable support for recently upstreamed RZ/A2 (r7s9210) SoC
* Enable NXP pcf85363 RTC which is used on RZ/G1C (r8a77470) based iWave SBC
shmobile defconfig
* Refresh for changes present in v5.0-rc1
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAlxdV5wACgkQ189kaWo3
T75X1Q/7BMrKJisvrPEcCcfWFJd3ce6ojtaSa7kVAAgoaOpgylZGtC9inWW/XbPS
aYitIE2aT3rRO1+xOV31SsMW0RFELyQkIvJTzYyVjC5AdeBqIt5fHqJqXq+k0jF9
MbvxHtfxxTpKp0vIvhBnONIqMlj4N4BRHyhMtLaDKoePGE3NdYX9y0122QsFOhpY
3txSuKx1ZX6awJEz1XXTxJj4Kun37g77LBGsfE3aGjEsTKANYevRyCxOK4+EF9ks
sSAo3bPTqne3KmUE+vPqMSUDXal9u1RYoqk1UL0ke4ceHv967xjyQzwZCz4FY/Vu
SJmWs3dPxy+WU8PV5GLj9oBw9Yp5jYOFFMGJu74TinHcGw3xFEc6Dwp+H295u/Jm
UizpNKWXKqRq4cIs1y4kb425lvygTP3sfuYKKaKsnTF8vlj6s6rvvN5B97epDBrK
SypENZloY8C+laAux1n/hgH96G/8PHpXxvRKBc5eUdqlb3f7+GqPwGJNsSAaOhsX
3rw4wChWJF27z1WQyWPvlVHl68TibzqSWegAOfq4xLAiwtvkvn49nJq4OgMrJUkP
uTWZHZQC4hJ6NPnGQ7myKcSJcSa3nd5nTIqzFUjHUrRDa1mzAVOW2cdpvXp1ROMv
7fqNUgxjOkBPEctwu+DbTyu1sGoUD+IKJxBOeLMm0S6bAXQ9udI=
=8/bA
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-defconfig-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/defconfig
Renesas ARM Based SoC Defconfig Updates for v5.1
shmobile and multi_v7 defconfig
* Enable support for recently upstreamed RZ/A2 (r7s9210) SoC
* Enable NXP pcf85363 RTC which is used on RZ/G1C (r8a77470) based iWave SBC
shmobile defconfig
* Refresh for changes present in v5.0-rc1
* tag 'renesas-arm-defconfig-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: multi_v7_defconfig: Enable support for RZ/A2
ARM: shmobile: defconfig: Enable support for RZ/A2
ARM: shmobile: defconfig: Refresh for v5.0-rc1
ARM: multi_v7_defconfig: Enable NXP pcf85363 rtc
ARM: shmobile: Enable NXP pcf85363 rtc in shmobile_defconfig
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Drop PROVE_LOCKING as it should not be enabled in the defconfig. It
causes quite a bit overhead as noted in the patch description.
Then let's update omap2plus_defconfig for dropped options and moved
options. That way makesavedefconfig can actually be used to generate
patches against omap2plus_defconfig.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlxlrd0RHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXOMQQ//dnvmQ0xiVFFB/I4hfgcI2kHxk4J3nIoO
zPGPb2ygUN6CeFLVSVUv3vytOR4FkvKZU/Z6hyxJTv0cain1yxZ6IfTRjNwKdDxF
UA35AvB992WwBqbu7UxUUSI80dAY9CAqY7Cq0niaFbpQ7giIbL+qQtWLoVHFJi76
V3DQa45QXgNGURJ7bMYxjzb2/mH9cAx7UfOIuePNdACGhf9t/PHYIjJnPA9PLurq
Umgv00FraiUbSQhVF0Pfdd5ljPrpV0pf3DWrsOAnPuPJo2wmLzrfyLi014JSoifH
DGyi47uyq2XXwdHMtfPU0YiRGhP0O9md5nGcGIjKNiAeCISmYgqYtXsTsAah4wDY
2RQajX0y6KKuQobrRewoK82QGgqcJcj3Xd61+luf7wh3w9nTpZ/HrS4pqVC/cvos
S/5Wsj7yT/k+g4LOINzhaBaLVlKhW0KPQtiJpexSjgfLoTSQ32H1aCvpEUpwKcYQ
nUZX/bgKhNmFLeH7V0MnTcnuR2cWcpyK1yO6HyjfxEA3cEbZkrpBVoGd9xOtqDik
miUN54C4vDdidjq20Y+h7ZYvWchBwLbEVr98kaBZvDeBNQpL16+vdx1qLufW/j8F
B7gSJJZNYJd4riRF8R7DSnx1eqDsmqedXVmjGGX14QdpP+5BI//DaGfmY3cQN0eE
79Tc2xtnWmY=
=Cia+
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.1/defconfig-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/defconfig
Defconfig changes for omaps
Drop PROVE_LOCKING as it should not be enabled in the defconfig. It
causes quite a bit overhead as noted in the patch description.
Then let's update omap2plus_defconfig for dropped options and moved
options. That way makesavedefconfig can actually be used to generate
patches against omap2plus_defconfig.
* tag 'omap-for-v5.1/defconfig-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: omap2plus_defconfig: Update for moved options
ARM: omap2plus_defconfig: Update for dropped options
ARM: omap2plus_defconfig: remove PROVE_LOCKING from defconfig
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
We add support for Bosch Guardian am335x device, and configure more
devices like GNSS and LCD backlight for omap3-gta04. And we replace
the wlcore binding documentation URL with a local file that we have.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlxlryMRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXOMDBAAw57p8QZSacuX1OLXcwCotq1p/LWs7423
Y+Dm2UhEdmi89+DL5yDO6Wd46VJ2/mZ9T+WR2cUeUsSs/YPApTmBBB7cBs5Kk7GS
07olRxqnbB+myESx5he5lSfxAwnXRF2is7PE0bf3gTTulPaVkz1/OUYZdwdL8j4q
wabUZ3cyDkr1ZwSiTMpddDlP0o/kNWcGt7Lhu3+kvYygAKqjRaXgtwlFbWDgwQFl
OBFO5lhupC07EItzPYqNxZMKKamf9Gegw86bfa1rFVy5Q5xCKnstKcoShF8i/h4K
2sYq8siUU6r4KNVibIaT0zRdmXBVIcZYzR4dK5MJrzaS64hX+F12p7XDezcUGqfR
/1guoQSHbZL8a/gGFtRdkxmv6UDfVlARY0f+oRRNX3SUAuvaOnmpqFyLNw1MUcsv
OuuciW9O8WE7MZ01hhTokVEI9M0xZXx0xdyx7jr/pAN7vnxrR+mDRNbaxAAr4941
YWjmg77k04qfV9hCKX5dMGMnT+fJWxO6kkfkTqS7OF6QNDHtV8Ym/T5riTxkzeAj
fjB4E9TmQ8Zad2A+bDH2PTIJsjnU1Ofnr/SFCR/ztCw70I+t6yzAGs+mQX6Dve/g
6tcnE0YgBM4x030DlykUixFFB/8OLCCsHP5qGAHtu9yp7Iwda8Yeyt7K4AeetF7l
KYXTWZrxljU=
=gumh
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.1/dt-pt2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt
More dts changes for omaps
We add support for Bosch Guardian am335x device, and configure more
devices like GNSS and LCD backlight for omap3-gta04. And we replace
the wlcore binding documentation URL with a local file that we have.
* tag 'omap-for-v5.1/dt-pt2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: omap3-gta04: declare backlight in lcd node
ARM: dts: am335x: Add support for Bosch Guardian
ARM: dts: gta04: add gps support
ARM: dts: gta04: add ldo 3v3 regulator
ARM: dts: gta04: add pinctrl settings for wkup domain
ARM: dts: omap3-gta04a5: Replace LXR reference with a local one
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Use new "wakeup-source" instead of "gpio-key,wakeup" in Z-Turn
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlxiwoEACgkQykllyylKDCGAJQCbB4cK6W0fXAfw/Zi7mHBEo0yL
lxEAn3/zTTTB2DFB+kimxZFZcHJaEY11
=dMVs
-----END PGP SIGNATURE-----
Merge tag 'zynq-dt-for-v5.1' of https://github.com/Xilinx/linux-xlnx into arm/dt
ARM: dts: zynq: DT changes for v5.1
- Use new "wakeup-source" instead of "gpio-key,wakeup" in Z-Turn
* tag 'zynq-dt-for-v5.1' of https://github.com/Xilinx/linux-xlnx:
ARM: dts: zynq: replace gpio-key,wakeup with wakeup-source property
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- New board support: Logic PD i.MX6QD EVM, ZII SSMB DTU, Phytec
phyBOARD i.MX6UL Segin, Y Soft IOTA Draco, Hydra and Ursa boards.
- Add regulator control for various sensors on imx6qdl-sabresd board.
- Add DISPLAY power domain support for i.MX6SX SoC.
- Add stmpe-adc device node for Toradex iMX6 module.
- Switch to SPDX identifier for imx6q-tbs2910 board.
- Add proper ksz9031 clock skew values for imx6qdl-phytec-pfla02 board.
- Mark I2C recovery GPIOs as open drain and correct and WEIM range
configuration for apalis/colibri boards.
- Small and random updates to various devices.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJcYo+8AAoJEFBXWFqHsHzO+D0H/3RYArKxp1FJ2QVS2w4uE2O7
eWycgtie8d4x84/hdMG72sU/x0hZm0v1kXUGO9Yt17dgX3Dg1Sfv7bECqZAHvG11
6dMuG5u3lCLjQQLieAAUvxpWFCne3gSWVQnb0o/zWiHBeGNQJt42hacLNYaJSqTL
Vao3wiiGTZvVih6B+ueFi4Im/VChEn5rnKmjCqkFTAlUIpVvzLZqY8Jy+vjVC3aP
5tLq8WnStJqgFgxtRpVKDsdu2KjJKCozpw0KZyM3MYQ4blGCCbFpFfyGfBeNves5
xCWrx//rt//ol09X5UXtz4T+/QKC5390styCA9m+XgSFcFSYKgjps+9iD+5a1tk=
=OH8n
-----END PGP SIGNATURE-----
Merge tag 'imx-dt-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX device tree changes for 5.1:
- New board support: Logic PD i.MX6QD EVM, ZII SSMB DTU, Phytec
phyBOARD i.MX6UL Segin, Y Soft IOTA Draco, Hydra and Ursa boards.
- Add regulator control for various sensors on imx6qdl-sabresd board.
- Add DISPLAY power domain support for i.MX6SX SoC.
- Add stmpe-adc device node for Toradex iMX6 module.
- Switch to SPDX identifier for imx6q-tbs2910 board.
- Add proper ksz9031 clock skew values for imx6qdl-phytec-pfla02 board.
- Mark I2C recovery GPIOs as open drain and correct and WEIM range
configuration for apalis/colibri boards.
- Small and random updates to various devices.
* tag 'imx-dt-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (31 commits)
ARM: dts: imx: Add support for Logic PD i.MX6QD EVM
ARM: dts: imx6qdl-sabresd: remove reg_sensors' regulator-always-on
ARM: dts: imx6qdl-sabresd: add regulators control for mma8451 sensor
ARM: dts: imx6qdl-sabresd: add regulators control for mag3110 sensor
ARM: dts: imx6qdl-sabresd: add regulator control for isl29023 sensor
ARM: dts: vf610: Add ZII SSMB DTU board
ARM: dts: pfla02: add ksz9031 clock skew values
ARM: dts: imx6qdl-phytec-pfla02: add missing interrupt-controller property
ARM: dts: Add stmpe-adc DT node to Toradex iMX6 modules
ARM: dts: Add devicetree compatibles for LS1021A based boards
ARM: dts: colibri: use valid range configuration for weim
ARM: dts: imx6: Add support for Phytec phyBOARD i.MX6UL Segin
ARM: dts: imx6*-apalis/-colibri: mark I2C recovery GPIOs as open drain
ARM: dts: vf610-zii-ssmb-spu3: Pass "no-sdio"/"no-sd" properties
ARM: dts: imx: Add Y Soft IOTA Draco, Hydra and Ursa boards
ARM: dts: imx7ulp: add sim node
ARM: dts: imx6ull: change to use new compatible "fsl,imx6ull-usdhc" for usdhc
ARM: dts: imx6ull: Fix i.MX6ULL/ULZ ocotp compatible
ARM: dts: imx6sx: Add DISPLAY power domain support
ARM: dts: i.MX51: digi-connectcore-som: Add support for I2C bus recovery
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- more features for Endless EC100 board
- chip temperature sensor support
- fix ethernet pins
- add Mali-450 GPU
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAlxh4LQACgkQWTcYmtP7
xmWu3w//bOc1aqMh325KmhP+WXUJEp0Z+7/r8TcqYYW2UMdjqGKvYNREaL+cDKu3
6DOaWvTKrRHOJr1L4uSdg1NBEhH6Nzmb7r9bRLkj2xT5vT66pZIiMa4OETfvdvP2
TQ86MPUY69M6IJ2JzeYA34stItYanExDhosbaHmPSJqwvDdh0V932eBg4OY/IpEn
j4Hygf9HYSA5cSx7J2Ah1gUXzI66FcPlRBWrl+jeTS7qqU9GxYo8/8Hrgn6hyCTQ
dpQHvgsCdeHvsf8fRpulxH/aUo5u2nuX1/R8UrOWUmCPd2r3RBu0U27Ja7FJiAeb
s6OwLveAVeMS7Urrh3ylaFstbjg3CMtGvh1hnbWozF08yNzd6ihD5vsUED7vpxNr
hT8m8oC8hujP1CiIxFqbkPZsz/hWoagPOG2AtRNMehs+gVxOfD+CTkw3Y+x3+NrA
DwU9YzrKqFn4StSHJ6ccBE857gSH5QgOq0rLYiH1AlktHvXKh/hL/H82pFDJHZcW
OFZ2nAI9VCPDlx8tCbuH16BIqD03piT5ew0wWozG5uc/JP26stmMXHQlQVDxRju4
NsJiqGzAtgIK+jf2COVZJeYtOO9IYjPwrC0wJe2vWW7MTUBv0LSQDuBV2pTT/N87
pSqeusg80DuPC3WZLGU3whitwO6yg3NiWeGB6cweu3gWeQsMSig=
=PNC5
-----END PGP SIGNATURE-----
Merge tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt
ARM: dts: Amlogic updates for v5.1
- more features for Endless EC100 board
- chip temperature sensor support
- fix ethernet pins
- add Mali-450 GPU
* tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
ARM: dts: meson8b: ec100: add the GPIO line names
ARM: dts: meson8b: ec100: improve the description of the regulators
ARM: dts: meson8b: ec100: enable the Ethernet PHY interrupt
ARM: dts: meson8m2: mxiii-plus: add iio-hwmon for the chip temperature
ARM: dts: meson8b: odroidc1: add iio-hwmon for the chip temperature
ARM: dts: meson8b: ec100: add iio-hwmon for the chip temperature
ARM: dts: meson8b: add the temperature calibration data for the SAR ADC
ARM: dts: meson8: add the temperature calibration data for the SAR ADC
ARM: dts: meson8m2: use the Meson8m2 specific SAR ADC compatible
ARM: dts: meson: switch the clock controller to the HHI register area
ARM: dts: meson8b: fix the Ethernet data line signals in eth_rgmii_pins
ARM: dts: meson8b: add the Mali-450 MP2 GPU
ARM: dts: meson8: add the Mali-450 MP6 GPU
dt-bindings: gpu: mali-utgard: add Amlogic Meson8 and Meson8b compatible
ARM: dts: meson8b: add the APB bus
ARM: dts: meson8: add the APB bus
ARM: dts: meson6: add the APB2 bus
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Contains a single patch that adds the "jedec,spi-nor" compatible string
where appropriate.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlxdmP0THHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoe4QD/4kFg14Rd4ERRZU31B5MNTmVETqEPx4
FGyR0FvMP0eNQCTJE/hrI9yiPVdB1ryE9YU//rsfIcezpTcsLbquEb2QqJqrP5y1
cdENJ7vi5kRV7xIh/UzkaYvg5qp2gYZVL7wMvPfuaSXqExcZqoyiNnHnGbP2oJzg
/GM1doEe8yck6WGLipJMyYtXkWAQydUwhNuWSAMXHKrgisIdB1/BSVXT3Ty9LpXC
doroWS/CeW3QN+VfqXPObXWM4f2EX7ApThblb7cvt55jbb8CenQXlszFGcPq4L29
ZV0s04mNBwXbJl4W0ilaXfCWceyjOx3EPeYJ/XA9khswyFVg7TVXV+AsevSbONya
bfm7c2x5Km35olPTlKo14qhcUw9ExfxyiC/rwi08/LI6wNZFSux9ZYNJL5EYPrxI
7F4ULcJaTG1K/LQy6xXrh98xRy0sSsSklFfGZ8DdOFuHEpHI+RQaWfOXYD4T+2QN
oZIA4x93zbRbvOQGkO7sMm1I9Oa3EI+PRG6QBHJyn/uMbaeA1gdtPr/gpwccTQo1
stgRLDwaxcUuvD0Byz2jAkgOoN2bPUdjqXWnKqHXFSiFoJj2IQOdJqNLw9NfB3j/
JrDOHHsJyHaAKovVAvaGi0zF83ZspVMyw4OnwyCCmeGqUX1BXwHCYzJWI7f+4WQS
R5wzq2pVU4+Opg==
=Cuag
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.1-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
ARM: tegra: Device tree changes for v5.1-rc1
Contains a single patch that adds the "jedec,spi-nor" compatible string
where appropriate.
* tag 'tegra-for-5.1-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: add "jedec,spi-nor" flash compatible binding
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* R-Car H2 (r8a7790) based Stout board
- Convert to new LVDS DT bindings
* R-Car H1 (r8a7779) and M1A (r8a7778) SoCs
- Describe HSCIF0/1 devices in DT
* RZ/G1M (r8a7743) SoC
- Correct sort order of the RWDT node
- Remove aliases: should be defined in board rather than SoC DT if needed
- Remove generic compatible string from iic3: it is not compatible
* RZ/G1N (r8a7744) SoC
- Describe LVDS and DU devices in DT
- Correct sort order of VSP and MSIOF noces
* RZ/G1C (r8a7747) based iWave SBC
- Enable RTC
* RZ/A2M (r7s9210) SoC and EVB
- Initial support
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAlxdXz4ACgkQ189kaWo3
T75wbBAAqOyXvMCt7lGsov4i0e/lqSFl13uHv83Mk+PVvvT48H2g/ItitGDq4GYr
ItAYBRF66XcAKJbA30e4OvAk+yB0Y3iMT8KIR4Nca5ls9rn6NwbyBugZ65mizKEk
vIoA1sGpsWUrK0yxmGoIx9C6aX9qsh82ivdMpvwb1Kzy5oO59GCgJ9d/d+Q2KwvG
rycEPQwHLFIIijoNr0IH3ZiXhyfeEabGHg/EK/FVxJJNgQLjFW0ZogsZ/a49ptoZ
YZqEc2w13a+rWFTg7059UbzPNjJCq0/2lYRPthWTz9KzUyFgSZ+2GvawdoFSvBZ5
cf+6+qZkgkVvs00yajd6Q2t9IcyjeVmU+GBHFSO65wDRJknDN8sE1v/qHaAr0+Bm
My8Th55Tzak/d+6Zb6xP95kTiaUDpWQrjntMvg3AewiAcjDJasBSsU9EDBlEDh3W
VaQVkyyHtWwfiS0qFf4u0Rfgb2DIBYLvXzslipyZnsKih14+rC/S6N3j8rykrOoE
DTjh7Hi4k4xYwqwNFrg9lvGCoAG4aZddyat9SYfgTs65OmG7huyTH5vqtsmB3kN0
0a33nQ8xt24TH6wSHGB17GXeR9JEluqHC0Do9bbis1B6QiSBvcY+Ne1LtFN8O5sH
RNEcoqU1cCLVHvbRJL/3Y5bwYF22f0GvbMxO/vgdmcz2DSxbuL0=
=q0l0
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-dt-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/dt
Renesas ARM Based SoC DT Updates for v5.1
* R-Car H2 (r8a7790) based Stout board
- Convert to new LVDS DT bindings
* R-Car H1 (r8a7779) and M1A (r8a7778) SoCs
- Describe HSCIF0/1 devices in DT
* RZ/G1M (r8a7743) SoC
- Correct sort order of the RWDT node
- Remove aliases: should be defined in board rather than SoC DT if needed
- Remove generic compatible string from iic3: it is not compatible
* RZ/G1N (r8a7744) SoC
- Describe LVDS and DU devices in DT
- Correct sort order of VSP and MSIOF noces
* RZ/G1C (r8a7747) based iWave SBC
- Enable RTC
* RZ/A2M (r7s9210) SoC and EVB
- Initial support
* tag 'renesas-arm-dt-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: dts: r8a7744: Add LVDS support
ARM: dts: r8a7744: Add DU support
ARM: dts: r7s9210-rza2mevb: Add support for RZ/A2M EVB
ARM: dts: r7s9210: Initial SoC device tree
ARM: dts: r8a7779: Add HSCIF0/1 device nodes
ARM: dts: r8a7778: Add HSCIF0/1 support
ARM: dts: r8a7743: Fix sorting of rwdt node
ARM: dts: r8a7743: Remove aliases from SoC dtsi
ARM: dts: r8a7743: Remove generic compatible string from iic3
ARM: dts: r8a7744: Fix sorting of vsp and msiof nodes
ARM: dts: iwg23s-sbc: Enable RTC
ARM: dts: stout: Convert to new LVDS DT bindings
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Deny autoidle for hwmods with the OCPIF_SWSUP_IDLE flag,
that makes hwmods working properly which cannot handle
autoidle properly in lower power states.
Affected is e. g. the omap_hdq.
Since an ick might have mulitple users, autoidle is disabled
when an individual user requires that rather than in
_setup_iclk_autoidle. dss_ick is an example for that.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Our usual round of DT changes shared between arm and arm64.
We have a bunch of changes for board, improving the eMMC support on the H5
variant of the All-H3-CC, enabling HDMI and reworking the CSI driver.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXF1X8QAKCRDj7w1vZxhR
xX9ZAP9KwFKKehrS1QJjTHKeowUKEnRHuDj2MlwTZJgCw/AMMgEAzgRZwY/VH/Os
aQIhJho9hWmBE0dePIZuWzzCp1giNw8=
=7jQV
-----END PGP SIGNATURE-----
Merge tag 'sunxi-h3-h5-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Allwinner H3 and H5 changes for 5.1
Our usual round of DT changes shared between arm and arm64.
We have a bunch of changes for board, improving the eMMC support on the H5
variant of the All-H3-CC, enabling HDMI and reworking the CSI driver.
* tag 'sunxi-h3-h5-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: h5: libretech-all-h3-cc: Mark eMMC HS-DDR 3.3V capable
ARM: dts: sunxi: h3/h5: Drop A31 fallback compatible for CSI controller
ARM: dts: sun8i-h3: nanopi-m1-plus: enable HDMI
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add SMMU node for Stratix10
- Add vendor prefix fo Novtech
- Add a new 96Boards Chameleon96 board that uses a Cyclone5 SoCFPGA
- Add missing reset properties for all IP on Cyclone5 and Arria10
-----BEGIN PGP SIGNATURE-----
iQJIBAABCgAyFiEEoHhMeiyk5VmwVMwNGZQEC4GjKPQFAlxYYAAUHGRpbmd1eWVu
QGtlcm5lbC5vcmcACgkQGZQEC4GjKPSfPA//a013n1vCV9Wz6RsbXNRODXzhV6FN
9uPWAdbkuWrCvDFAH+9s/0nMwxAj8f1HCEK9J07CPRcjcLPO7iHfIUeJ4lbCNCXZ
1ZuLDdK0Y4GjziJ4xlUP0JvUpJXtRKo+XDXVC+jNAMQy6wQpsEYdEwpeTPo94jrv
X0Zait3PeaY6ai6ImzV4QOYYmZ9GhRHjNY/Hc8jSsZeMWk+sMWygExlUngXlpO8c
dvK1Z4dfhrRZyJ/ewjjb/D0eekq8XiIfGmI4A2Cox3A73XAmtPEL3MT57BbPnq7f
jmNmlh7yRrxZHVErSt0dJTOJ6dNx+McuuwSmDL1vR19M44JUbVOjLjDUEwA7tSmr
eQXVhGuYHfxgJT0CeEBIHJAxPZfTqy68IijZYXv4aWimFdsbeAtraY7PKeZ/TnOP
3Aa9GDSks5NsAGVR5AltiNRmZujyQktbcNU8TcNt8tc19Kub8Q9GVhsmPUIKEov8
oAeXq4xbvGe6Ike6cfR1H+P14mgpbxJSZwGQoqky1T3lWqFBhl/93/ixpzt5jMWX
96tHA7VuZ7+in3BoqzHNxZ2PWpHScd3UScLxzxFEotW2nCofXCLCVkW+Zl8xWLa9
eu5GXE0ZzA04Elaagj2MM/rTsIgWFWqROq4A3Za6k5AB7quThr1yMoL+5Q5keOlO
4xAhCKudZb74BS4=
=8OgV
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_for_v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt
SoCFPGA DTS updates for v5.1
- Add SMMU node for Stratix10
- Add vendor prefix fo Novtech
- Add a new 96Boards Chameleon96 board that uses a Cyclone5 SoCFPGA
- Add missing reset properties for all IP on Cyclone5 and Arria10
* tag 'socfpga_dts_for_v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: dts: socfpga: update more missing reset properties
ARM: dts: socfpga: update missing reset property peripherals
ARM: dts: Add support for 96Boards Chameleon96 board
dt-bindings: vendor-prefixes: Add Novtech Vendor Prefix
arm64: dts: stratix10: Add Stratix10 SMMU support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Fixup GIC IRQ flags and GSBI state on MSM8660
* Add USB OTG, gpio ranges, and Wifi support on MSM8974 Hammerhead
* Remove skeleton.dtsi on IPQ4019
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJcV5CEAAoJEFKiBbHx2RXVXysQAK08L4mNPGVLt+NkHVr9kLcD
CUq5emEizYWs1wdA4H+2Zzf/EEMAoGHLI0uX3WnP55fPTbLhVBVVIlvv5+J9KF9T
Y37LF4mMho7JvmDUfq9t4brx9sosduEVpbLyQcmR+avWWbSVjmgajPCyBTOgR/0C
2wUnl0mKDSsZO8fqNiQd8AkeXfkBSDFCYOq6jn2MZ6Aop93Lg7GqZ4/hWp/WRA8Z
9AhgGLNF02O4mIyfZI8k9tf8CYjHNlm3ceIDj1uRBfMtyhLQZDoAWc+zVXQ2njbW
5lLMPdbqZzepNU9ou/4Z4DeVKwAt0EnaOcDiMi7JJ3o8rtQXI9UL0QnKJK1Rcj7K
82XKP+lbzB2/JI62PSk7kT+bQ1EmmJn19wRcjBtP4L+gCdH0kq2QopVEVkhUU7pg
y5cwHKLtKtYlXeXO27h0amYY+xy/MgMfgJMAhxsn2hj+U3N7DJKYSh5nfWpVU2BP
ztobWTvCvnxPTGFXI9Txl00KVgy5Og2pWaMzkge3yAbesqsPNjJamk+BGn8qL75X
ViBnHMmvH2RBgROLcHgJcjrkdeu5xNwps38xlb/5K9L4jT8wPAcal00y/qMv1saR
A56zL+wtuHEOCqyULvKAzNzduVdEoQechCYueZTm+5M/pXkrkddIDcs6xUGvxtPX
bw9AhstcXIl49QRKgeUg
=0M2a
-----END PGP SIGNATURE-----
Merge tag 'qcom-dts-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into arm/dt
Qualcomm Device Tree Changes for v5.1
* Fixup GIC IRQ flags and GSBI state on MSM8660
* Add USB OTG, gpio ranges, and Wifi support on MSM8974 Hammerhead
* Remove skeleton.dtsi on IPQ4019
* tag 'qcom-dts-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
ARM: dts: ipq4019: Remove skeleton.dtsi
ARM: dts: qcom: msm8974-hammerhead: add USB OTG support
ARM: dts: qcom: msm8974: add gpio-ranges
ARM: dts: qcom: msm8974-hammerhead: add WiFi support
ARM: dts: msm8660: Fix up GIC IRQ flags
ARM: dts: msm8660: Mark two GSBI blocks "disabled"
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Here are the changes for ARM NXP LPC32xx and ARM NXP LPC18xx/LPC43xx
devicetree files:
* added dts file for MYIR Tech MYD-LPC4357 development board,
* two missing properties are added to LPC32xx keypad controller device
tree node, this fixes a long-standing problem with its initialization,
* LPC32xx PL11x LCD controller device node got corrected properties,
which allows to use it with a new PL11x DRM driver,
* output voltage level on one of Phytec phyCORE-LPC3250 fixed regulators
is corrected, the fix is needed to remove duplicating platform data,
* Phytec phyCORE-LPC3250 board gets a description of a kit LCD panel,
this completes setup of CLCD device tree node for the board,
* added unit addresses to memory device nodes on EA and Phytec boards,
* fixes of ordinary warnings in dts formatting like leading zeroes,
unused address and size cell properties and so on.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEETKMJMWSwX7CFTVIOqj3i2jwlOWUFAlxXTzIACgkQqj3i2jwl
OWXBRA//RCAfC/GhIyZF1uHIhj/G85sAWuGSYQ90+fEVtyzb1Y+yeBRKkNH2Xi8C
LkSzD58z/1BTaYz68EaRENU3xCkBcBHH8ZymqJP8/pG+/AoLVIg7/wkeFj/BCC80
rESTV4IjTFdbAaqmM8Y/rcWuPTs5fgxZzFdCgqY0FuTee5hx5aLQkA39cIPWJLJz
Ox+e/Yhs00blWZUFyitP5sd/rnVeuNXWqY0VnN8hG4oH4+GJOA8QAIzzq1DTKaj0
43073ymRw4ZOry0qfsbRvjQZwvSAQD+kZx24DXwP+6YFdW8DqdAZPkuCYYMV10JO
tiOg6hHHjM1lKJWom/6N1Z9layMZeyPxBRYQ2Tpn3+5Or05iHgAhbYv5kRvIBZ8W
cL8hA9SNb/g4yRa67GBINdGHlf3nRBvqDgOR0OQEF3Q/JTFferJOb3MhGuIX1fS7
39JRIndLJD10SoK/Nezvc68myei8aQ+YTQBzaNkm3q4q4SuLF9nEb92s313yvzKv
vBwMuaGuTL+pBvDR3qGsFHxrExj1DIbecYqGdvGj0lmSZbNPWeR2ZSj6XGfT18x3
pCmr7C6brY6jWsp6p8nG7ovFkPqv3X3x/gBszLFGFaEedkssabfLesWdZooHIAgJ
Fa6Lc2M7AAwxHT1YDn6+ojrr/yhaQoaray/+aOT9WAwAhElpc24=
=J1uJ
-----END PGP SIGNATURE-----
Merge tag 'lpc32xx-dt-for-5.1' of https://github.com/vzapolskiy/linux-lpc32xx into arm/dt
ARM: lpc32xx: devicetree updates for v5.1
Here are the changes for ARM NXP LPC32xx and ARM NXP LPC18xx/LPC43xx
devicetree files:
* added dts file for MYIR Tech MYD-LPC4357 development board,
* two missing properties are added to LPC32xx keypad controller device
tree node, this fixes a long-standing problem with its initialization,
* LPC32xx PL11x LCD controller device node got corrected properties,
which allows to use it with a new PL11x DRM driver,
* output voltage level on one of Phytec phyCORE-LPC3250 fixed regulators
is corrected, the fix is needed to remove duplicating platform data,
* Phytec phyCORE-LPC3250 board gets a description of a kit LCD panel,
this completes setup of CLCD device tree node for the board,
* added unit addresses to memory device nodes on EA and Phytec boards,
* fixes of ordinary warnings in dts formatting like leading zeroes,
unused address and size cell properties and so on.
* tag 'lpc32xx-dt-for-5.1' of https://github.com/vzapolskiy/linux-lpc32xx:
ARM: dts: lpc32xx: ea3250: beautify gpio keys children nodes
ARM: dts: lpc32xx: ea3250: add unit address to memory device node
ARM: dts: lpc32xx: phy3250: add unit address to memory device node
ARM: dts: lpc32xx: phy3250: setup LCD controller to panel interface
ARM: dts: lpc32xx: phy3250: remove regulators umbrella device node
ARM: dts: lpc32xx: phy3250: fix SD card regulator voltage
ARM: dts: lpc32xx: fix ARM PrimeCell LCD controller clocks property
ARM: dts: lpc32xx: fix ARM PrimeCell LCD controller variant
ARM: dts: lpc32xx: reparent keypad controller to SIC1
ARM: dts: lpc32xx: add required clocks property to keypad device node
ARM: dts: Add DT for MYIR Tech MYD-LPC4357 Development Board
ARM: dts: lpc32xx: Remove leading 0x and 0s from bindings notation
ARM: dts: lpc435x: remove address and size cells from gpio-keys-polled nodes
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
for 5.1, please pull the following:
- Dan relicenses the Luxul DTS files to GPL 2.0+/MIT
- Hao adds support for the Phicomm K3 which is a BCM4709 SoC with dual
BCM4366 radio
- Stefan adds support for the Raspberry Pi A+: binding and DTS files. He
also provides a bunch of DTC warning fixes for the different RPi DTS(i)
files and adds support for missing GPIO lines on RPi 2/3
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAlxVz5oACgkQh9CWnEQH
BwSx3w/8Dtph3vW+OjerHao0vEXM85iYGUyydTvmOB+lM3Cq09vtqgXNX8xTnH8F
jFv5o//vdrLF1JFFthJeR06MGr8BOEncQJKKCEXnEGdkaL50CzvH5pD/q1iOm5ig
qrXiBy8hNd/gmkmj/BUUjKQLViUzelameGOezAI5RE+QzkraO3rIPFItT1R+X5uQ
pc6CPpEmRXWvcUn3QOimqaFW+mePqoez1xA12bBCw9DXAUKX/p3sglTC+kA7t0zC
DfgXYpGhvIk0e7inJIk+rLMJKbD2Pmvd3hS0XT6AnObRFApYwMiso3BVTvEbFvv8
ebt9j+QZmJFcVp68NDErrNjq4yjq+yUqhikd/G3KGfPzCWZHIC4LFQu3LEZjq61Q
NTRxNgRvUwdifRWEAGYWZJdjJSWtnrDdoR3h446bv5WELGF2WDHv5kRs+NEkxkwK
fTHPRFMLAuai6nFiIEnSHfBbcZEH7R0R8+FKmoPYFz6KbU54EzJYDhv+DTjG713K
xqdfNTwyZhC3E9fxXZGGV1Jc/u/HlCuCRiGXIaUAoOz6PTZ6mR/rd8KhlwrzHFfS
Gazr/mOviYAiHzjdFGij3GOL2rgO/izMOEorPtH2bJj01VmmAsJygbZn9oSoSAEn
VxIAiAnT2ShiVuXUVxAvKGtKhu3x3Da1VychBYVw30jzkkgzvHU=
=Ykbm
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.1/devicetree' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contains Broadcom ARM-based SoCs Device Tree updates
for 5.1, please pull the following:
- Dan relicenses the Luxul DTS files to GPL 2.0+/MIT
- Hao adds support for the Phicomm K3 which is a BCM4709 SoC with dual
BCM4366 radio
- Stefan adds support for the Raspberry Pi A+: binding and DTS files. He
also provides a bunch of DTC warning fixes for the different RPi DTS(i)
files and adds support for missing GPIO lines on RPi 2/3
* tag 'arm-soc/for-5.1/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: bcm2835-rpi-zero-w: Drop unnecessary pinctrl
ARM: dts: bcm283x: Add missing GPIO line names
ARM: dts: bcm2837-rpi-3-b-plus: Clarify label for STATUS_LED
ARM: dts: bcm2837-rpi-3-b: Use consistent label for HDMI hotplug
ARM: dts: bcm2835: Fix labels for GPIO 0,1
ARM: dts: bcm2835-rpi: Drop unnecessary #address-cells/#size-cells
ARM: dts: bcm283x: Fix DTC warning for memory node
ARM: dts: add Raspberry Pi 3 A+
dt-bindings: bcm: Add Raspberry Pi 3 A+
ARM: dts: BCM5301X: Add basic DT for Phicomm K3
ARM: dts: BCM53573: Relicense Luxul files to the GPL 2.0+ / MIT
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
1. Extend support for Aries family of mobile devices (e.g. Samsung
Galaxy S) based on S5Pv210 SoC: DRM Rotator, FIMD, PWM vibrator,
power off, touchscreen, Broadcom BCM4329 Bluetooth and cpufreq.
2. Remove hardcoded bootargs on Galaxy S family (proper support in
U-Boot).
3. Fix minor DTC warnings.
4. Fix Exynos4412 Odroid X2/U3 conflicting eMMC GPIO settings and regulator
properties.
5. Fix the eMMC RTSN pin breaking proper reboot on X2.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAlxUmBoQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD115MD/wLf75FsakZ21mCRPmQ2DNhRzlZezCi75YH
7a/AO9j9I2+gL5Bg9oIHS/5l3YnZSDqYfBj61fzHIEp5lzD1UwVBJLUsDS00NKHt
B58/dH2V9pFj9ZyUDJj7MdMCrt7dNznGDOeztG8XRWd7AeoENP3ysDnjvd6FmGLY
2AgoTrql0cGzTwIcL7dTgg1dEdwSTPyQ1rXovAnF6ylRwFnts9xWRgdIm2/IAzHz
/vgdXzApFykWaoEH+5NIskNQZuGgDKi5zAT4h1yMcOamG7FxBRGzaWJiG+YhQC/M
c6wMaOZxnTRDOhLpcVsNS3i1FCIN6TtbAq0kMDz99v7o2RJm3AdroM+Hm4bXc4sU
JKk8PVufQxk37JIygUCBESwVVNhnX4ZzIGQSxX74k9rvLEYjdnzEU0o5s/69h/q+
1kK8t0/2CPVXKRKkNV7X0wAyLYoNtNh84v45Xyp0EJLHgMA2E2L2zojFqKISlilG
4ctnWG9se7PCGBVLAHAX1z2htMPQ0rHdSYi7U5Z5rJoRdVy96CcYMPXCtKxTtqea
02tNyXxi+bgizsQBSTpwG2+66p5vAIwA/PYLM4b6ZcTILmS0jjCZCUS6wfxYYa22
5Y37sPNSxjAOireg0QQJiBiiiHn+0qYakdw/t11zJ8tc2JDhDVD5tYaahpS8IH5g
NDHCIjBDZQ==
=9+iJ
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung DTS ARM changes for v5.1
1. Extend support for Aries family of mobile devices (e.g. Samsung
Galaxy S) based on S5Pv210 SoC: DRM Rotator, FIMD, PWM vibrator,
power off, touchscreen, Broadcom BCM4329 Bluetooth and cpufreq.
2. Remove hardcoded bootargs on Galaxy S family (proper support in
U-Boot).
3. Fix minor DTC warnings.
4. Fix Exynos4412 Odroid X2/U3 conflicting eMMC GPIO settings and regulator
properties.
5. Fix the eMMC RTSN pin breaking proper reboot on X2.
* tag 'samsung-dt-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: Fix pinctrl definition for eMMC RTSN line on Odroid X2/U3
ARM: dts: exynos: Fix eMMC regulator properties on Odroid U3 boards
ARM: dts: exynos: Fix conflicting fixed-regulator GPIO flags and properties
ARM: dts: s3c2416: Fix xti node's missing reg property warning
ARM: dts: s5pv210: Fix onenand's unit address format warning
ARM: dts: s5pv210: Add DMC nodes
ARM: dts: s5pv210: Add support for more devices present on Aries
ARM: dts: s5pv210: Add reserved memory for MFC on Aries
ARM: dts: s5pv210: Remove hardcoded bootargs on Galaxy S and Fascinate 4G
ARM: dts: s5pv210: Use correct fimd variant
ARM: dts: s5pv210: Add node for exynos-rotator
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
improvements for rv1108 as well. RK3066 got support for the core
display components and the Edison tablet got its touchscreen added.
Apart from that a wider fix to drop display-wp usage from places where
it shouldn't be used, a pin fix for Edison and a cleanup to prevent
rk3036 board from defining sound-dai-cells for core components in
each board separately.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlxTAPIQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgYbQCACiWIYVLrOwOPSgDo3xRFygo2Bmlo2EncEz
UZM0z3gQpzQ8go7Ms6eqL7qRoMI14Cc3XT6dNkzjRBIBaJAi3LXy1G4CLMzxuurD
qri6shmJv94TfBNISJ9FOQYqJRxSK1z4ncp6iXNeOgOa9NCkqSXkHTOve8oVAxfj
nBnMAA0kkX/haF4pNaLoDUv3ppMi7UHjAuoyJMNaTFqVG9qjR1DPNBnCGdYZGacU
Xkb/9n/QOLsJc/yoMcUno+Q5tUVkLsxQVhsApf9Tf7Hd76WV0dgIzi0hENvoKJjK
TwfHz26NyNzw9KbX5YJmNGUAbgesjVBx5AXJk+pBZvrBWGUDtixE
=VDwG
-----END PGP SIGNATURE-----
Merge tag 'v5.1-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
New board the Elgin-R1 based on the rv1108 soc and a number of small
improvements for rv1108 as well. RK3066 got support for the core
display components and the Edison tablet got its touchscreen added.
Apart from that a wider fix to drop display-wp usage from places where
it shouldn't be used, a pin fix for Edison and a cleanup to prevent
rk3036 board from defining sound-dai-cells for core components in
each board separately.
* tag 'v5.1-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: clean up the abuse of disable-wp
ARM: dts: rv1108: Add support for rv1108-elgin-r1 board
dt-bindings: Add vendor prefix for elgin
ARM: dts: rockchip: rv1108: Add spim0 and spim1 pinctrl groups
ARM: dts: rockchip: Add missing dma-names SPI support for rv1108
ARM: dts: rockchip: add rk3066 vop display nodes
ARM: dts: rockchip: add focaltech touchscreen to rk3188-bqedison2qc
ARM: dts: rockchip: fix cif1_pdn pin on rk3188-bqedison2qc
ARM: dts: rockchip: add HCLK_HDMI to rk3066 vio power-domain
ARM: dts: rockchip: move rk3036 i2s sound-dail-cells into soc dtsi
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
mic input on da850 LCDK board.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJcVAHxAAoJEGFBu2jqvgRNKDsQAIQxTufIRkRxbd+diYCcMlas
9HINvZklP/Utqg4oo5tEaAH8An1E7AR67UcOwvCzFU4tN6vBMsnZN+oaBJ9Tsfbi
0fB5lld/WYAN/+4wQpv6lOI1A2kNohi9nKZLiwDvEhFFTevoeciS8Ypepl9h7Zr4
PyQ7xthz29vsbE8TzpFIs4225VrqFCjXMa5hzrDmuaj4Fn6wMBwhgnLbfW8plg2j
FzxZj1t5ZoOUIOkokdGXwcPMkY86cVc0ntEQLWy8lRqnX3zzpYbJ4zk7Fg4XH2wE
DzJSXeJIPO8nqN3XXmDYEXSmO0X3KRHam5ggVKtaQVPEur04AsJTaJqhUlQGKDi+
LmGXi0d/SGg581VPbsgF6rk9Suxzq6EPHZ6zkx1AFLnHfXzTSFOoUdgkQ7pqarM/
529dYiVrWztk3NB0mYCI3q30l7SIuKh9R8WlAXhAnHCb8v2467VKBvIXcPI3UrSz
OESTln6gl9ZKkkp6ZlGFfIWWTzdoSg2blO3izIjVVzvPDFF7J4Sa2/fHORGAJBlt
slFUEjc5PicXj60rG+1jRunGu0YLUjqvJFSJzH8nGnUsBbHhnFhf0/eYzC+Li+2R
pUk6U+7UP9rSdqUYYTw+U+wHzWGYcDxcBMjUg+qt6djFm2uGGyLAHujDyXnFyP5z
42t2Zt3tnsjJh22J/uTH
=6oqi
-----END PGP SIGNATURE-----
Merge tag 'davinci-for-v5.1/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into arm/dt
DaVinci device-tree updates for v5.1 contains a patch to enable analog
mic input on da850 LCDK board.
* tag 'davinci-for-v5.1/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: dts: da850-lcdk: Enable the analog mic input
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This series contains board specific dts updates and few minor
clean-up changes:
- add stdout-path for am335x-chiliboard
- add wlcore wakeirq for omap3-evm, pandaboard and omap4-droid4
- remove unnecessary address-cells and io-cells for am33xx
- replace deprecated linux,wakeup with wakeup-source property
- use spdx license for am335x-shc
- configure ethernet pins for omap4-sdp
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlxTIEkRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXM2BA//cCf3AQJ3NsQu0Ptg8gA9KE7QgJGNS2Om
kyBr8lI5VKOS7BTNTvocplOTIzaAPLGivmQVlmcOl5AIk4CcfCjzo0Z67Z/9QM4Z
JMmcrhLR+R5Ha6xpWMq0C9fYnV4gbPmZExr+MIg8vOx65ln6j4yYATFNX+2pc7SN
BAXmj5AHr06CTKS6gjPYJ4Mb/YNNcf2WB2fgSmXff8TQ5zO75GnJU/RY80kdQyB4
aHD4KKg9exuRRJxf/mDnQMos6hkanUlciZ0I+QgIizL3/+z8T0psRjNIet5zoi/n
8yqlXT60T+C8t3s9KoVt7Ls2sdW5tZUz28V6Us7sYuEPi2BKXhaU5tm1mjrdRfTx
Iny+d/otKgGMjiuX040GUezzJMdZUz5N5Ah/WaGCgCpyvGMuIosqprGxnBBOH+pp
2sN8Quaq80x6kKkVFwrU1fsU4QsBlc2vqEXMb/DSZRnT+aQn8Eek6DB++nl/bHuy
RxlXR5xg/nFGN4XeFIlIEJjSEBYb6V+6erln4XkPPhbSE9v/Dj6ycFIF5W0B/lDB
gtOHhTH0kn154A3Wtx6BB6sntjRQ+mr8LX2CcfR18VPg3Jh4L0rjpxJ4niIt5VG5
dPIkZPIPHE3fqJTLSpD1yFydIg3xsLv5MZ1i5Tz2B4cOMgwwNoR/kUN9xZATThA4
NE+4kOVt3rU=
=6JIq
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.1/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt
dts updates for omap variants for v5.1 merge window
This series contains board specific dts updates and few minor
clean-up changes:
- add stdout-path for am335x-chiliboard
- add wlcore wakeirq for omap3-evm, pandaboard and omap4-droid4
- remove unnecessary address-cells and io-cells for am33xx
- replace deprecated linux,wakeup with wakeup-source property
- use spdx license for am335x-shc
- configure ethernet pins for omap4-sdp
* tag 'omap-for-v5.1/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: omap4-sdp: Make ethernet working even if booted with latest u-boot
ARM: dts: am335x-shc.dts: Switch to SPDX identifier
ARM: dts: am437x: replace linux,wakeup with wakeup-source property
ARM: dts: am33xx: Remove unnecessary properties
ARM: dts: omap4-droid4: Configure wlcore wakeirq
ARM: dts: Configure wlcore wakeirq for pandaboard
ARM: dts: Add wlcore wakeirq for omap3-evm
ARM: dts: am335x-chiliboard: Add stdout-path property
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Two changes to add support for McGill University's IceBoard telescope
ARM + FPGA instrumentation board. This board is used for several
telescopes around the world, see the related device tree commit for
some interesting links for more information.
Note that these changes are based on the related ti81xx soc changes.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlxTHpMRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXPIjg/9F44dfPdlGf8Dk14pTEGpOUOBIbNoSpod
4IKB1DDu84NEVeoH8cDxp98U++Bra/JGwUwa5gEkZOa/qZG/iTpcJckpLCeKu3qf
2OKb+cU1+ByYUJqn2Ji8LyQ6Spi2XafGKDCGFcXB7XcDx1SgMlOllQLaf2lPVtsq
IUsBHzmtFbj0DZ+laEGQTQxnSefEFvLpb5r7lM7grA3AuNQFSxz3QAy2QE7Cbfxs
IeVbVeDBqI6OtbYwW7muOds19CZToqIVe3kNydxEXvUdBB3qzB8rIy1a6kbH4lgH
0+J4TqjZ7Iwqlcew9h4CO1AO3P11/PKdFM4lQt8hA9e90qM48zW1WEeMbteliP6x
XnEo5sQQd62Qf8lQUeh8b7uw/6fABQIML7kdqcIiAKC6BfWClJv1wLLpRPV9UGGm
CKDkTsMEuEZPBM0TVf1BZVzQA6pwVO0FJfmjcG/yvUDATGNBj0zCdUKpiBVVnXa+
kTSQpLlbkuDARg/KVTVEkNf9CsqzNJyah5BhYbZUPhyoxs00vRJRRa+4Ay0Gpw7O
HggCvLL73y+8QNMOUj9FKmHA+cnIqB15tRmQ3+K3FCBpmmOediS6hp1Kufk9e9Y/
cTONQQUR2IqwnTdYoxR093xEdPkksQO7FOm/KmSLU/PgaqZNmAje6kZf9OT/tv53
Fn/96rJvrBE=
=ucZD
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.1/dt-ti-81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt
dts updates for ti81xx for v5.1 merge window
Two changes to add support for McGill University's IceBoard telescope
ARM + FPGA instrumentation board. This board is used for several
telescopes around the world, see the related device tree commit for
some interesting links for more information.
Note that these changes are based on the related ti81xx soc changes.
* tag 'omap-for-v5.1/dt-ti-81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: Adds device tree file for McGill's IceBoard, based on TI AM3874
ARM: dts: ti81xx: Add dts boilerplate for all GPIO and SPI peripherals
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Two changes to add legacy hwmod data for gpio and spi peripherals on
ti81xx. We have not yet updated ti81xx to probe devices with ti-sysc
interconnect target module driver, so these changes are still needed
to make devices usable for the related device tree changes.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlxTGfwRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXMTDxAAsGXhQz6TfSUZGcYVow/1v3l/1Mr3S/Yb
gBMeHVQqoGFTU4eCGHEL3X2qNFE+0Kfq1Sbqbfq6sbyzqiExjbYFF58hMJVHVxRX
WzO/GNEZFugdFf70K2sb/d5xZEq1YIlxna8Brg32zIp6YROLREtNPUO3Lehn21rj
KKWAb00fnyt04XM1JI/Q/tOQeRsz+Ec3KytSkYzGt8jaaEgzU8tH05uVfQB7Qshv
z5mr737CHnUXH/AaEFzboUlTzETPM03oHObBpylPYCvBgzGPKCHsBHdPfIYqiEyn
pgoBGJT6ZqsxfhcLi9umoUxHMJAVhGh8pB01sewct8sbhWdT5fOuOwlFl9Rhvpue
kkj8bqWMKHz9TFACiXtqj6qGQt9Fm61w2i8cAvlpjMPRLo+a+qDZeqcum9X5PnwA
pKKoc0gMEZmg7LWSFiPuXdxeL3QG4NtB/KI0CiDg2xHU/+wTKiIGq29V9tBag70h
1UAyhDMkqsG/pIM01kOnKSkNIIRLgqjTMyuwEJnKdB7m7QF5aSw1UQethEIjXXzb
24vDHdTBlg9tb7pKn6/QL92PWtT6ceRsz9Ck7zR1UpijK+KlFfsPz1VYk+L9Op8G
7Lfux80AEuuz69PH3V23bsvysFIqgGXpzExEiVsVcJQz0GZ5DutyY5JNo/8uptNd
bjoJMWKfPbo=
=f3Ol
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.1/soc-ti-81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt
SoC updates for ti81xx for v5.1 merge window
Two changes to add legacy hwmod data for gpio and spi peripherals on
ti81xx. We have not yet updated ti81xx to probe devices with ti-sysc
interconnect target module driver, so these changes are still needed
to make devices usable for the related device tree changes.
* tag 'omap-for-v5.1/soc-ti-81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: ti81xx: Add hwmod boilerplate for all GPIO and SPI peripherals
ARM: ti81xx: Move I2C entries in omap_hwmod_81xx to maintain grouping
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlxS/KYQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgUdCB/9d8IN+iZUxo1TX5QS0ov+1FYhkly6FNEj2
JGQYL5zCDGe5RvgfyqL3vi3kHFQoDIHjsRQBUl14/ryo+InIl8ZJWl38tFjHYmdw
o883g3zyJLbwKrsE2RBtWtWsoK5TSwbV7xR3JO8tHWFV+mXDUUcFFXpR5VRjnQ9l
XsjvvzznfQQLpUzJy5OAjTAhtvkXExM74h4MpwIXtyeqrWUI73a6uBUeY6Js43rZ
zTfyv8Ikla3eP+fMQqf60CwKjxhQwyG7/7UxWp7iIatsUMeC5VLRCZuM7l109pH0
hKQLWybzcReCPfTqQ2rAwAhBQmQIpEvdwhFk5WA1mmqMi/d/Zdoh
=oEEi
-----END PGP SIGNATURE-----
Merge tag 'v5.0-rockchip-dts32fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
Drop one non-existent component from powerdomain list.
* tag 'v5.0-rockchip-dts32fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: remove qos_cif1 from rk3188 power-domain
This series contains two SoC regression fixes and one uninitialized
variable fix:
- Fix inverted nirq pin handling for omap5 that started producing
warnings with earlier GIC direction checks and took a while to
understand and confirm. Basically there are two sys_nirq pins
that are bypassing peripheral modules and inverted automatically
by the SoC and need to be handled with a custom irq_set_type()
- Recent ti-sysc changes caused a regression to the pwm-omap-dmtimer
code where the device tree handling code for timer source clock
gets confused. It looks like we can remove that code eventually,
but for now we just drop a bogus pm_runtime_irq_safe() for the
timers with the related quirks caused by pm_runtime_irq_safe(),
and have the standard assigned-clocks and assigned-clock-parents
deal with setting the source clock
- Fix potentially uninitialized value for display init code if
regmap_read() fails
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlxR8TERHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXNhNQ/+JfJVPT4SyF0KQz8BJYYF2bVvJyFv0kBR
XrGIi6KTdoiN9Bm3Trt1rM+YJpS2Ii2YAc2frGVE4qMHw6ZUZA1uDxDl6J6C04H+
Eb7XrYnt0hqzuLfmx5ubX2eem92AgszWou85v8flwIk7dUJWtNkhUFTZtoDujLSM
ZnBWcG+9MuSWGpcigu1O9Qt/ePwQerxAksE46fKlbjZrk03j/Eh3A3YCTInV7sgR
Dl+jZhfva92GupcBzMsjWYaqLzdBG7Cq4pGfbhyTHdaapt26nK/osuNPh+zFgWZe
ppKbyPcQQ9ph9qJWd6A/BN9uN3zQfBwwtjVWaGX0LqahsEcIQyjj6QSKMjbYdNOK
fdXuL3Du6zMeQlez1mjS9xBU9s8B1N60F+vCVanDZW8ynkPZp7gBnG5vxC9ZEfR3
ZVLzhWMwejmidnPi9Clm/OHiU7ExAKwS6ql7qnhZS/3l8sdzm6Rs9ZQ1UO7scdfc
8MrB6wKNYQHPeoDLxmOa+DvSn64BPEboZtm2IoP+fvOvoJoffcM7FSxWTkkElrLO
6jgtRRm6Raw4vJvWmSJVIH8lpzthnOmdhtf+Ni9ZKysAPmj2N2uROdcjlqgOBvCf
xagW4iSUXMLNa2W1IgcTOxeAQs+ASVm3AvG02kx1ImMlnWrLJQO2yOW7DYdd6sCJ
x23XUpsiFeA=
=5oVS
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.0/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
SoC fixes for omaps for v5.0-rc cycle
This series contains two SoC regression fixes and one uninitialized
variable fix:
- Fix inverted nirq pin handling for omap5 that started producing
warnings with earlier GIC direction checks and took a while to
understand and confirm. Basically there are two sys_nirq pins
that are bypassing peripheral modules and inverted automatically
by the SoC and need to be handled with a custom irq_set_type()
- Recent ti-sysc changes caused a regression to the pwm-omap-dmtimer
code where the device tree handling code for timer source clock
gets confused. It looks like we can remove that code eventually,
but for now we just drop a bogus pm_runtime_irq_safe() for the
timers with the related quirks caused by pm_runtime_irq_safe(),
and have the standard assigned-clocks and assigned-clock-parents
deal with setting the source clock
- Fix potentially uninitialized value for display init code if
regmap_read() fails
* tag 'omap-for-v5.0/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Variable "reg" in function omap4_dsi_mux_pads() could be uninitialized
ARM: dts: Configure clock parent for pwm vibra
bus: ti-sysc: Fix timer handling with drop pm_runtime_irq_safe()
ARM: OMAP5+: Fix inverted nirq pin interrupts with irq_set_type
clocksource: timer-ti-dm: Fix pwm dmtimer usage of fck reparenting
- finally remove legacy platform data as all users have been switched
to using device properties and nvmem notifier chain
- add support for the 'num-addresses' property
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEFp3rbAvDxGAT0sefEacuoBRx13IFAlxlKUgACgkQEacuoBRx
13KYNhAAlAIEWvp41luNy5MeAhMdLue4ruWNqkUrI/VmoxAY6DFPtwiZirjRF9HT
1XK+T+CRiHGgjiMV2YvjEh1XLZYmnuUQnTVbJ50O9UDizewcwHB4Vqi0Llyz+kaI
RPzO+iyt61UYGbLmsE+UemOiefWnvq3BlPMHY4X3RjhOyDie/N8D+t+zePIhqDmZ
5iEHAkkVavznyQ60x1KZMojU6bsG6zbhoLdFcSty5oDpQ1vtsTRMvnuXWwzqnama
czTLbza9XPXOoBdB7P2TAcBQII36PptCLQdmcqY9knBvRHGM6L8JKMha0huNS0u4
OogHod7M9jPJbMPnsh21S4JpR5z4R1UUeM95V8a7FRTjN0EC2jDFEAsQj1bbAMTn
Zj0oYUq0lljriyuPisQ5hPkUIDV+XztOYgt/acPbo3UwtIjGe9gsCKJYVfrXM8EK
NfIQsAXQb/r12f49b32IVgCxEIsk6jFvsRDAsWIUlreHf8wMWOD5fir7r1CjRqac
ngQC1y9At0TgQwUN+Qzmch0oeAuOmm/yfZsroeRK3NQmKsgakRO57FfvSD0TDK6Y
5QELKonwEazgt+oSzbFlUdDyVuMIQ39pYGXgs0HJl07lPK2oyg8od0JP44Vw4SoA
bxUrHUG/VL238DmkPMa+UZFpEnj7v+Lb7cgcrArTg+y3M7wpke4=
=Jbyk
-----END PGP SIGNATURE-----
Merge tag 'at24-5.1-updates-for-wolfram' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into i2c/for-5.1
at24 updates for v5.1
- finally remove legacy platform data as all users have been switched
to using device properties and nvmem notifier chain
- add support for the 'num-addresses' property
- Fix the way we reset vcpus, plugging the race that could happen on VHE
- Fix potentially inconsistent group setting for private interrupts
- Don't generate UNDEF when LORegion feature is present
- Relax the restriction on using stage2 PUD huge mapping
- Turn some spinlocks into raw_spinlocks to help RT compliance
-----BEGIN PGP SIGNATURE-----
iQJJBAABCgAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAlxcHeIVHG1hcmMuenlu
Z2llckBhcm0uY29tAAoJECPQ0LrRPXpD4jUP/inpLftQam7i+BNeZmaHbTEDAjOb
6i4AXnjkZfbC5fu6Kf0GXNAEvjsbQB2OuAM3G49c6eSjPz/NeY2Y1XBJkiNblmcu
toOWXHABRmUrFa6Lo3z6SE7MYBe4oZpBiX1By3qcWSdRDYM4sIz/9TdIFEIgtjgX
TrlsmPwjOsGoJs/MwRPoM74ZR6oEF8D56HwKNOQHr8jGVgMdKw6cWUood4oljNyx
ncxl63M4fuNfhc7qttp3WSyHjBK5huZvTtyoUfgfq5aPFkRkRNgTO+JOy+VHbQfy
E99l+YBKHgWf9ZE8hioSzvqqTJisO0EMeS6sGW2NvtStEIeYwEzwV6qnjeFhy/lk
yn0WqFlcqFsS6ip3AU5RzbyzxGnaeammTHEoyvOxHGaQZ2Tvw/VaQxdJLeAKe4z1
I6h8JuGj8fVtVgd45mOQTrTkGER1gSkmwQcAU7kJU6nk/fVL0lvYijBD0JUeXUcx
YR457UjgmNGUfFD2vtSfrKcff9mdZjEUvFTYTquy9G5y+nfIo8N5+EtQu3bbukDR
PHhH6Z/9TpjN1mk6uiUB+lDDgq5lYj0Q9sKxGRngAZpm4UasyTmyXNf9dS2sehzO
IiAuCqSlXKTg8h4exFqqigEuGzWirGuj5+NtJwhY5dmftJH9c8v+Ik1+XO5UzlN/
rByichaaiR4ILgVX
=PNZ5
-----END PGP SIGNATURE-----
Merge tag 'kvm-arm-fixes-for-5.0' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into kvm-master
KVM/ARM fixes for 5.0:
- Fix the way we reset vcpus, plugging the race that could happen on VHE
- Fix potentially inconsistent group setting for private interrupts
- Don't generate UNDEF when LORegion feature is present
- Relax the restriction on using stage2 PUD huge mapping
- Turn some spinlocks into raw_spinlocks to help RT compliance
