Commit Graph

12 Commits

Author SHA1 Message Date
Thomas Gleixner
9c92ab6191 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282
Based on 1 normalized pattern(s):

  this software is licensed under the terms of the gnu general public
  license version 2 as published by the free software foundation and
  may be copied distributed and modified under those terms this
  program is distributed in the hope that it will be useful but
  without any warranty without even the implied warranty of
  merchantability or fitness for a particular purpose see the gnu
  general public license for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 285 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-05 17:36:37 +02:00
Axel Lin
74a484ced2 clk: qcom: lcc-ipq806x: Fixup overriding val in regmap_read call
Drop the assignment of regmap_read return code to val, so the code checks
the value read.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01 17:44:09 -07:00
Stephen Boyd
c430daf951 Revert "clk: qcom: Specify LE device endianness"
This reverts commit 329cabcecf.

The commit that caused us to specify LE device endianness here,
29bb45f25f (regmap-mmio: Use native endianness for read/write,
2015-10-29), has been reverted in mainline so now when we specify
LE it actively breaks big endian kernels because the byte
swapping in regmap-mmio is incorrect. Let's revert this change
because it will 1) fix the big endian kernels and 2) be redundant
to specify LE because that will become the default soon.

Cc: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-12 14:24:24 -08:00
Stephen Boyd
329cabcecf clk: qcom: Specify LE device endianness
All these clock controllers are little endian devices, but so far
we've been relying on the regmap mmio bus handling this for us
without explicitly stating that fact. After commit 4a98da2164cf
(regmap-mmio: Use native endianness for read/write, 2015-10-29),
the regmap mmio bus will read/write with the __raw_*() IO
accessors, instead of using the readl/writel() APIs that do
proper byte swapping for little endian devices.

So if we're running on a big endian processor and haven't
specified the endianness explicitly in the regmap config or in
DT, we're going to switch from doing little endian byte swapping
to big endian accesses without byte swapping, leading to some
confusing results. On my apq8074 dragonboard, this causes the
device to fail to boot as we access the clock controller with
big endian IO accesses even though the device is little endian.

Specify the endianness explicitly so that the regmap core
properly byte swaps the accesses for us.

Reported-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Tyler Baker <tyler.baker@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Cc: Simon Arlott <simon@fire.lp0.eu>
Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-11-20 13:14:43 -08:00
Stephen Boyd
9bc432cb24 clk: qcom: Drop calls to qcom_cc_remove()
Now that qcom_cc_remove() is a nop, drop calls to
qcom_cc_remove() and any empty driver remove functions.

Cc: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-08 23:53:01 -07:00
Georgi Djakov
adb11a40a3 clk: qcom: Constify the parent names arrays
Make const both the array and the strings, so they can be
moved to .rodata section.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 17:20:59 -07:00
Stephen Boyd
b3261d768b clk: qcom: Fix ipq806x LCC frequency tables
These frequency tables list the wrong rates. Either they don't
have the correct frequency at all, or they're specified in kHz
instead of Hz. Fix it.

Fixes: c99e515a92 "clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver"
Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-26 22:43:30 -07:00
Georgi Djakov
293d2e97b3 clk: qcom: Introduce parent_map tables
In the current parent mapping code, we can get duplicate or inconsistent
indexes, which leads to discrepancy between the number of elements in the
array and the number of parents. Until now, this was solved with some
reordering but this is not always possible.

This patch introduces index tables that are used to define the relations
between the PLL source and the hardware mux configuration value.
To accomplish this, here we do the following:
 - Define a parent_map struct to map the relations between PLL source index
 and register configuration value.
 - Add a qcom_find_src_index() function for finding the index of a clock
 matching the specific PLL configuration.
 - Update the {set,get}_parent RCG functions use the newly introduced
 parent_map struct.
 - Convert all existing drivers to the new parent_map tables.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-23 16:09:19 -07:00
Stephen Boyd
5cf065f556 Merge branch 'clk-fixes' into clk-next 2015-03-12 12:20:36 -07:00
Stephen Boyd
9d3745d44a clk: qcom: Properly change rates for ahbix clock
The ahbix clock can never be turned off in practice. To change the
rates we need to switch the mux off the M/N counter to an always on
source (XO), reprogram the M/N counter to get the rate we want and
finally switch back to the M/N counter. Add a new ops structure
for this type of clock so that we can set the rate properly.

Fixes: c99e515a92 "clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver"
Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-12 12:20:30 -07:00
kbuild test robot
3b34109a4d clk: qcom: fix platform_no_drv_owner.cocci warnings
drivers/clk/qcom/lcc-ipq806x.c:465:3-8: No need to set .owner here. The core will do it.

 Remove .owner field if calls are used which set it automatically

Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci

CC: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-25 12:14:35 -08:00
Rajendra Nayak
c99e515a92 clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver
Add an LCC driver for IPQ806x that supports the i2s, S/PDIF, and
pcm clocks.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
[sboyd@codeaurora.org: Reworded commit text, added Kconfig
select, fleshed out Kconfig description a bit more, added pll4
configuration and reworked probe for it, added muxes, split out
dt-binding file]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27 11:49:19 -08:00