3 Commits

Author	SHA1	Message	Date
Haojian Zhuang	ea010e5188	clk: hi3620: add gate clock flag ... Add missing CLK_SET_RATE_PARENT flag for gate clock. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>	2013-12-11 16:42:23 +08:00
Haojian Zhuang	5e39edd485	clk: hi3620: fix wrong flags on divider ... The flags on dividers should be CLK_DIVIDER_HIWORD_MASK, not CLK_MUX_HIWORD_MASK. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>	2013-12-11 16:42:11 +08:00
Haojian Zhuang	0aa0c95f74	clk: hisilicon: add common clock support ... Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is used to support the clock gate that enable/disable/status registers are seperated. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>	2013-12-04 18:36:45 +08:00