Commit Graph

4 Commits

Author SHA1 Message Date
Peng Fan
d2199b3487 ARM: imx: use device_initcall for imx_soc_device_init
This is preparation to move imx_soc_device_init to drivers/soc/imx/

There is no reason to must put dt devices under /sys/devices/soc0,
they could also be under /sys/devices/platform, so we could
pass NULL as parent when calling of_platform_default_populate.

Following soc-imx8.c soc-imx-scu.c using device_initcall, need
to change return type to int type for imx_soc_device_init.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-05-20 23:03:42 +08:00
Anson Huang
9edf908a16 ARM: imx: add i.MX7ULP SoC revision support
i.MX7ULP SoC's revision info is inside the SIM module,
bit[31:28] of JTAG_ID register defines revision as below
from B0:

0001        B0
0010        B1

This patch adds SoC revision support for i.MX7ULP, test
result as below:

root@imx7ulp-evk ~$ cat /sys/devices/soc0/revision
2.1

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-16 09:36:07 +08:00
Anson Huang
6d45a4028c ARM: imx: add i.MX7ULP cpuidle support
This patch adds cpuidle support for i.MX7ULP, 3 cpuidle
states supported as below:

1. WFI, just ARM wfi;
2. WAIT mode, mapped to SoC's partial stop mode #3;
3. STOP mode, mapped to SoC's partial stop mode #1.

In WAIT mode, system clock and bus clock will be enabled;
In STOP mode, system clock and bus clock will be disabled.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-15 23:03:40 +08:00
A.s. Dong
de70d0e9d4 ARM: imx: add initial support for imx7ulp
The i.MX 7ULP family of processors features NXP's advanced implementation
of the Arm Cortex-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D
Graphics Processing Units (GPUs).

This patch aims to add an initial support for imx7ulp. Note that we need
configure power mode to Partial Stop mode 3 with system/bus clock enabled
first as the default enabled STOP mode will gate off system/bus clock when
execute WFI in MX7ULP SoC.

And there's still no MXC_CPU_IMX7ULP IDs read from register as ULP has no
anatop as before. So we encode one with 0xff in reverse order in case new
ones will be in the future.

Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-10 08:56:30 +08:00