When booting a board that does not have a keypad (such as imx6q-sabresd) the
following error is seen on boot:
imx-keypad 20b8000.kpp: OF: linux,keymap property not defined in /soc/aips-bus@02000000/kpp@020b8000
imx-keypad 20b8000.kpp: failed to build keymap
imx-keypad: probe of 20b8000.kpp failed with error -2
Let's disable the keypad functionality in the dtsi files and let each board dts
enable it when needed.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
imx6sl fec MDIO clock source is from ipg 66Mhz, but the currect imx6sl
device tree define it as "enet_ref" clock (50Mhz), so the patch just
corrects imx6sl dtsi fec "ipg" clock.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add alias for FEC ethernet on i.MX to allow bootloaders (like U-Boot)
patch-in the MAC address for FEC using this alias.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Per bindings of fixed-clock, #clock-cells is a required property. Let's
add it for those fixed rate clocks.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Those two properties should have been set to zero, which
is the same as not specifying them.
Having address-cells set to 1 causes OF interrupt
mapping routines to add 1 to the interrupt-cells
property and as result fail because all calculations
are off by one.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
imx51-ssi and imx21-ssi are different IPs. imx51-ssi supports online
reconfiguration and needs this for correct interaction with SDMA. This
patch adds imx51-ssi before each imx21-ssi for all imx6 SoCs.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
We need to use controller id to access different register regions
for mxs phy.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Instead of calling the regulator for the ARM core as 'cpu', let's rename it
as 'vddarm', so that we keep a better consistency with the other internal
regulators:
vdd1p1: 800 <--> 1375 mV at 1100 mV
vdd3p0: 2800 <--> 3150 mV at 3000 mV
vdd2p5: 2000 <--> 2750 mV at 2400 mV
vddarm: 725 <--> 1450 mV at 1150 mV
vddpu: 725 <--> 1450 mV at 1150 mV
vddsoc: 725 <--> 1450 mV at 1200 mV
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Device tree for iMX6SL doesn't have an existing cpu frequency table
as well as the VDDSOC/PU.
Signed-off-by: John Tobias <john.tobias.ph@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Make the interrupts node slightly more readable.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that
boards that share the same pinctrl setting do not have to define it time
and time again in <board>.dts. However, along with the devices and use
cases being added continuously, the pinctrl setting nodes under iomuxc
becomes more than expected. This bloats device tree blob for particular
board unnecessarily since only a small subset of those pinctrl setting
nodes will be used by the board. It impacts not only the DTB file size
but also the run-time device tree lookup efficiency.
The patch moves all the pinctrl data into individual boards as needed.
With the changes, the pinctrl setting nodes becomes local to particular
board, and it makes no sense to continue numbering the setting for
given peripheral. Thus, all the pinctrl phandler name gets updated to
have only peripheral name in there.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Most of this branch consists of updates, additions and general churn of
the device tree source files in the kernel (arch/arm/boot/dts). Besides
that, there are a few things to point out:
- Lots of platform conversion on OMAP2+, with removal of old board files
for various platforms.
- Final conversion of a bunch of ux500 (ST-Ericsson) platforms as well
- Some updates to pinctrl and other subsystems. Most of these are for
DT-enablement of the various platforms and acks have been collected.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJSgB6cAAoJEIwa5zzehBx3uuEP/0n8b7qgmx2e0HPtx3qlqPiR
3bit2/5MzJNufb46qnYhhE+DF+bo1yfGlrIQK7nBXuv1fMKKlVMoUZ7Ql3EBbPzd
UWrENl2eiapO7D9uN9EZ5WVYu+tKJewU89xkhM70xlCBUHGgQ4k958E8TH9vmELI
Qj1s2UcsYftMF9EH6sbQZ7Jkhrg2M9zVgqUcrqqZT/ZF97174SCEJzAt6n9RGGvr
M9sPOPOIO2D5/tu1oOz1dCQQmATj2r5NYAMOu/jVlvB0OpsCrsFwrTWGHWfssR4z
3uIxcaVb4XgtxCtY9o+C9nJiLGqoENWQS7ScuAx6GTHjn4dwL9OZBMjb/vGGFKQp
dtikMRCaNAkJ8XNl/s8ND+rLzXuPF2KIqkZZz/Nwm02lZq/0OPu0ysBGpdN4C4pk
TRiLxnqE0OZg5cnFQFOMAZF4ABh/0x8cM7a1PPBT5MnTvuH1YrLAuvL5daReU5u1
LlxlFd9rSq8SVn8pBLgKk8RlMkqduDm1HusABnFlzBJMJ0Jy2Ol1X3fPK/8wHq6e
4NedNaQbnx1U5pB2mGIPutkBdVkjK7dKvlDXgYi1sunf5Ake+vej3zJ7u4UfWeIJ
lHJgjnPHdGtZ74RU4/ckp5ba+JHXJ15XAxFKk9XRiOjf+9ciQ4dLRF/JfiSRG2Yc
9NZi38w8M3wC2P7U3dh4
=nH67
-----END PGP SIGNATURE-----
Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC DT updates from Olof Johansson:
"Most of this branch consists of updates, additions and general churn
of the device tree source files in the kernel (arch/arm/boot/dts).
Besides that, there are a few things to point out:
- Lots of platform conversion on OMAP2+, with removal of old board
files for various platforms.
- Final conversion of a bunch of ux500 (ST-Ericsson) platforms as
well
- Some updates to pinctrl and other subsystems. Most of these are
for DT-enablement of the various platforms and acks have been
collected"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (385 commits)
ARM: dts: bcm11351: Use GIC/IRQ defines for sdio interrupts
ARM: dts: bcm: Add missing UARTs for bcm11351 (bcm281xx)
ARM: dts: bcm281xx: Add card detect GPIO
ARM: dts: rename ARCH_BCM to ARCH_BCM_MOBILE (dt)
ARM: bcm281xx: Add device node for the GPIO controller
ARM: mvebu: Add Netgear ReadyNAS 104 board
ARM: tegra: fix Tegra114 IOMMU register address
ARM: kirkwood: add support for OpenBlocks A7 platform
ARM: dts: omap4-panda: add DPI pinmuxing
ARM: dts: AM33xx: Add RNG node
ARM: dts: AM33XX: Add hwspinlock node
ARM: dts: OMAP5: Add hwspinlock node
ARM: dts: OMAP4: Add hwspinlock node
ARM: dts: use 'status' property for PCIe nodes
ARM: dts: sirf: add missed address-cells and size-cells for prima2 I2C
ARM: dts: sirf: add missed cell, cs and dma channel for SPI nodes
ARM: dts: sirf: add missed graphics2d iobg in atlas6 dts
ARM: dts: sirf: add missed chhifbg node in prima2 and atlas6 dts
ARM: dts: sirf: add missed memcontrol-monitor node in prima2 and atlas6 dts
ARM: mvebu: Add the core-divider clock to Armada 370/XP
...
Add imx6sl support into imx_init_revision_from_anatop(), so that it can
be used to initialize cpu type and revision on imx6sl.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The imx6sl iomuxc syscon is compatible to imx6q, so let's add
compatible string 'fsl,imx6q-iomuxc-gpr' for imx6sl iomuxc syscon node.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
add a pinctrl for ECSPI1. This pinctrl can be used in the imx6sl-evk board.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Enable USB function for OTG 1 and OTG 2 at mx6sololite evk.
Besides, fix the wrong interrupt number for OTG2 and host 1.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add the dma property for all the uart.
Note: Add the dma property does not mean we enable the dma for this
uart.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
In order to enable the DMA for some uart port in imx6sl, we add the
"fsl,imx6q-uart" to the uart's compatible property.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add the #dma-cells property for all the sdma in all the imx platforms.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>