Commit Graph

2052 Commits

Author SHA1 Message Date
Dinh Nguyen
8a53fb2bce clk: sunxi: make use of of_clk_parent_fill helper function
Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: "Emilio López" <emilio@elopez.com.ar>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:59:05 -07:00
Dinh Nguyen
0b4e7f0842 clk: st: make use of of_clk_parent_fill helper function
Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Tested-by Gabriel Fernandez <gabriel.fernandez@st.com>
Cc: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:59:03 -07:00
Dinh Nguyen
5f23eff7af clk: keystone: make use of of_clk_parent_fill helper function
Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:59:01 -07:00
Dinh Nguyen
f0557fbe13 clk: at91: make use of of_clk_parent_fill helper function
Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:58:59 -07:00
James Liao
75ce0cdb62 clk: mediatek: Add MT8173 MMPLL change rate support
MT8173 MMPLL frequency settings are different from common PLLs.
It needs different post divider settings for some ranges of frequency.
This patch add support for MT8173 MMPLL frequency setting by adding
div-rate table to lookup suitable post divider setting under a
specified frequency.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:58:57 -07:00
James Liao
196de71a9d clk: mediatek: Fix calculation of PLL rate settings
Avoid u32 overflow when calculate post divider setting, and
increase the max post divider setting from 3 (/8) to 4 (/16).

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:58:54 -07:00
James Liao
b3be457e58 clk: mediatek: Fix PLL registers setting flow
Write postdiv and pcw settings at the same time for PLLs if postdiv
and pcw settings are on the same register.

This is need by PLLs such as MT8173 MMPLL and ARM*PLL.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:58:52 -07:00
Stephen Boyd
9783c0d985 clk: Allow providers to configure min/max rates
clk providers are using the consumer APIs to set min/max rates on
the clock they're providing. To encourage clk providers to move
away from the consumer APIs, add a provider API to set the
min/max rate of a clock. The assumption is that this is done
before the clock can be requested via clk_get() and that the
clock rate is already within the boundaries of the min/max that's
configured.

Tested-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:58:50 -07:00
Axel Lin
5c757456c1 clk: twl6040: Convert to use devm_clk_register
Use devm_clk_register() to simplify the code by removing
twl6040_clk_remove().

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:58:48 -07:00
Axel Lin
264e3b75de clk: s2mps11: Simplify s2mps11_clk_probe unwind paths
The devm_clk_unregister() in .probe error case is not necessary as it will
be automatically called when probe fails.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:58:46 -07:00
Geert Uytterhoeven
5a1cfafaea clk: shmobile: Remove unneeded #include <linux/clkdev.h>
The CCF implementations for the various shmobile SoCs don't use clkdev
functionality, hence drop the inclusion of <linux/clkdev.h>.

Add the missing #include <linux/slab.h>, which was included implicitly
through <asm/clkdev.h> before.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:58:44 -07:00
Stephen Boyd
14cc4e9578 clk: ti: Force pointer to be __iomem
Add __force here so that sparse doesn't complain about us playing
tricks with __iomem.

Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:58:41 -07:00
Stephen Boyd
76642eb4cb clk: ti: clk-3xxx: Remove unused structures
Sparse complains about these structures missing static, but they
also don't look to be used. Remove them.

drivers/clk/ti/clk-3xxx.c:74:30: warning: symbol 'clkhwops_omap3430es2_ssi_wait' was not declared. Should it be static?
drivers/clk/ti/clk-3xxx.c:157:30: warning: symbol 'clkhwops_omap3430es2_hsotgusb_wait' was not declared. Should it be static?

Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:58:39 -07:00
Stephen Boyd
3fe6d69742 clk: ti: Mark ti_clk_features static
This variable isn't exported outside of this file so mark it
static. Silences the following sparse warning:

drivers/clk/ti/clk.c:36:24: warning: symbol 'ti_clk_features' was not declared. Should it be static?

Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:58:37 -07:00
Stephen Boyd
f645f72d87 clk: ti: Check kzalloc() for failures
smatch reports a failure to check kzalloc() here:

drivers/clk/ti/clk.c:232
omap2_clk_provider_init() error: potential null dereference 'io'.
(kzalloc returns null)

Check for an allocation failure and return -ENOMEM.

Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:58:35 -07:00
Stephen Boyd
4d34105620 Merge branch 'for-4.2/ti-clk-move' of https://github.com/t-kristo/linux-pm into clk-next
From Tero Kristo:
  "This pull request contains the TI clock driver set to move the
   clock implementations under clock driver. Some small portions of
   the clock driver code still remain under mach-omap2 after this,
   it should be decided whether this code is now obsolete and should
   be deleted or should someone try to fix it."

Slight merge conflicts with determine_rate prototype changes.
2015-07-28 11:58:26 -07:00
Axel Lin
e306479ac2 clk: h8300: Fix signness bug
of_clk_get_parent_count() may return negative error code, so num_parents
needs to be int rather than unsigned int.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:53:20 -07:00
Stephen Boyd
d7a304e9d0 clk: qcom: Set CLK_SET_RATE_PARENT on ce1 clocks
The other ce clocks have the flag set, but ce1 doesn't, so
clk_set_rate() doesn't propagate up the tree to the ce1_src_clk.
Set the flag as this is supported.

Reported-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Tested-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Fixes: 0282465320 ("clk: qcom: Add APQ8084 Global Clock Controller support")
Fixes: d33faa9ead ("clk: qcom: Add support for MSM8974's global clock controller (GCC)")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:51:40 -07:00
Stephen Boyd
c5e857a46a clk: gpio: Unlock mutex on error path
We don't unlock the mutex if we fail to allocate the parent names
array. Unlock it and return an error in this case as well.

Reported-by: kbuild test robot <fengguang.wu@intel.com>
Acked-by: Julia Lawall <julia.lawall@lip6.fr>
Cc: Sergej Sawazki <ce3a@gmx.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:51:39 -07:00
Stephen Boyd
006cb8b66e clk: h8300: Use standard Linux I/O accessors
There doesn't seem to be any reason why we can't use the standard
readb()/writeb() accessors here because ctrl_inb() and
ctrl_outb() match the generic implementation of readb() and
writeb() that the h8300 architecture uses. This allows us to test
compile this driver on other architectures besides h8300.

Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:51:38 -07:00
Stephen Boyd
9298f0267c clk: h8300: Drop allocation printk and cleanup sizeof style
We don't need to print an error on allocation failures, drop it.
While we're here, change the sizeof() to be sizeof(*<ptr>) to
make code more future proof.

Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:51:36 -07:00
Stephen Boyd
19aab27308 Merge branch 'clk-determine-rate-struct' into clk-next
* clk-determine-rate-struct:
  clk: fix some determine_rate implementations
  clk: change clk_ops' ->determine_rate() prototype
2015-07-28 11:51:30 -07:00
Boris Brezillon
57d866e606 clk: fix some determine_rate implementations
Some determine_rate implementations are not returning an error
when they failed to adapt the rate according to the rate request.
Fix them so that they return an error instead of silently
returning 0.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Jonathan Corbet <corbet@lwn.net>
CC: Tony Lindgren <tony@atomide.com>
CC: Ralf Baechle <ralf@linux-mips.org>
CC: "Emilio López" <emilio@elopez.com.ar>
CC: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Tero Kristo <t-kristo@ti.com>
CC: Peter De Schrijver <pdeschrijver@nvidia.com>
CC: Prashant Gaikwad <pgaikwad@nvidia.com>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Thierry Reding <thierry.reding@gmail.com>
CC: Alexandre Courbot <gnurou@gmail.com>
CC: linux-doc@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-omap@vger.kernel.org
CC: linux-mips@linux-mips.org
CC: linux-tegra@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-27 18:13:32 -07:00
Boris Brezillon
0817b62cc0 clk: change clk_ops' ->determine_rate() prototype
Clock rates are stored in an unsigned long field, but ->determine_rate()
(which returns a rounded rate from a requested one) returns a long
value (errors are reported using negative error codes), which can lead
to long overflow if the clock rate exceed 2Ghz.

Change ->determine_rate() prototype to return 0 or an error code, and pass
a pointer to a clk_rate_request structure containing the expected target
rate and the rate constraints imposed by clk users.

The clk_rate_request structure might be extended in the future to contain
other kind of constraints like the rounding policy, the maximum clock
inaccuracy or other things that are not yet supported by the CCF
(power consumption constraints ?).

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Jonathan Corbet <corbet@lwn.net>
CC: Tony Lindgren <tony@atomide.com>
CC: Ralf Baechle <ralf@linux-mips.org>
CC: "Emilio López" <emilio@elopez.com.ar>
CC: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
CC: Peter De Schrijver <pdeschrijver@nvidia.com>
CC: Prashant Gaikwad <pgaikwad@nvidia.com>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Thierry Reding <thierry.reding@gmail.com>
CC: Alexandre Courbot <gnurou@gmail.com>
CC: linux-doc@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-omap@vger.kernel.org
CC: linux-mips@linux-mips.org
CC: linux-tegra@vger.kernel.org
[sboyd@codeaurora.org: Fix parent dereference problem in
__clk_determine_rate()]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Romain Perier <romain.perier@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate
clocks without parents or a rate determining op]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-27 18:12:01 -07:00
Stephen Boyd
86665d2897 clk: st: Fix error paths and allocation style
The error paths in this file leak memory and mappings and test
for pointers being valid after dereferencing them. Fix these
problems and properly free resources on errors. Fix some
stylistic things too like using sizeof(*ptr) and fitting more
code on a single line. Note that we don't unregister clocks here.
That needs a clk_composite_unregister() API that we don't have
right now.

Acked-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Cc: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-13 17:12:31 -07:00
Stephen Boyd
f04b8b48d3 Merge branch 'clk-fixes' into clk-next
* clk-fixes:
  drivers: clk: st: Incorrect register offset used for lock_status
2015-07-07 17:20:07 -07:00
Stephen Boyd
2573a02aa5 clk: Move clk_provider_list to scope of function using it
The list isn't used after of_clk_init() is called, so we don't
need to keep an empty list around after init. Put the list on the
stack.

Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-07 17:20:05 -07:00
Stephen Boyd
2e3b19f137 clk: Check for allocation errors in of_clk_init()
Dan Carpenter reports that we don't check the allocation here for
failure. Add a failure check and free any previously allocated
providers from the clk_provider_list.

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-07 17:20:03 -07:00
Stephen Boyd
ca7d07a22a Merge branch 'clk-rk3368' into clk-next
* clk-rk3368:
  clk: rockchip: add rk3368 clock controller
  clk: rockchip: add missing include guards
  clk: rockchip: add dt-binding header for rk3368
  dt-bindings: add documentation of rk3668 clock controller
  clk: rockchip: define the inverters of rk3066/rk3188 and rk3288
  clk: rockchip: fix issues in the mmc-phase clock
  clk: rockchip: add support for phase inverters
  clk: rockchip: add COMPOSITE_NOGATE_DIVTBL variant
  clk: rockchip: protect register macros against multipart values
  clk: rockchip: fix faulty vip parent name on rk3288
  clk: rockchip: rk3288: add CLK_SET_RATE_PARENT to sclk_mac
2015-07-07 17:20:00 -07:00
Georgi Djakov
d4f76de374 clk: qcom: Add support for SR2 PLLs
Add support for SR2 type pll operations. SR2 is optimized for Time Interval
Error (TIE) or absolute jitter.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-07 17:19:58 -07:00
Stephen Boyd
a8a8db4799 clk: at91: Silence warnings and cleanup __init/extern usage
Remove useless ifdefs around function prototypes to silence the
following sparse warnings when the configs aren't enabled.

drivers/clk/at91/clk-h32mx.c:95:13: warning: symbol
'of_sama5d4_clk_h32mx_setup' was not declared. Should it be
static?
drivers/clk/at91/clk-utmi.c:159:13: warning: symbol
'of_at91sam9x5_clk_utmi_setup' was not declared. Should it be
static?

Plus, using __init and extern in function prototypes doesn't do
anything, so just drop it throughout this file.

Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-07 17:19:31 -07:00
Pankaj Dev
56551da925 drivers: clk: st: Incorrect register offset used for lock_status
Incorrect register offset used for sthi407 clockgenC

Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Fixes: 51306d56ba ("clk: st: STiH407: Support for clockgenC0")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-07 16:05:08 -07:00
Georgi Djakov
adb11a40a3 clk: qcom: Constify the parent names arrays
Make const both the array and the strings, so they can be
moved to .rodata section.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 17:20:59 -07:00
Matthias Brugger
78e50c6def clk: xgene: Delete duplicated name field
X-Gene clocks implement it's name in the clock private struct.
This is a duplication of the name field. We can delete the field
and rely on the common implementation to retrieve the name.

Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 17:20:57 -07:00
Sergej Sawazki
bb68a4f1e5 clk: Rename clk-gpio-gate.c to clk-gpio.c
The file clk-gpio-gate.c does not only contain the gate clock, but also
the mux clock. Rename the file to clk-gpio.c.

Cc: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Sergej Sawazki <ce3a@gmx.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 17:20:55 -07:00
Sergej Sawazki
80eeb1f0f7 clk: add gpio controlled clock multiplexer
Add a common clock driver for basic gpio controlled clock multiplexers.
This driver can be used for devices like 5V41068A or 831721I from IDT
or for discrete multiplexer circuits. The 'select' pin selects one of
two parent clocks.

Cc: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Sergej Sawazki <ce3a@gmx.de>
[sboyd@codeaurora.org: Fix error paths to free memory and do it
in the correct order]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 17:20:52 -07:00
Sergej Sawazki
281cbb0076 clk: gpio-gate: Stay silent on EPROBE_DEFER
Do not output an error message if requesting gpio failes with EPROBE_DEFER.

Cc: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Sergej Sawazki <ce3a@gmx.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:55:07 -07:00
Sergej Sawazki
e21b08e2f3 clk: gpio-gate: Include export.h instead of module.h
Include export.h for EXPORT_SYMBOL_GPL, no need to include module.h.

Cc: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Sergej Sawazki <ce3a@gmx.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:55:06 -07:00
Stephen Boyd
f75073fabd Merge branch 'clk-fixes' into clk-next
* clk-fixes:
  clk: mediatek: mt8173: Fix enabling of critical clocks
  drivers: clk: st: Fix mux bit-setting for Cortex A9 clocks
  drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocks
  drivers: clk: st: Fix flexgen lock init
  drivers: clk: st: Fix FSYN channel values
  drivers: clk: st: Remove unused code
  clk: qcom: Use parent rate when set rate to pixel RCG clock
  clk: at91: do not leak resources
  clk: stm32: Fix out-by-one error path in the index lookup
  clk: iproc: fix bit manipulation arithmetic
  clk: iproc: fix memory leak from clock name
2015-07-06 15:54:58 -07:00
Sascha Hauer
7b2a4635b8 clk: mediatek: mt8173: Fix enabling of critical clocks
On the MT8173 the clocks are provided by different units. To enable
the critical clocks we must be sure that all parent clocks are already
registered, otherwise the parents of the critical clocks end up being
unused and get disabled later. To find a place where all parents are
registered we try each time after we've registered some clocks if
all known providers are present now and only then we enable the critical
clocks

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
[sboyd@codeaurora.org: Marked function and data __init]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:54:13 -07:00
Heiko Stuebner
3536c97a52 clk: rockchip: add rk3368 clock controller
Describe the clock tree and software resets of the rk3368 ARM64 SoC

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:09:22 -07:00
Heiko Stuebner
4534b1113e clk: rockchip: define the inverters of rk3066/rk3188 and rk3288
Both soc series' have inverters on the hsadc and camera interface clock
paths. So define them using the newly added inverter type.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:07:40 -07:00
Heiko Stuebner
7c494ad058 clk: rockchip: fix issues in the mmc-phase clock
The review for the new inverter clock type uncovered some issues (missing
headers and name handling) that are also present in the mmc-phase clock
type, I got (to much) inspiration from. Fix these there too.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:07:38 -07:00
Heiko Stuebner
8a76f443a9 clk: rockchip: add support for phase inverters
Most Rockchip socs have optional phase inverters connected to some
clocks that move the clock-phase by 180 degrees.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[sboyd@codeaurora.org: Dropped lazy part of commit text]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:04:40 -07:00
Heiko Stuebner
6f08507253 clk: rockchip: add COMPOSITE_NOGATE_DIVTBL variant
A clock branch consisting of a mux and divider with non-standard
divider values.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:03:25 -07:00
Heiko Stuebner
2d7884a7d0 clk: rockchip: protect register macros against multipart values
The macros calculate the correct offset from the id in the parameter.
If this parameter does not consist of a single number, the calculation
will return wrong registers in the best case or create unaligned accesses
in the worst case. So protect the calculations against such values.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:03:24 -07:00
Heiko Stuebner
101762976b clk: rockchip: fix faulty vip parent name on rk3288
The video input processor (vip) was called camera interface (cif) on
older socs which seems to have resulted in a copy'n'paste error when
creating the rk3288 camera clocks.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:03:23 -07:00
Heiko Stuebner
4791eb61db clk: rockchip: rk3288: add CLK_SET_RATE_PARENT to sclk_mac
The dwmac ethernet controller on the rk3288 supports phys connected
via rgmii and rmii. With rgmii phys it is expected that the mac clock
is provided externally while with rmii phys the clock can be external
but also generated from the plls. In the later case it of course needs
be at 50MHz, which gets set from the dwmac_rk driver.
As most devices use a rgmii phy it never surfaced so far that the mac
clk mux, doesn't go up one lever to the pll clock in the rmii case with
internal clock generation, as it is missing the CLK_SET_RATE_PARENT flag,
and thus will not set the correct frequency in most cases.

Fixes: b9e4ba5416 ("clk: rockchip: add clock controller for rk3288")
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:03:23 -07:00
Gabriel Fernandez
3be6d8ce63 drivers: clk: st: Fix mux bit-setting for Cortex A9 clocks
This patch fixes the mux bit-setting for ClockgenA9.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Fixes: 13e6f2da1d ("clk: st: STiH407: Support for A9 MUX Clocks")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 12:25:42 -07:00
Pankaj Dev
18fee4538f drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocks
Add the CLK_GET_RATE_NOCACHE flag to all the clocks with recalc ops,
so that they reflect Hw rate after CPS wake-up when a clk_get_rate()
is called

Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 12:25:40 -07:00