Commit Graph

36 Commits

Author SHA1 Message Date
Vinod Koul
8a0cb2360d ASoC: Intel: Skylake: Add support for LPMode
For D0i3, we need to tell DSP to run the pipelines in LP mode. This
information is kept in topology and passed to driver as an attribute
for pipe.

So add a new tuple for lpmode and program the pipe based on value set.

Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-03 11:14:22 -06:00
Dharageswari R
5e8f0ee46d ASoC: Intel: Skylake: Update to use instance ids generated
Post bind parameters of KPB module contains the instance id's of
neighbouring modules in the sink path

Now that module instance ids are generated dynamically we need to update
these parameters as well, so use the table created and update the ids

Signed-off-by: Dharageswari R <dharageswari.r@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-24 19:26:25 +01:00
Dharageswari R
700a9a63f9 ASoC: Intel: Skylake: Add module instance id generation APIs
Driver needs to send unique module instance id to firmware while
creating the module and uses this id to communicate with DSP for setting
parameters while audio use case is ongoing.

But, we have upper bound of instance ID. The current IDs are coming from
topology but it doesn't know the upper bound and can't assign unique
id's subject to upper bounds as we can create a big graph but not all
parts running at same time.

This patch adds a 128bit unique id management routines which are built
on top of ffz() for faster implementation. Unfortunately ffz() works on
32bits values, so additional code is added on top of ffz() to create a
128bit unique id.

Signed-off-by: Dharageswari R <dharageswari.r@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-24 19:26:24 +01:00
Jeeja KP
0b6d76bbd5 ASoC: Intel: Skylake: Fix DMA control config size
DMA control IPC structure wrong config array length,
So corrected the size

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-09-01 21:27:41 +01:00
Vinod Koul
b7c505554c ASoC: Intel: Skylake: Move modules query to runtime
Since we are moving DSP init to later, at the topology load the
module info is not available.

So set the module id to -1 at init and query at first module
initialization.

Signed-off-by: Senthilnathan Veppur <senthilnathanx.veppur@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-08-08 11:54:59 +01:00
Mark Brown
44d624622e Merge remote-tracking branch 'asoc/topic/intel' into asoc-next 2016-07-24 22:07:22 +01:00
Dharageswari R
0d68210400 ASoC: Intel: Skylake: Fix to use the actual size for TLV control
DSP expects the actual length of parameters that is set through
TLV to be passed in large config set, so pass the actual size
received in tlv_control_set() instead of max size.

Signed-off-by: Dharageswari R <dharageswari.r@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-07-08 14:47:04 +02:00
Jeeja KP
f0aa94faa0 ASoC: Intel: Skylake: Set the DSP pipe type
DSP pipe type can be a pass through or it can be processing pipe.
In case of pass through pipe, it is a single pipeline with both
host and link copier in the same pipeline.

Identify the DSP pipe type if it pass through or not. Pass through
pipe is identified by checking if it has both host and link copier
in the same pipeline.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-06-07 14:19:11 +01:00
Jeeja KP
2004432f94 ASoC: Intel: Skylake: Reset DSP pipe when host/link DMA is reset
In case of XRUN recovery PCM prepare will be called. In this case
Host/Link DMAs are reset and reconfigured, hence the corresponding
FE/BE pipe needs to be reset in order to get to a clean state.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-06-07 14:19:11 +01:00
Mark Brown
0ce8428ba9 ASoC: Fixes for v4.6
This is a fairly large collection of fixes but almost all driver
 specific ones, especially to the new Intel drivers which have had a lot
 of recent development.  The one core fix is a change to the debugfs code
 to avoid crashes in some relatively unusual configurations.
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Merge tag 'asoc-fix-v4.6-rc5' into asoc-intel

ASoC: Fixes for v4.6

This is a fairly large collection of fixes but almost all driver
specific ones, especially to the new Intel drivers which have had a lot
of recent development.  The one core fix is a change to the debugfs code
to avoid crashes in some relatively unusual configurations.
2016-05-02 12:02:09 +01:00
Shreyas NC
09305da97c ASoC: Intel: Skylake: Use UUID in binary format
To avoid complex string manipulations with UUID in canonical
form, use UUID in binary format.

Signed-off-by: Shreyas NC <shreyas.nc@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-21 17:09:03 +01:00
Jeeja KP
d643678b9a ASoC: Intel: Skylake: Fix for unloading module only when it is loaded
Module needs to be unloaded only when it is loaded successfully.
To fix this, first correct the module state sequence and set module
state to LOADED if module is loaded successfully.
When unloading the module check if module state is not in UNINIT,
then unload it.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-03-28 10:38:00 +01:00
Dharageswari.R
c115fa5ec0 ASoC: Intel: Skylake: Add MCLK configuration
The SoC has MCLK output which is typically required by codecs.
The MCLK is controlled by DSP FW, so driver can configure that by
sending DMA_CONTROL IPC. The configuration for MCLK is present
in the endpoint blob.

So if block has this configuration, send IPC to DSP for MCLK
configuration. This is done by new function skl_dsp_set_dma_control()
which is invoked by BE prepare.

Signed-off-by: Dharageswari R <dharageswari.r@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-02-08 16:44:17 +00:00
Dharageswari.R
718a42b5ea ASoC: Intel: Skylake: Add skl_tplg_be_get_cpr_module() helper
An I2S port can be connected to multiple BE pipes, get module config
only for the active BE pipe.

This helpers helps to do that and is used in subsequent patches

Signed-off-by: Dharageswari R <dharageswari.r@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-02-08 16:44:17 +00:00
Omair M Abdullah
7d9f29119d ASoC: Intel: Skylake: read params from DSP if module is on
If a module is ON then we should read the module parameters from
DSP rather than driver cached values

Signed-off-by: Omair M Abdullah <omair.m.abdullah@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-12-08 17:57:51 +00:00
Jeeja KP
4ced182763 ASoC: Intel: Skylake: Fix module init data correctly
Module initialization parameter data can be set by
     - INIT_INSTANCE IPC by using the default value
     - SET_PARAMS immediately after INIT_INSTANCE
     - SET_PARAMS data from kcontrol values set
this patch add param type to identify the parameters
has to be sent to DSP.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-12-08 17:57:51 +00:00
Dharageswari R
fd18110f14 ASoC: Intel: Skylake: Add support for Mic Select module
Mic select is a DSP module which is used to select one or many
inputs to form an output. This is useful to select data
selectively from PDM input and hence the name. This module is of
generic module type.

This patch adds support to add and configure Mic select module in
firmware topology.

Signed-off-by: Dharageswari R <dharageswari.r@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-12-08 17:57:51 +00:00
Jeeja KP
b18c458de1 ASoC: Intel: Skylake: Add memory pages to widget data.
A module can require extra memory for processing, like audio
algorithms. The memory for these modules needs to be represented
in base module configuration and passed to DSP on init, so add
the memory pages as a field in widget data

Signed-off-by: Dharageswari.R <dharageswari.r@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-12-08 17:57:51 +00:00
Jeeja KP
abb740033b ASoC: Intel: Skylake: Add support to configure module params
This adds support to configure module parameter during module
initialization or after module init using set module param
required by the DSP firmware sequence.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-12-01 22:17:00 +00:00
Jeeja KP
399b210bef ASoC: Intel: Skylake: Add helper routine to handle Algo parameter
Some DSP modules has user configurable parameters, which are
required by some modules at module initialization.

To configure the module algorithm parameter during initialization
we add helpers here

Signed-off-by: Divya Prakash <divya1.prakash@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-12-01 22:17:00 +00:00
Jeeja KP
9939a9c331 ASoC: Intel: Skylake: Add helper routines to handle module params
Some DSP modules have user configurable parameters. These
parameters are required by modules in the following scenario
	-  during initialization
	-  after initialization using set parameter

This patch adds helper routine to set module parameters using
large config set IPC message and removes params to be passed as
init module routine.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-12-01 22:17:00 +00:00
Hardik T Shah
65aecfa884 ASoC: Intel: Skylake: Add support for module GUIDs
The DSP FW specifies loadable modules using GUIDs so add support to
specify the GUIDs from topology

Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com>
Signed-off-by: Omair M Abdullah <omair.m.abdullah@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-11-16 10:08:09 +00:00
Hardik T Shah
04afbbbb1c ASoC: Intel: Skylake: Update the topology interface structure
This patch updates the topology interface structure alignment and
also updates the Sample interleaving defines

Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com>
Signed-off-by: Omair M Abdullah <omair.m.abdullah@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-11-16 10:08:09 +00:00
Hardik T Shah
4cd9899f0d ASoC: Intel: Skylake: Add multiple pin formats
The module pin formats are considered homogeneous, but some
modules can have different pcm formats on different pins, like
reference signal for a module.

This patch add support for configuration of each pin of module
and allows us to specify if pins and homogeneous or heterogeneous

Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com>
Signed-off-by: Omair M Abdullah <omair.m.abdullah@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-11-16 10:08:09 +00:00
Jeeja KP
ce1b5551a0 ASoC: Intel: Skylake: use module_pin info for unbind
in_pin and out_pin list for a module has the information about
the module that are bound together. So we can directly look at
pin information of module for binding and unbind.

As a result the preinitialized dapm_path_last we had is removed
and code and memory optimzed.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-11-16 10:08:09 +00:00
Jeeja KP
4f7457089d ASoC: Intel: Skylake: Fix support for multiple pins in a module
For supporting multiple dynamic pins, module state check is
incorrect. In case of unbind, module state need to be changed to
uninit if all pins in the module is is unbind state.
To handle module state correctly add pin state and use pin
state check to set module state correctly.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-11-16 10:08:09 +00:00
Jeeja KP
4e10996ba8 ASoC: Intel: Skylake: Add support to disable module notifications
Each FW modules can report underrun/overrun notification from
all modules. This patch disables underrun/overrun notification after
firmware is loaded.
This will be supportted for debug mode only thru debugfs

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-10-24 01:31:34 +09:00
Jeeja KP
d7b188131c ASoC: Intel: Skylake: Update for ssp node index in copier cfg
DSP firmware has interface change for SSP node index structure.
New FW interface removes the dual_mono field and adds 4 bits for
TDM slot group index. This patch updates the ssp dma to align with
the DSP firmware structure.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-10-24 01:31:34 +09:00
Vinod Koul
3af36706ff ASoC: Intel: Skylake: Add topology core init and handlers
The SKL driver does not code DSP topology in driver. It uses the
newly added ASoC topology core to parse the topology information
(controls, widgets and map) from topology binary.
Each topology element passed private data which contains
information that driver used to identify the module instance
within firmware and send IPCs for that module to DSP firmware
along with parameters.
This patch adds init routine to invoke topology load and callback
for topology creation.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-10-07 16:04:14 +01:00
Vinod Koul
cfb0a87383 ASoC: Intel: Skylake: Add FE and BE hw_params handling
For FE and BE, the PCM parameters come from FE and BE hw_params
values passed. For a FE we convert the FE params to DSP expected
module format and pass to DSP. For a BE we need to find the
gateway settings (i2s/PDM) to be applied. These are queried from
NHLT table and applied.

Further for BE based on direction the settings are applied as
either source or destination parameters.

These helpers here allow the format to be calculated and queried
as per firmware format.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-10-07 15:30:16 +01:00
Vinod Koul
d93f8e550f ASoC: Intel: Skylake: add DSP platform widget event handlers
The Skylake driver topology model tries to model the firmware
rule for pipeline and module creation.
The creation rule is:
 - Create Pipe
 - Add modules to Pipe
 - Connect the modules (bind)
 - Start the pipes

Similarly destroy rule is:
 - Stop the pipe
 - Disconnect it (unbind)
 - Delete the pipe

In driver we use Mixer, as there will always be ONE mixer in a
pipeline to model a pipe. The modules in pipe are modelled as PGA
widgets.  The DAPM sequencing rules (mixer and then PGA) are used
to create the sequence DSP expects as depicted above, and then
widget handlers for PMU and PMD events help in that.

This patch adds widget event handlers for PRE/POST PMU and
PRE/POST PMD event for mixer and pga modules.  These event
handlers invoke pipeline creation, destroy, module creation,
module bind, unbind and pipeline bind unbind

Event handler sequencing is implement to target the DSP FW
sequence expectations to enable path from source to sink pipe for
Playback/Capture.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-10-07 15:30:15 +01:00
Jeeja KP
e4e2d2f452 ASoC: Intel: Skylake: Add pipe and modules handlers
SKL driver needs to instantiate pipelines and modules in the DSP.
The topology in the DSP is modelled as DAPM graph with a PGA
representing a module instance and mixer representing a pipeline
for a group of modules along with the mixer itself.

Here we start adding building block for handling these. We add
resource checks (memory/compute) for pipelines, find the modules
in a pipeline, init modules in a pipe and lastly bind/unbind
modules in a pipe These will be used by pipe event handlers in
subsequent patches

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-10-07 15:30:15 +01:00
Jeeja KP
c9b1e834bc ASoC: Intel: Skylake: Add pipe management helpers
To manage DSP we need to create processing pipeline and on cleanup destroy
them. So we add create and destroy routines for pipelines The pipelines need
to to be executed so we add pipeline run and stop routines
All these send required IPCs to DSP using IPC routines added earlier

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-07 14:26:03 +01:00
Jeeja KP
beb73b266a ASoC: Intel: Skylake: Add DSP module init and binding routines
A module needs to be instantiated and then connected with other modules. On
cleanup we need to disconnect the module.
This is achieved by helpers module init, bind and unbind which are added
here

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-07 14:26:02 +01:00
Hardik T Shah
a0ffe48bb5 ASoC: Intel: Skylake: Add helpers for SRC and converter modules
SRC and converter modules are required to do frequency and channel
conversion in DSP. Both take base module configuration and additional SRC
and converter parameters. The helpers here are added to calculate the values
for these modules

Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-07 14:26:02 +01:00
Jeeja KP
23db472bba ASoC: Intel: Skylake: Add helpers for DSP module configuration
This adds helper functions to calculate parameters required for base module
format and copier module. A generic module is modelled by base module.
Copier module is responsible for getting/sending data to FE (host DMAs) and
BE (link HDA DMA, SSP, PDM)
This also ads module pin management helpers which help in finding pins to
use or freeing them up

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-07 14:26:02 +01:00