3 Commits

Author	SHA1	Message	Date
Mrinmay Sarkar	a05b6d5135	phy: qcom-qmp-pcie: add support for sa8775p ... Add support for dual and four lane PHY found on sa8755p platform. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Link: https://lore.kernel.org/r/1689311319-22054-5-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>	2023-07-18 11:37:10 +05:30
Rohit Agarwal	92bd868f52	phy: qcom-qmp: Add support for SDX65 QMP PCIe PHY ... The PCIe PHY version used in SDX65 is v5.20 which has different register offsets compared to the v5.0x and v4.0x PHYs. So separate register defines are used for init sequence and PHY status. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/1679035114-19879-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>	2023-03-31 19:24:24 +05:30
Dmitry Baryshkov	5fc21d1bd3	phy: qcom-qmp: split allegedly 4.20 and 5.20 TX/RX registers ... Split registers definitions belonging allegedly to 4.20 and 5.20 QMP PHYs. They are used for the PCIe QMP PHYs, which have no good open source reference. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-19-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>	2022-07-07 10:36:00 +05:30