7 Commits

Author	SHA1	Message	Date
Alex Deucher	f47299c55a	drm/radeon/kms: display watermark fixes ... - rs780/880 were using the wrong bandwidth functions - convert r1xx-r4xx to use the same pm sclk/mclk structs as r5xx+ - move bandwidth setup to a common function Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>	2010-03-31 13:02:06 +10:00
Alex Deucher	29fb52ca78	drm/radeon/kms: expose thermal/fan i2c buses ... Look up i2c bus in the power table and expose it. You'll need to load a hwmon driver for any chips on the bus, this patch just exposes the bus. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>	2010-03-31 09:38:06 +10:00
Daniel Vetter	e6990375ef	drm/radeon: include radeon_asic.h in the asic specific files ... In essence this creates a home for all asic specific declarations in radeon_asic.h Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>	2010-03-15 11:27:22 +10:00
Jerome Glisse	51e5fcd353	drm/radeon/kms: force pinning buffer into visible VRAM ... This patch properly set visible VRAM and enforce any pinned buffer to be into visible VRAM. We might later add a flag to release this constraint for some newer hw more clever than previous. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>	2010-02-25 11:32:36 +10:00
Jerome Glisse	d594e46ace	drm/radeon/kms: simplify memory controller setup V2 ... Get rid of _location and use _start/_end also simplify the computation of vram_start|end & gtt_start|end. For R1XX-R2XX we place VRAM at the same address of PCI aperture, those GPU shouldn't have much memory and seems to behave better when setup that way. For R3XX and newer we place VRAM at 0. For R6XX-R7XX AGP we place VRAM before or after AGP aperture this might limit to limit the VRAM size but it's very unlikely. For IGP we don't change the VRAM placement. Tested on (compiz,quake3,suspend/resume): PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710 AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730 IGP:RS480(RPB*),RS690,RS780(RPB*),RS880 RPB: resume previously broken V2 correct commit message to reflect more accurately the bug and move VRAM placement to 0 for most of the GPU to avoid limiting VRAM. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>	2010-02-18 14:49:35 +10:00
Dave Airlie	8256856568	drm/radeon/kms: set gart pages to invalid on unbind and point to dummy page ... this uses a new entrypoint to invalidate gart entries instead of using 0. Changed to rather than pointing to 0 address point empty entry to dummy page. This might help to avoid hard lockup if for some wrong reasons GPU try to access unmapped GART entry. I'm not 100% sure this is going to work, we probably need to allocate a dummy page and point all the GTT entries at it similiar to what AGP does. but we can test this first I suppose. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>	2010-02-11 19:11:32 +10:00
Alex Deucher	bcc1c2a1d2	drm/radeon/kms: add initial Evergreen support (Radeon HD 5xxx) ... This adds initial Evergreen KMS support, it doesn't include any acceleration features or interrupt handling yet. Major changes are DCE4 handling for PLLs for the > 2 crtcs. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>	2010-02-09 09:44:02 +10:00