Add basic support for Hitex LPC4350 Evaluation Board. Board
features a LPC4350 Soc, 8 MB SDRAM, 8 MB SPI Flash, USB and
Ethernet.
More information can be found on:
http://www.hitex.com/index.php?id=3212
Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@gmail.com>
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Adds basic support for Embedded Artists' LPC4357 Developer's Kit. Board
features a LPC4357 Soc, 32 MB SDRAM, 128 MB NAND Flash, 16 MB SPI
Flash, USB and Ethernet.
More information can be found on:
http://www.embeddedartists.com/products/kits/lpc4357_kit.php
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
NXP LPC18xx/43xx SoCs are very similar devices and should be able to
share a common base (lpc18xx.dtsi). Diffences between the devices are
put in a dtsi which is specific to that device.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- A series adding support for the Compulab CM-A510
- Add alias for mdio on Armada 38x
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlVV6S0ACgkQCwYYjhRyO9W1tQCghag9/kiZ0qMJSesLBLwG7tcE
yrcAniOoTLzP6cMF+jqtuTrXwoke13JN
=OfeD
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt-4.2' of git://git.infradead.org/linux-mvebu into next/dt
Merge "mvebu dt changes for v4.2 (part #1)" from Gregory CLEMENT:
- A series adding support for the Compulab CM-A510
- Add alias for mdio on Armada 38x
* tag 'mvebu-dt-4.2' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: add alias for mdio on Armada 38x
ARM: dts: dove: Add Compulab SBC-A510 to Makefile
ARM: dts: dove: Add proper support for Compulab CM-A510/SBC-A510
ARM: dts: dove: Remove Compulab CM-A510 from Makefile
ARM: dts: dove: Add internal i2c multiplexer node
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVVGaiAAoJEFGvii+H/Hdh+EgP/3TFK863t7j9r4UdN76dPogx
GUvaT0U1H6/zs3P9B0/L4FVVdkIhEXZ7NvkiEjGuMySpSoAAouWclaW40FQUysK4
Pr9A0Qssp0QjjIwBpT/cRWyCmTpP00qbYsDRlKWtDmMu4A134UCUTXY5008+S++2
EqVyP28hpkImAvPEt2jj14kFep/HroxVPvsD7/vWM0SP5BY3zXxHl5wSD/6XzmEa
/jJonhhNWVd+/Vkgu331360vEx6zvC66GhIqFLHlSz7dUI4cw008c4NtxcYjFUVl
0Jv9YXyxD3GC52S1cZ0MGrWaMXC9LBOq4/5THU/rU+7n3rrkIl/Wrj4zvyKy6IUo
E/XRzZ0EBRooSR+z/ptZ1QBZouhWRRi5iN8Ql+AqHhUg9QV03wXtauijpkRgKRnO
+eiPeuMvHnWzfWLrfHamQTgHAJdfD8o0+nBx/0mvy76JidamIsbYoRB1NSixKNEz
lZXeQoKQ7H+2Ojky+QQArBFnxH1z1OAga2lKh1MXaHs6mvNzHL1W1btcg66sIjFV
FJHqJjZgPgbelG+fqvYtegfOQKVAGVMDhnGUUeVA22bTPgHvdaLCCTiaCXdpsNC9
cuM0yykWZL0NcZiGXtWSs/2rA7Fw25TJkZ23i1lye15nNeyFLoEZIE1UbtcxylPt
edoYW47mgIS0Xdoi/wim
=KpAt
-----END PGP SIGNATURE-----
Merge tag 'rpi-dt-for-armsoc-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi into next/dt
Merge "RaspberryPi Device Tree changes due for v4.2" from Lee Jones:
* tag 'rpi-dt-for-armsoc-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi:
ARM: bcm2835: dt: Use 0x4 prefix for DMA bus addresses to SDRAM.
ARM: bcm2835: dt: Add the mailbox to the device tree
ARM: bcm2835: dt: Fix i2c0 node name
ARM: bcm2835: dt: Use pinctrl header
ARM: bcm2835: dt: Add header file for pinctrl constants
ARM: bcm2835: dt: Add root properties for Raspberry Pi
ARM: bcm2835: dt: Add vendor prefix for Raspberry Pi
The Ux500 like other Cortex-A9 SoC's has a Snoop Control
Unit (SCU) and a Watchdog in the same address range as
the local timers. Add these to the SoC device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Enable DMA for HSUSB on r8a7790 and r8a7791 SoCs
* Configure the HOME key as wake-up source on kzm9g board
* Use generic names for device nodes on SH Mobile SoCs and boards
* Add "nor-jedec" compatible value to SH Mobile boards
* Add IRQC clock to r8a73a4, r8a779* SoCs
* Remove MSIOF address from r8a7790 and r8a7791 SoCs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVU/RhAAoJENfPZGlqN0++yMMP/1gRmFjcDdkM9uZclxU7MAo2
eMAQPn1a/ziWIck5cLrCQhk+xZg5FqFhTrzq0oRVa3p6Dq7HOLki3eugp30OjQ/F
c8J2QeYRHDwpVNvSfu/h4YEiKIVURKYFQTn9bSx6B4AefD70+vkRNyZLfDFP/oO/
w/NwkNcyDCHGSlltUddTAggf+XNwWd2S/+KEqFpdeFXUWR/7X3GTzwqji2iyG8Ft
tAJOe6xveAv0WyXCVXs7sf6/LXyyfpzI5jQpmIN3tv4yuUbmIhiihSW1zEFKggQl
+Wa9YQhixdYBRQEDLkCP2qGxwg4q+/58/RHvN3S0eQUrf3/dsnjIdnoLxuEMBpIi
xKqtnO02FNzjcc7XNitaE5hzdNLikVCg8zs48yo4nvBYaWOnsUFXQ5jgkhl/eiqa
q3FsFrk44/1QnHoHmICasfwxJ1TOv5R/FpDxJrBUAFtTfPkRGl/hgpUi0g9d1CNk
XAw/+gUfyJZTHz9la7okwFYb83lHSGHwH3maaRHJ7WCN/T7hGd6BQNZgj3vGkCVq
A9p1t97Pu1+3Yd2IjaRItSlTUW0nvy+uZY58aXluBhM3WKR6ZkaiQC/GWy1Z8fAH
49K1fKR32cu0+zBrD9exaW/Xsc8YKb71C3F/nCwsLOlkLpqJ3Bm2Ys4pe8jHsOJ5
pmSWiLDmIFkccDY2qA6t
=OdRc
-----END PGP SIGNATURE-----
Merge tag 'renesas-dt-for-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Merge "Renesas ARM Based SoC DT Updates for v4.2" from Simon Horman:
* Enable DMA for HSUSB on r8a7790 and r8a7791 SoCs
* Configure the HOME key as wake-up source on kzm9g board
* Use generic names for device nodes on SH Mobile SoCs and boards
* Add "nor-jedec" compatible value to SH Mobile boards
* Add IRQC clock to r8a73a4, r8a779* SoCs
* Remove MSIOF address from r8a7790 and r8a7791 SoCs
* tag 'renesas-dt-for-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (31 commits)
ARM: shmobile: r8a7791: Enable DMA for HSUSB
ARM: shmobile: r8a7791: add USB-DMAC device nodes
ARM: shmobile: r8a7790: Enable DMA for HSUSB
ARM: shmobile: r8a7790: add USB-DMAC device nodes
ARM: shmobile: kzm9g dts: Configure the HOME key as wake-up source
ARM: shmobile: koelsch dts: Use generic names for device nodes
ARM: shmobile: lager dts: Use generic names for device nodes
ARM: shmobile: bockw dts: Use generic names for device nodes
ARM: shmobile: koelsch dts: Add "nor-jedec" compatible value
ARM: shmobile: bockw dts: Add "nor-jedec" compatible value
ARM: shmobile: lager dts: Add "nor-jedec" compatible value
ARM: shmobile: bockw-reference dts: Add "nor-jedec" compatible value
ARM: shmobile: henninger dts: Add "nor-jedec" compatible value
ARM: shmobile: armadillo800eva dts: Use generic names for device nodes
ARM: shmobile: marzen dts: Use generic names for device nodes
ARM: shmobile: kzm9d dts: Use generic names for device nodes
ARM: shmobile: ape6evm dts: Use generic names for device nodes
ARM: shmobile: sh73a0 dtsi: Use generic names for device nodes
ARM: shmobile: r8a7791 dtsi: Use generic names for device nodes
ARM: shmobile: r8a7790 dtsi: Use generic names for device nodes
...
- clocks descriptions (pxa27x, pxa3xx)
- timer descriptions (pxa27x, pxa3xx)
- IPs which are embedded on the SoC
- keypad
- udc (USB client)
- power I2C
These are amongst the building blocks for future pxa device-tree board
description.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVUm1JAAoJEAP2et0duMsSxJUQAIXpLJWnPYKPj24AQYwQki4T
PlhDxYUPSOFJy2JVBnk+wwuPH+7qFwwZ+6q/y/7l6O5U4okHzoQCL/CySCBHJiFJ
poLFqPfbZn+6WSR9px47v4nDniaoOsBLwb/Z/B7AOC9FgqNBX9lwpkCQeb5ybRk2
vfqUZjbyq5/bxhPSCKh29wclqrO88xaowK9fClXFhgUNjmL/5YEBi3qYKErtGZyi
udAh2rnljIWzgzTfpIs/ovtjgPV8Qy7s0iw0YJLcak3Pl9lmyUA/iQLgK21RfX7J
nQr3AFHkmKs+r496TYrbA5+PLd00LSBs6FIFRHJBvqSEiecqm/hYzY/T+g8KAziG
p7bG9B7DCpM8wvScqGnzaLI0g0wYZVm7XGeSjMnFxQON1Zyk2tg/e7fXSTt/B7/W
mOgmU9bb981zfS6yocrXZaeq48ApnO7dVoWN9orwIOfjSaQA1N4eNeD9VwVNQIxT
sPlmrH4+DH5Ov/coQtGS467W2+leJTtAEYv4SHqqXIj74Je9tiEc9UVVeJhJauxd
LMfPkl4/P9WaBVFqICAGbBE+F597hOIG9CPec0gKVg8c4wq3Ji2fHEy+wZXBSSuC
t06d5yt082ffrPY0qqZSGal7vUUzDMav+HUmGU/34QpQbUE6rr7sflOPpSLIK1Qe
sURcpwaKhGmNqhnOBxm3
=GbmD
-----END PGP SIGNATURE-----
Merge tag 'pxa-dt-4.2' of https://github.com/rjarzmik/linux into next/dt
Merge "device-tree pxa update" from Robert Jarzmik:
- clocks descriptions (pxa27x, pxa3xx)
- timer descriptions (pxa27x, pxa3xx)
- IPs which are embedded on the SoC
- keypad
- udc (USB client)
- power I2C
These are amongst the building blocks for future pxa device-tree board
description.
* tag 'pxa-dt-4.2' of https://github.com/rjarzmik/linux:
ARM: dts: pxa: add pxa-timer to pxa27x and pxa3xx
ARM: dts: pxa: add pxa27x-keypad to pxa27x
ARM: dts: pxa: add pxa27x-udc to pxa27x
ARM: dts: pxa: add clocks
ARM: dts: pxa: add pwri2c to pxa device-tree
Merge "Device Tree changes" from Florian Fainelli:
New devices:
- Felix adds support for the Buffalo WXR-1900DHP and adds the USB led on Buffalo
WZR-1750DHP
- Rafal adds support for the SmartRG SR400ac, Asus RT-AC68U and RT-AC56U
New peripheral support:
- Brian adds Device Tree nodes for the Broadcom NAND controller found on
BCM7xxx, BCM63138 and Cygnus SoCs
- Brian adds Device Tree nodes for the SATA AHCI and PHY controller found on
BCM7xxx
- I add the Device Tree nodes and bindings documents for bringing-up secondary
CPUs and timer/syscon-reboot on BCM63138
* tag 'arm-soc/for-4.2/dts' of http://github.com/broadcom/stblinux:
ARM: BCM5301X: Add DT for Asus RT-AC56U
ARM: BCM5301X: Add DT for Asus RT-AC68U
ARM: dts: BCM63xx: Add timer and syscon-reboot nodes
dt-bindings: Add documentation for the BCM63138 timer and syscon-reboot
ARM: dts: brcmstb: add nodes for SATA controller and PHY
ARM: dts: cygnus: Enable NAND support for Cygnus
ARM: bcm63138: add NAND DT support
ARM: bcm7445: add NAND to DTS
ARM: BCM5301X: Add DT for SmartRG SR400ac
ARM: BCM5301X: Add DT for Buffalo WXR-1900DHP
ARM: BCM5301X: Add USB LED for Buffalo WZR-1750DHP
ARM: dts: BCM63xx: Add SMP nodes and required properties
Documentation: DT: Document SMP DT nodes and properties for BCM63138
ARM: dts: BCM63xx: Add PMB busses nodes
Documentation: DT: Add Broadcom BCM63138 PMB binding
This patch fixes a regression where serial is enabled by the first
(board) DTSI, then disabled by the second (SoC) file. To enable
serial and keep it enabled, we need to include the file which enables
it last.
Reported-by: LAVA [via Peter Griffin <peter.griffin@linaro.org>]
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical addresses to bus
addresses. These bus addresses determine the caching behavior in the
VC's L1/L2 (note: separate from the ARM's L1/L2) according to the top
2 bits. The bits in the bus address mean:
From the VideoCore processor:
0x0... L1 and L2 cache allocating and coherent
0x4... L1 non-allocating, but coherent. L2 allocating and coherent
0x8... L1 non-allocating, but coherent. L2 non-allocating, but coherent
0xc... SDRAM alias. Cache is bypassed. Not L1 or L2 allocating or coherent
From the GPU peripherals (note: all peripherals bypass the L1
cache. The ARM will see this view once through the VC MMU):
0x0... Do not use
0x4... L1 non-allocating, and incoherent. L2 allocating and coherent.
0x8... L1 non-allocating, and incoherent. L2 non-allocating, but coherent
0xc... SDRAM alias. Cache is bypassed. Not L1 or L2 allocating or coherent
The 2835 firmware always configures the MMU to turn ARM physical
addresses with 0x0 top bits to 0x4, meaning present in L2 but
incoherent with L1. However, any bus addresses we were generating in
the kernel to be passed to a device had 0x0 bits. That would be a
reserved (possibly totally incoherent) value if sent to a GPU
peripheral like USB, or L1 allocating if sent to the VC (like a
firmware property request). By setting dma-ranges, all of the devices
below it get a dev->dma_pfn_offset, so that dma_alloc_coherent() and
friends return addresses with 0x4 bits and avoid cache incoherency.
This matches the behavior in the downstream 2708 kernel (see
BUS_OFFSET in arch/arm/mach-bcm2708/include/mach/memory.h).
Signed-off-by: Eric Anholt <eric@anholt.net>
Tested-by: Noralf Trønnes <noralf@tronnes.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Device tree node names should contain the node's reg property address value.
The i2c0 node was apparently forgotten in commit 25b2f1bd0b (ARM: bcm2835:
node name unit address cleanup).
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This patch converts all bcm2835 dts and dtsi files to use the pinctrl
header file.
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Add a "brcm,bcm6328-timer" and "syscon-reboot" nodes to allow the
generic syscon-reboot driver to reset a BCM63138 SoC.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Enable NAND support for Broadcom Cygnus SoC
Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Update bcm63138.dtsi with the following:
- enable-method for both CPU nodes
- brcm,bcm63138-bootlut node
- resets properties to point to the correct PMB controller to release
the secondary CPU from reset
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add the two BCM63138 PMB busses nodes found on this System-on-a-Chip as
described in their corresponding binding document.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Contains a couple of fixes and additions to device tree files. The most
notable change is a fix for a misapplied patch that was only exposed by
a recent change in the regulator subsystem that caused USB to break on
Tegra124 recently.
Other than that there are a more or less random assortment of additions
to enable various features on a couple of boards.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJVU1KlAAoJEN0jrNd/PrOhMKgP/jOIwMgc+RC6uud66kAb8oQ8
itcNWwhHFv/7fiCeIbCq8qsp51DHPxhDuWeBP/FIhfExJcDD+P2pfrKpXlI1bCrz
jgOHfgauKSzSEIQcFU3uYWMr7qR7euVtaBsB0v16HtSpTcRnNKv/hvlvYPFYVl5D
NvWyYB7hjHrbAur97vrJJ9e+RKZGfKo0bOqikyQ5ftbKcASa9HNY6JAeOrV+Delw
LPA3P98eXcwVSBgdHw++iOqVZNbs+kNXnRV8dcjgWXdXsI2LQGgZrbEb5WS7/29j
0Jaz9dwMJ4EC9yZaiT2sOXxdOjnSJ5MC1lE/CuCjE8Kz4fsq8sCudTp90fi6eFxT
QcrneJ7d7LzjprDpKdK8E/YgPHjp5pOVuBvqtJ/RtjHFCVlaZ5OvZMdNX0zqY7SU
T+3kYNXTcFhJHyQOtajGOSixVyqOEVddjjCvSyH+QXB6MmkH37Jcg6A7J/t6VrX3
eK0VQMqkB10hZj8pzP/kN4dpiw3YQXxszF9luQ10AjHZvnADyGKesaDXYEjGD3FL
ux1hjQHTAuRauID4XUzu2vfNQqYbLb0papQ+6RnlgBn4P+jS/45xTZEchUU5Xoj/
SGTgxqNM4TjCDGf6iYzpbKi/A/T46w5Xt05r2g57qkQPcITVJK6MHtbEmPjWR1jP
3CJ0qItO/dSTi61vV0XW
=8R5I
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-4.2-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt
Merge "ARM: tegra: Devicetree changes for v4.2-rc1" from Thierry Reding:
Contains a couple of fixes and additions to device tree files. The most
notable change is a fix for a misapplied patch that was only exposed by
a recent change in the regulator subsystem that caused USB to break on
Tegra124 recently.
Other than that there are a more or less random assortment of additions
to enable various features on a couple of boards.
* tag 'tegra-for-4.2-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Fix hda2codec_2x clock and reset names
ARM: tegra: Add Tegra30 HDA support
ARM: tegra: Cardhu device-tree comment spelling fix
ARM: tegra: venice2: Set min-/max-microvolt for VDD_LED supply
ARM: tegra: venice2: Mark eMMC as non-removable
ARM: tegra: jetson-tk1: Enable HDA support
ARM: tegra: Add missing HDMI +5V regulator
ARM: tegra: cardhu: Add power and volume keys
ARM: tegra: Correct which USB controller has the UTMI pad registers
- Add a DTS node for the A9 SCU
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJVU1L4AAoJEBmUBAuBoyj05zEP/02UJVcqCHT2P/z/1XJnIwed
hZgO0Oej4ZEc+futAIx6IeMEkgNoIDZX1rdijiQe3Uv2QK8niC7R8yOjwcZrM8jZ
ws/jyKWpCBsV0J+lzZevxa3DpxMHPmcx0W9gAqYpikrwgbXt0Dyy62CQkp+XKZ5d
mluxSEbkSlORddzD8eQbM1yuVlFGg9RAzdwaeZk4j6x+vq2Zk+jEwq5EKLBIiO/U
kGwu/mEryiWl+lzqV7Nlagt4uLASsT5ZxEjr4zUx9ddDTJo4mqStqONdDPMTdf9h
0qzHrWa9mMhI7RLoOWBuvTEcvEVPSRNhVfo6cY8ZnQcZ/V5tj4sG3jAPUFXkFSMd
iZW3mud5P45ugbKiumR5R7ve3t6yxhvNqWH9FZqfnlPPNXtCaUqBGB772A0Xr2Hz
mRPu2Vl9cjmGdrWQHqF5sViPdm52E8Het3/HO0ccsx4aoH+jhgGKeqmiK779EKTA
lA0NPBrL5PRzjNacNwnR7RxtLpcISf5CbsV0ojiIDtB8x11TCg1Zct+ogeE03luT
YpTNuOgTEg7Gy4oa6LPPXahUS+6RffHmASjlt15xaWx/x5MaCXTyk3H4JtSumDiL
blFzdQmNUcO2YpggSgyS0UzRFyqYJIRPq7lHKMJz5NMfaHVzu4VzoDKmJVo4zG2T
BftEOP7ROh5wq1HkWJs3
=23ne
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_for_v4.2_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt
Merge "SoCFPGA update for v4.2 part 2" from Dinh Nguyen:
- Add a DTS node for the A9 SCU
* tag 'socfpga_dts_for_v4.2_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: socfpga: dts: add the a9-scu node
the Cortex-A12 HW PMU on the rk3288 and the tsadc on some more rk3288
boards, as well as some usb properties and marking the radxarock pmic
as system-power-controller.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABCAAGBQJVU2Y0AAoJEPOmecmc0R2BXCQIAIV6yQP+f6ACIPJEVRk8yD3W
YyJ/mXgrSD/RaaFYnEO3PPVC8TibVI6a7SIoa4y92g0LW7VYn7UQY1wzlrt3rzR5
rY71uB/Ew0yQBJe1rsw+Sn7couG9U/g3YB/guJmFfO2rS9xn6wICKcLxYNaIp9sb
WOwzNlpWwpejCdYLzxw9BP0qxFRE2ZlxoF96VB+j5s+IcnvKGGo3twYqtyN5YEjK
dB7Bbnq6n9VWgYMkuijxyQ00skUNUb+7ciHSO4pksPtuSa4K+GsqjkTu37nkBPmn
t53c+M93WuI5hplFRM3UwXKH6ELqhEuq0GN4dPzRD5VBWcWYOMXl8AmhfOlR6cU=
=39uK
-----END PGP SIGNATURE-----
Merge tag 'v4.2-rockchip-dts1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Merge "ARM: rockchip: dts changes for 4.2" from Heiko Stuebner:
Some misc improvements defining additional supply regulators, enabling
the Cortex-A12 HW PMU on the rk3288 and the tsadc on some more rk3288
boards, as well as some usb properties and marking the radxarock pmic
as system-power-controller.
* tag 'v4.2-rockchip-dts1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: add system-power-controller to act8846 on radxarock
ARM: dts: rockchip: add properties for dwc2 usb otg controller
ARM: dts: rockchip: enable tsadc on rk3288 boards
ARM: dts: rockchip: add act8846 supplies on rk3288-firefly
ARM: dts: rockchip: Specify VMMC and VQMMC on rk3288-evb
ARM: dts: rockchip: Enable Cortex-A12 HW PMU events on rk3288
Define CPU topology, connect that with CoreSight blocks,
add sensor information to DT boards.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVUyYjAAoJEEEQszewGV1zZGIP/jiHCMNtMgFOjPxfDI3lwvpl
p9b6YUeEVknUk0yObYmHcqt6vg71zhiAUndJV5P/dN7jN2n8Cr7JIs52uVkpGuhh
2CkQgXTMlCpR6LnFWgUT1OMRKg6EBP/JFOJdHbFq+HD6QsBAD9oKULt9VPValtrM
2VkktKaetXHJND7nwdC8MTKe+4oOs/YpOy+yKVYb/iWNMrTCPCFLBI5BRKLUaPdd
A0EtGARSkCGU9QZkGvuyhI4UY1KWi4JjKfD9GNmka3FTq8y5MGjdgn1VEw9whZcW
wtJFiTuZ9CM+Jm+WyJx6bdZwlIjMKMrGaaMDeRnoh9UQml4+DDyJJWgbeAT8rhQS
XP5NG4I9X1RSqen1XUikPPBl2V5u1baIfaP4noLxuu4yVYfUTuC76T+k+FCAPxQu
Ymw/RWWmPwodXrN7OBlpPW7rTUk269LVCrWpIFQkhkDnrmYH4Rs8CAv4boDd3yj1
P4ew49Cu0Y489vR8DBndbUlXjL/ssD2Uh4DZp8fzURTfnu2P6Yzk9Q98At87uqqp
Hz/OfLBcnX5N7myu+fMkKBf7Ju3Nz/Ho1hA/q8rsPXfazvQcYm5gL9vI1wljRn0B
b8++F+scoiM0iEY/OpjWX8box9w+gE7lq/14QqRVpRmCNyC1JtlQT7AoXCSDMkic
EJn4vhHoLu4Bhl9/ypND
=+QE+
-----END PGP SIGNATURE-----
Merge tag 'ux500-v4.2-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/dt
Merge "Ux500 Device Tree changes for the v4.2 series" form Linus Walleij:
Define CPU topology, connect that with CoreSight blocks,
add sensor information to DT boards.
* tag 'ux500-v4.2-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: add the sensors to the STUIB board
ARM: ux500: assign the sensor trigger IRQs
ARM: ux500: fix lsm303dlh magnetometer compat string
ARM: ux500: add CoreSight blocks to DTS file
ARM: ux500: define CPU topology
This adds the device tree data for the LIS331DL and the
AK8974 magnetometer to the STUIB board device tree include
file.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The ST sensors on the Ux500 boards were not utilizing the IRQs
for data ready sample triggers. Enable this by assigning the
right GPIO lines and interrupt lines (when the GPIO lines are
used for IRQs) to the accelerometer, gyro and magnetometer
sensors.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The magnetometer found on the Ux500 TVK and Snowball boards
is a LSM303DLH not a LSM303DLM, small differences but still
different. Put in the right compatible strings and things start
working smoothly.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This registers all the CoreSight blocks on the DB8500 SoC:
each core has a PTM (v1.0, r1p0-00rel0) connected, both connected
to a funnel (DK-TM908-r0p1-00rel0) which in turn connects to a
replicator (DM-TM909-r0p1-00rel0). The replicator has two outputs,
port 0 to a TPIU interface and port 1 to an ETB
(DK-TM907-r0p3-00rel0). The CoreSight blocks are all clocked by
the APEATCLK from the PRCMU and their AHB interconnect is clocked
from a separate clock called APETRACECLK.
The SoC also has a CTI/CTM block which can be added later as we
have upstream support in the CoreSight subsystem.
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This driver is used to enable System Configuration Register controlled
External, CTI (Core Sight), PMU (Performance Management), and PL310 L2
Cache IRQs prior to use.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
This driver is used to enable System Configuration Register controlled
External, CTI (Core Sight), PMU (Performance Management), and PL310 L2
Cache IRQs prior to use.
Here we are enabling PMU IRQs on both channels.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
This is ARM's generic Performance Monitoring Unit.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
This driver is used to enable System Configuration Register controlled
External, CTI (Core Sight), PMU (Performance Management), and PL310 L2
Cache IRQs prior to use.
Here we are enabling PMU IRQs on both channels.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
This is ARM's generic Performance Monitoring Unit.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
All the infrastructure is now in place for ST's PWM controller. This
patch takes the final step and enables the IP on the 2020 Rev-E
development platform.
Signed-off-by: Ajit Pal Singh <ajitpal.singh@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Supply top level nodes for the STiH416 based development boards.
The Pinctrl configuration has already been applied, so the only
missing piece of the DT puzzle is for a board's DTB to enable
the nodes.
Signed-off-by: Ajit Pal Singh <ajitpal.singh@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Supply the Pinctrl configuration to enable PWM{0,1} lines on STiH416
based development boards.
Signed-off-by: Ajit Pal Singh <ajitpal.singh@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Supply top level nodes for the STiH407 based development boards.
The Pinctrl configuration has already been applied, so the only
missing piece of the DT puzzle is for a board's DTB to enable
the nodes.
Signed-off-by: Ajit Pal Singh <ajitpal.singh@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Each pxa has an embedded OS Timers IP. The kernel cannot work without a
valid clocksource, and this adds the OS Timers to the pxa device-tree
description.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
