xHCI 1.0 specification specifies that CErr does not apply to Isoch endpoints
and shall be set to '0' for Isoch endpoints.
Signed-off-by: Andiry Xu <andiry.xu@amd.com>
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
xHCI 1.0 specification indicates that software should set Average TRB Length
to '8' for control endpoints.
Signed-off-by: Andiry Xu <andiry.xu@amd.com>
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Setup Stage Transfer Type field is added to indicate the presence and the
direction of the Data Stage TD, and determines the direction of the Status
Stage TD so the wLength length field should be ignored by the xHC.
Signed-off-by: Andiry Xu <andiry.xu@amd.com>
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Implement good battery algorithm defined in the battery charging V1.2 spec
for detecting different charging ports. USB hardware is put into low power
mode when connected to a dedicated charging port. vbus_draw and set_power
methods are implemented for determining the allowed current from Host in
different states (un-configured/suspend/configured).
The charger block is implemented using vendor specific registers and the
PHY used in MSM8960(28nm PHY) different from older targets like MSM8x60
and MSM7x30(45nm PHY). The PHY vendor and product id registers are not
implemented in the above chipsets. Hence PHY type is passed via platform
data.
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
HSUSB core clock is derived from daytona fabric clock and for
HSUSB operational require minimum core clock at 55MHz. Since, HSUSB
cannot tolerate daytona fabric clock change in the middle of HSUSB
operational, vote for maximum Daytona fabric clock
while usb is operational
Signed-off-by: Anji jonnala <anjir@codeaurora.org>
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This patch adds support for the UHCI part of the GRLIB GRUSBHC controller
found on some LEON/GRLIB SoCs.
The UHCI HCD previously only supported controllers connected over PCI.
This patch adds support for the first non-PCI UHCI HC. I have tried to
replicate the solution used in ehci-hcd.c.
Tested on GR-LEON4-ITX board (LEON4/GRLIB with GRUSBHC) and x86 with Intel
UHCI HC.
Signed-off-by: Jan Andersson <jan@gaisler.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This patch is part of a series that extend the UHCI HCD to support
non-PCI host controllers.
This patch also extends the uhci_{read,write}* functions to allow accesses
to registers not mapped into PCI I/O space. This extension also includes
the addition of a void __iomem pointer to the uhci structure.
A new Kconfig option is added to signal that the system has a non-PCI HC.
If this Kconfig option is set, uhci-hcd.c will include generic reset functions
for systems that do not make use of keyboard and mouse legacy support. PCI
controllers will still always use the reset functions from pci-quirks
This patch is followed by a patch that adds bus glue for the first non-PCI
UHCI HC.
Signed-off-by: Jan Andersson <jan@gaisler.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This patch is part of a series that extend the UHCI HCD to support
non-PCI controllers.
This patch replaces in{b,w,l} and out{b,wl} with calls to local inline
functions. This is done so that the register access functions can be
extended to support register areas not mapped in PCI I/O space.
Signed-off-by: Jan Andersson <jan@gaisler.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This patch is part of a series that extend the UHCI HCD to support
non-PCI controllers.
This patch moves PCI specific functions to uhci-pci.c and includes
this file in uhci-hcd.c. It also renames the function uhci_init to
uhci_pci_init.
uhci_init/uhci_pci_init is modified so that the port-detection logic
is kept in a new separate function uhci_count_ports() in uhci-hcd.c.
Signed-off-by: Jan Andersson <jan@gaisler.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This patch is part of a series that extend the UHCI HCD to support
non-PCI host controllers.
This patch fixes the following warnings from checkpatch:
ERROR: switch and case should be at the same indent
+ switch (to_pci_dev(uhci_dev(uhci))->vendor) {
+ default:
[...]
+ case PCI_VENDOR_ID_GENESYS:
[...]
+ case PCI_VENDOR_ID_INTEL:
WARNING: static char array declaration should probably be static const char
+ static char bad_Asus_board[] = "A7V8X";
WARNING: Use DEFINE_PCI_DEVICE_TABLE for struct pci_device_id
+static const struct pci_device_id uhci_pci_ids[] = { {
Signed-off-by: Jan Andersson <jan@gaisler.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This patch is part of a series that extend the UHCI HCD to support
non-PCI controllers.
This patch changes calls to uhci_reset_hc, uhci_check_and_reset_hc,
configure_hc, resume_detect_interrupts_are_broken and
global_suspend_mode_is_broken so that they are made through pointers
in the uhci hcd struct. This will allow these functions to be replaced
with bus/arch specific functions.
Signed-off-by: Jan Andersson <jan@gaisler.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This patch is part of a series that extend the UHCI HCD to support
non-PCI host controllers.
uhci-hub.c contained two PCI vendor checks for silicon quirks. Move
these checks into uhci-hcd.c and use bits in uhci_hcd structure to
mark that we need to use the quirks.
This patch is followed by other patches that will remove PCI
dependencies from uhci-hcd.c as well.
Signed-off-by: Jan Andersson <jan@gaisler.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Though USB controller works without this most of the time, an issue was faced
where USB was configured as printer device and it was dropping first
packet(64 bytes) in full speed mode due to DATA PID mismatch.
The problem gets resolved once unused endpoints are configured as bulk.
As per P1020 RM (Table17-31, bits 19-18, bits 3-2) "When only one endpoint
(RX or TX, but not both) of an endpoint pair is used, the unused endpoint
should be configured as a bulk type endpoint." So according to the RM,
this patch is initializing TX and RX endpoints as bulk type
Signed-off-by: Suchit Lepcha <Suchit.Lepcha@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This patch fixes the checkpatch errors ans warnings listed below:
ERROR: do not use assignment in if condition
WARNING: line over 80 characters
WARNING: braces {} are not necessary for single statement blocks
WARNING: space prohibited between function name and open parenthesis '('
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Remove a stray 'return 0' at the top of the suspend callback,
and move au1xxx_stop_ehc() out of the ehci spinlock since it takes
some time to complete.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Commit 3dacdf11 "usb: factor out state_string() on otg drivers"
broke building musb drivers since there is already another
otg_state_string() function in musb drivers, but with different
prototype. Fix musb drivers to use common otg_state_string(), too.
Also provide a nop for otg_state_string() if CONFIG_USB_OTG_UTILS
is not defined.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This patch adds support for the GRLIB GRUSBHC EHCI controller from
Aeroflex Gaisler. The controller is typically found on LEON/GRLIB
SoCs.
Tested on GR-LEON4-ITX with with little endian interface and on
LEON3 system on GR-PCI-XC5V development board for big endian
controller.
Signed-off-by: Jan Andersson <jan@gaisler.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
The two first HC capability registers (CAPLENGTH and HCIVERSION)
are defined as one 8-bit and one 16-bit register. Most HC
implementations have selected to treat these registers as part
of a 32-bit register, giving the same layout for both big and
small endian systems.
This patch adds a new quirk, big_endian_capbase, to support
controllers with big endian register interfaces that treat
HCIVERSION and CAPLENGTH as individual registers.
Signed-off-by: Jan Andersson <jan@gaisler.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
The current code is clearing in_lpm flag after enabling the IRQ.
If IRQ comes immediately before in_lpm flag is set, it thinks that
hardware is in low power mode and disables the IRQ. Fix this by
clearing in_lpm flag before enabling the IRQ.
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Some of the simulators may cache the ep0 maxpacket size to zero
if the ep0 dQh is not setup before enabling the pullup. Hence
Setup ep0 and initialize the dQh fields once while registering the
gadget(before enabling the pullup).
HSUSB Chipidea link controller spec says ep0 is enabled always
in the HW. Hence disabling and enabling the ep0 as a part of
reset interrupt is unneccesary.
Remove the disable/enable ep0 logic from reset interrupt handling.
Signed-off-by: Anji jonnala <anjir@codeaurora.org>
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
The current code queue the control OUT data request to ep0in instead of
ep0out. Check ep0_dir and use the correct control endpoint.
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
The OUT endpoints are stored in 0 - hw_ep_max/2 and IN endpoints are
stored from hw_ep_max/2 - hw_ep_max in ci13xxx_ep array. Retrieve
the IN endpoint correctly while processing endpoint feature requests.
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Ask for vbus_draw regulator before registering tranceiver to disallow possible
race between registration and set_power/etc.
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Added several new devices to ldusb and excluded them from the HID driver.
Signed-off-by: Michael Hund <mhund@ld-didactic.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
As pointed out by Arnd Bergmann, in include/linux/usb/ehci_def.h, struct
ehci_caps is defined with __attribute__((packed)) for no good reason,
and this triggers undefined behaviour when using ARM's readl() on
pointers to elements of this structure:
http://lkml.kernel.org/r/201102021700.20683.arnd@arndb.de
The same problem exists with the other two structures in ehci_def.h too,
so remove the __attribute__((packed)) from all of them.
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
The reset value of the uSOF cycle period is incorrect. Set it to
60,000 bits. Without this, several commercial USB flash memory
devices and hubs fail to work properly.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
The UCTL clock initialization will cause the ehci and ohci blocks to
become inoperable if the clocks are reinitialized.
Check to see if the clocks have already been initialized.
Also use a mutex to protect the clock initialization code so that
there can be no attempt to use the clocks before they are fully
configured.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* 'for-usb-next' of git+ssh://master.kernel.org/pub/scm/linux/kernel/git/sarah/xhci:
xhci 1.0: Set transfer burst last packet count field.
xhci 1.0: Set transfer burst count field.
xhci 1.0: Update TD size field format.
xhci 1.0: Only interrupt on short packet for IN EPs.
xhci: Remove sparse warning about cmd_status.
usbcore: warm reset USB3 port in SS.Inactive state
usbcore: Refine USB3.0 device suspend and resume
xHCI: report USB3.0 portstatus comply with USB3.0 specification
xHCI: Set link state support
xHCI: Clear link state change support
xHCI: warm reset support
usb/ch9: use proper endianess for wBytesPerInterval
xhci: Remove recursive call to xhci_handle_event
xhci: Add an assertion to check for virt_dev=0 bug.
xhci: Add rmb() between reading event validity & event data access.
xhci: Make xHCI driver endian-safe
This patch replaces the code that handles qtds. Intead of directly allocating
chip mem and chip slot, enqueue the transfer in a list of queue heads. Use
a centralized function enqueue_qtds() to prioritize and enqueue transfers.
This removes all of the interrupt context BUG() calls when out of chip
mem or transfer slots. It also makes it possible to efficiently use the
dual-port mem on the chip for double-buffered transfers, which improve
transfer times to/from/between usb sticks by about 40 % on my HW.
With this patch it should also be possible to handle qtd scheduling outside
of the interrupt handler, for significantly improved kernel latency. I have
not implemented this since there are some locking issues which I haven't
had time to look at.
Signed-off-by: Arvid Brodin <arvid.brodin@enea.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This fixes a bug in my previous (2.6.38) patch series which caused
urb->status value to be wrong after unlink (broke usbtest 11, 12).
Signed-off-by: Arvid Brodin <arvid.brodin@enea.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Since we always set the OR flag for each transfer, we can just as well set all
these bits to 1 at init and be done with it. Also, HcBufferStatus can be set
at init as per the ISP1761 datasheet page 47 with no loss of performance.
Signed-off-by: Arvid Brodin <arvid.brodin@enea.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This collects urb enqueue code that was spread out all over the place
into a couple of more readable functions.
Signed-off-by: Arvid Brodin <arvid.brodin@enea.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This removes the "qh is 0" printout. qh == NULL if the urb has
been unlinked, so this condition is normal.
Signed-off-by: Arvid Brodin <arvid.brodin@enea.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
When File Storage gadget receives SET CONFIGURATION request it tries
to cancel all pending transfers. If some request is in progress,
gadget waits for its completion. This commit allows gadget to dequeue
invalid requests in progress left after reset.
Signed-off-by: Anton Tikhomirov <av.tikhomirov@samsung.com>
Reviewed-by: Kyoungil Kim<ki0351.kim@samsung.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
The following should be done for requests after endpoint stall
condition is cleared:
1) 'in progress' request (if any) should be completed since
Tx FIFO was flushed;
2) next request from queue (if any) should be started.
This commit does that.
Additionally set/clear stall condition code is fixed.
Signed-off-by: Anton Tikhomirov <av.tikhomirov@samsung.com>
Reviewed-by: Kyoungil Kim<ki0351.kim@samsung.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
UDC driver does not need to generate reply to host if request is
delivered to gadget. This is gadget's responsibility. This commit
fixes that.
Signed-off-by: Anton Tikhomirov <av.tikhomirov@samsung.com>
Reviewed-by: Kyoungil Kim<ki0351.kim@samsung.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit does the following:
1) clears all pending interrupts before unmasking;
2) clears interrupts as soon as possible to avoid missing
next coming that may occur during handling;
3) removes ineffective interrupt cleaning code.
Signed-off-by: Anton Tikhomirov <av.tikhomirov@samsung.com>
Reviewed-by: Kyoungil Kim<ki0351.kim@samsung.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Slightly reworked and cleaned up driver from Freescale LTIB
for MPC5121E. The driver has been ported to the current kernel,
proc interface "/proc/driver/fsl_usb2_otg" has been replaced by
sysfs interface.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Extend the FSL UDC driver to support MPC5121E DR USB Controller
operation in device mode. Add MPC5121E specific init/uninit
at probe and remove and isolate system interface register accesses
when running on MPC5121E SoC, as these registers are not available
on this platform. This patch relies on previous patch for supporting
big endian registers and descriptors access in the FSL UDC driver.
Additionally support endpoint FIFO status operation by providing
appropriate callback in endpoint ops structure.
Also flush cache for the req buffer used for GetStatus reply.
Without this, the correct reply to an endpoint GetStatus
is written to 'req', but doesn't make it out to the USB bus
since the buffer hasn't been flushed. This would cause the
USBCV Halt Endpoint test to fail (according to changelog in
Freescale LTIB driver code).
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Li Yang <leoli@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
On some SoCs, the USB controller registers and descriptors can be big
or little endian, depending on the version of the chip. In order to be
able to run the same kernel binary on different versions of an SoC, the
BE/LE decision must be made at run time. Provide appropriate register
and descriptor accessors which are configurable at run time using the
configuration flags from fsl_usb2_platform_data data structure.
This is in preparation for adding support for MPC5121E DR USB2 Controller
to the FSL UDC driver.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Li Yang <leoli@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
