sw clockgate was used on uvd6.0.
when uvd is idle, we gate the uvd clock.
when decode, we ungate the uvd clock.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Use the correct define. No functional change as both
defines are equivalent.
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Port the GMC v6 driver over to the new SI headers.
Tested with a Tahiti SI ASIC.
(v2) Fixed a couple of typos (in commented code) and moved
defines to si_enums.h
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This only has the effect of scanning the invisible range twice
since the topdown flag is given anyway.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: JimQu <Jim.Qu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This disables the VRAM manager when a special placement is requested, otherwise
we play ping/pong with the buffers on every command submission.
v2: only check lpfn
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: JimQu <Jim.Qu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1. fix uvd cg status not correct.
2. fix uvd pg can't work on tonga.
3. enable uvd mgcg.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
when uvd is idle, we gate uvd clock.
and uvd is busy, we ungate uvd clock.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add support for the debugfs wave reader.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This changes the gfx v6 driver to use the new AMDGPU style
SI headers. Also fixes a variety of coding style issues, white
space issues, and uses WREG32_FIELD in a few places where
appropriate.
Tested with a Tahiti 0x679A.
v2: Squash in typo fix patch
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add missing gca MMIO registers and defines necessary for the
next patch which re-works a lot of gfx v6 to use the new SI
headers.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This introduces the SI registers in the amdgpu
driver style.
v2: squash duplicates fix
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Replace direct comparisons to NULL i.e.
'x == NULL' with '!x'. As per coding standard.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ravikant B Sharma <ravikant.s2@samsung.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
De-numberify indirect register access for gfx v8.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
De-numberify indirect register access for gfx v7.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This patch is used for virtualization support. In virtualization case,
Tonga SMC should not be started and SMU firmware should not be loaded
if in SRIOV environment. The same operation will be applied on FIJI in
other patch.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Trigger Huang <trigger.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1. partial revert commit 91db308d6e96.
not set uvd bypass mode.
2. enable uvd cg before initialize uvd.
3. set uvd clock to default value 100MHz.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Voltage Controller have been enabled (SMC message)
before ULV enablement.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This patch is used for virtualization support. In virtualization case,
the initialization sequences are not totally the same as
non-Virtualization's. The avfs event manager should be bypassed if in
SRIOV virtualization case. At the same, this patch will also bypass
starting SMC within SRIOV in FIJI, so the SMU firmware loading will be
avoid, which is required in SRIOV.
Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Trigger Huang <trigger.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
KIQ is used for interaction between driver and
CP, and not exposed to outside client, as such it
doesn't need to be handled by GPU scheduler.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Trigger Huang <trigger.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add a new ring type definition for KIQ. KIQ is used for interaction
between driver and CP.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Trigger Huang <trigger.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
UVD clocks are set to be disabled, when not in use.
Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tom StDenis <Tom.StDenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Only for cards that are supported by powerplay.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Powerplay hwmgr already has an implementation, all we need to do is to call it.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
In fence waiting, it never return -EDEADLK yet, so drop this function
here.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
use same module parameter with powercontainment
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This is the initial ZTE VOU display controller DRM/KMS driver. There
are still some features to be added, like overlay plane, scaling, and
more output devices support. But it's already useful with dual CRTCs
and HDMI display working.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJYH++oAAoJEFBXWFqHsHzOlCQIAKLNtBmB2OSChdPRCa7tIG7O
vtjUwze70QtD6vVe+rs0fvc46PM3qrccJI6bcgzveki+vRvFVDlreydmB18g3bMx
cBbsByGnWrNWDtKrwvvRWrkDQwcxnSVX5lMWeIvLrPHeXQVb4nf0F2cn7/zEfIek
G55LHonRD28m66tWb87gaWwisowcaPzA3tAEP4Rifdqg9IQ45He7Po6KZWZU4DQq
M/RltIHQwt/OFxAnDuz18ecf+o0NXuLoMYmoA8EYdOTV3sJ2hiJQFWaL5qmXKl7C
Nzlql70txu9B9H5R4V/6MXS21J0H2uGs2Aig9l9Brz2Vn774IBX09Wi8Fo8G8VU=
=+zjh
-----END PGP SIGNATURE-----
Merge tag 'zxdrm-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into drm-next
ZTE zxdrm driver support for 4.10:
This is the initial ZTE VOU display controller DRM/KMS driver. There
are still some features to be added, like overlay plane, scaling, and
more output devices support. But it's already useful with dual CRTCs
and HDMI display working.
[airlied: use drm_format_plane_cpp instead of legacy api]
* tag 'zxdrm-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
MAINTAINERS: add an entry for ZTE ZX DRM driver
drm: zte: add initial vou drm driver
dt-bindings: add bindings doc for ZTE VOU display controller
Here is the list of fixes that I have for drm/mali-dp. They've been on the mailing
lists for a while and merged into linux-next for a few weeks, but due to holiday and
travel to Linux Plumbers I did not send the pull request earlier. I don't know if
these patches can be pulled into v4.9 still (they will conflict with Ville Syrjälä's
cleanup of DRM_ROTATE series that is already in drm-next), but if you do that would
be great.
* 'for-upstream/mali-dp' of git://linux-arm.org/linux-ld:
drm: mali-dp: Clear CVAL when leaving config mode
drm/arm: mark symbols static where possible
drm: mali-dp: Add support for setting plane's rotation property from userspace.
drm: mali-dp: Don't set DRM_PLANE_COMMIT_ACTIVE_ONLY
drm: mali-dp: Store internal format and n_planes in plane state
drm: mali-dp: Enable alpha blending
drm: mali-dp: Refactor plane initialisation
arm: mali-dp: Extract mode_config cleanup into malidp_fini
drm: mali-dp: Add pitch alignment check for planes
drm: mali-dp: Add pitch alignment check function
drm: mali-dp: Set the drm->irq_enabled flag to match driver's state.
drm: mali-dp: Clear the config_valid flag before using it in wait_event.
- add support for the HDMI I2C master controller, for boards that
can have their DDC pins connected only to the HDMI TX directly.
-----BEGIN PGP SIGNATURE-----
iQI0BAABCAAeBQJX34wqFxxwLnphYmVsQHBlbmd1dHJvbml4LmRlAAoJEFDCiBxw
nmDr7J0QAOhuvrQ03OhQ/WlnvdAfHG8+G7qFT38zzG9klWBhGYWgPNoZyTGCjmOB
pljEo3lAPjc5YIZcPWpDFU4GIE875lE4vKlpnjIHyFJKaAcnZxy3fh7AEdEjlfhd
PdHRpsLNsTxfZbvQnELwPl9qx1+OQjlSUCAQn8kFyyy5ejOWg3lXcZenPr/DWKxs
KpQjV3k/HZ5EbRLxxhMYCm5xgb0bI3oVjWw48xnLfIOY3UFlzaJ1dTmPCaWmA4VZ
7js52FRoeqCcq8OYEcq8Ix/72eNtWW7STJOlMqrB0TbTGKUwK0FEPu7k0xcn2OwK
6quA8s/1WzTxqkBAkhN7UkUlZVonle+V7iAhe0zAE4zNIUttyUhIazPVGPqWRLf2
FQdZC2r0hyRL5SijS/QowbPL75zB8cBQ/l9Et67wH2eSCC/ZijlQoAKtvWE4a5Tt
KuW8YPwGUJpVHiUpur+/tyWLtPgr40IwEfwx52F4HfT+4aY5rmKyHbi3y6nkK3vC
aXl1dtomU8p2tYf1iuXymI5e9gaz5GdEiR30ynIBMBsfgawUJL7bTDG9NFuhaioU
PoHia1zWBOXL8gYrvVT7tU4yeN9onx7LjPS8V8r0BszZ/6Y2hIfvXAX6zO9TLj4Y
kmWBJdCp937y/+DJ25YxA2e67ManONx7XHv5T2aix3w64uKzCZIw
=aAzo
-----END PGP SIGNATURE-----
Merge tag 'dw-hdmi-next-2016-09-19' of git://git.pengutronix.de/git/pza/linux into drm-next
dw-hdmi i2c master controller
- add support for the HDMI I2C master controller, for boards that
can have their DDC pins connected only to the HDMI TX directly.
* tag 'dw-hdmi-next-2016-09-19' of git://git.pengutronix.de/git/pza/linux:
drm: bridge/dw_hdmi: add dw hdmi i2c bus adapter support
drm: dw_hdmi: use of_get_i2c_adapter_by_node interface
- request modeset if plane offsets changed, only the plane base
address can be changed without disabling the plane IDMAC channel.
- cleanup of plane atomic_update
- remove unused ipu_cpmem_set_yuv_planar function
- support YUV 4:4:4, 4:2:2, NV12 and NV16 plane formats
- not only mask interrupts during irq init, also clear them
- remove a legacy check from imx-ldb
- add support to set the CSI downsizing bits
- silence an obnoxious warning during modeset
-----BEGIN PGP SIGNATURE-----
iQI1BAABCAAfBQJYJKqnGBxwaGlsaXBwLnphYmVsQGdtYWlsLmNvbQAKCRBQwogc
cJ5g644rD/0cVFsbTLhXY3wLbntZXeDrWEaR+PCoEcibsscBaomv1wietpkFMTKx
41S0HP8ygc912ptZ1JdgDIrDyDD6lsubpj3wUwOWz5zlbLtEOnF1S+C+kAbdJdyg
8wKNpTz8fxvb7tN+iYwtlDyzrEEHr0OFWtqDruuLi6Ti/bMl5QUVs1j7LBEQksgn
SmlU99xt84NyLYVm3B+BKAOW5LR1Kx1Qq50IBM9bH1dU8vLclAnsElTpeKppDcSL
dvvkYfFQIUNVMn8/9CBrLLaiI76j45YAnvhMPZ+g9g9IMyHqVh4Rsato7Y+u7Z2R
kKbwWmhyPMgTsrnpdvesg+9veJpv4/EDE1JEmpTzet0mmKEoUX6cfZUwF9vjvzGX
LED7fmVXm5gMTMPt4Tw2j5ZzVzflw+zW2g5/8e2otVVhpxC5DHKlnsUJ1fddRzu2
C4bD3CC0zmfN6EZZQT+n2kZSu4wZhd93WhffOSTShvypio1XZQlA2NiWIwSkNQe/
vGGTtWTT1NnV4CxrX4d3SS9IN5JhYlXQAJHNRdutLNyRKJLo6Wa3ilt+wy5jDmh4
uYHkdumGz+modtYv2b4OR9xdmLGt/ylkodlcXvpqmvBoL4RY6oPNRIeFMEOsUwlU
FWajcHZw7MINlKubTZGP/eWxKgfsB7fk0lcqz03nOm2f+IwMGzUy2g==
=uKg2
-----END PGP SIGNATURE-----
Merge tag 'imx-drm-next-2016-11-10' of git://git.pengutronix.de/git/pza/linux into drm-next
imx-drm plane update cleanup, YUV formats
- request modeset if plane offsets changed, only the plane base
address can be changed without disabling the plane IDMAC channel.
- cleanup of plane atomic_update
- remove unused ipu_cpmem_set_yuv_planar function
- support YUV 4:4:4, 4:2:2, NV12 and NV16 plane formats
- not only mask interrupts during irq init, also clear them
- remove a legacy check from imx-ldb
- add support to set the CSI downsizing bits
- silence an obnoxious warning during modeset
* tag 'imx-drm-next-2016-11-10' of git://git.pengutronix.de/git/pza/linux:
gpu: ipu-di: silence videomode logspam
gpu: ipu-v3: add ipu_csi_set_downsize
drm/imx: imx-ldb: remove unnecessary double disable check
gpu: ipu-v3: initially clear all interrupts
drm/imx: ipuv3-plane: add support for YUV 4:2:2 and 4:4:4, NV12, and NV16 formats
gpu: ipu-v3: add YUV 4:4:4 support
gpu: ipu-cpmem: remove unused ipu_cpmem_set_yuv_planar function
drm/imx: ipuv3-plane: let drm_plane_state_to_ubo/vbo handle chroma subsampling other than 4:2:0
drm/imx: ipuv3-plane: merge ipu_plane_atomic_set_base into atomic_update
drm/imx: ipuv3-plane: request modeset if plane offsets changed
- better atomic state debugging from Rob
- fence prep from gustavo
- sumits flushed out his backlog of pending dma-buf/fence patches from
various people
- drm_mm leak debugging plus trying to appease Kconfig (Chris)
- a few misc things all over
* tag 'topic/drm-misc-2016-11-10' of git://anongit.freedesktop.org/drm-intel: (35 commits)
drm: Make DRM_DEBUG_MM depend on STACKTRACE_SUPPORT
drm/i915: Restrict DRM_DEBUG_MM automatic selection
drm: Restrict stackdepot usage to builtin drm.ko
drm/msm: module param to dump state on error irq
drm/msm/mdp5: add atomic_print_state support
drm/atomic: add debugfs file to dump out atomic state
drm/atomic: add new drm_debug bit to dump atomic state
drm: add helpers to go from plane state to drm_rect
drm: add helper for printing to log or seq_file
drm: helper macros to print composite types
reservation: revert "wait only with non-zero timeout specified (v3)" v2
drm/ttm: fix ttm_bo_wait
dma-buf/fence: revert "don't wait when specified timeout is zero" (v2)
dma-buf/fence: make timeout handling in fence_default_wait consistent (v2)
drm/amdgpu: add the interface of waiting multiple fences (v4)
dma-buf: return index of the first signaled fence (v2)
MAINTAINERS: update Sync File Framework files
dma-buf/sw_sync: put fence reference from the fence creation
dma-buf/sw_sync: mark sync_timeline_create() static
drm: Add stackdepot include for DRM_DEBUG_MM
...
- gpu idling rework for s/r (Imre)
- vlv mappable scanout fix
- speed up probing in resume (Lyude)
- dp audio workarounds for gen9 (Dhinakaran)
- more conversion to using dev_priv internally (Ville)
- more gen9+ wm fixes and cleanups (Maarten)
- shrinker cleanup&fixes (Chris)
- reorg plane init code (Ville)
- implement support for multiple timelines (prep work for scheduler)
from Chris and all
- untangle dev->struct_mutex locking as prep for multiple timelines
(Chris)
- refactor bxt phy code and collect it all in intel_dpio_phy.c (Ander)
- another gvt with bugfixes all over from Zhenyu
- piles of lspcon fixes from Imre
- 90/270 rotation fixes (Ville)
- guc log buffer support (Akash+Sagar)
- fbc fixes from Paulo
- untangle rpm vs. tiling-fences/mmaps (Chris)
- fix atomic commit to wait on the right fences (Daniel Stone)
* tag 'drm-intel-next-2016-11-08' of git://anongit.freedesktop.org/git/drm-intel: (181 commits)
drm/i915: Update DRIVER_DATE to 20161108
drm/i915: Mark CPU cache as dirty when used for rendering
drm/i915: Add assert for no pending GPU requests during suspend/resume in LR mode
drm/i915: Make sure engines are idle during GPU idling in LR mode
drm/i915: Avoid early GPU idling due to race with new request
drm/i915: Avoid early GPU idling due to already pending idle work
drm/i915: Limit Valleyview and earlier to only using mappable scanout
drm/i915: Round tile chunks up for constructing partial VMAs
drm/i915: Remove the vma from the object list upon close
drm/i915: Reinit polling before hpd when resuming
drm/i915: Remove redundant reprobe in i915_drm_resume
drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms
drm/i915/dp: BDW cdclk fix for DP audio
drm/i915: Fix pages pin counting around swizzle quirk
drm/i915: Fix test on inputs for vma_compare()
drm/i915/guc: Cache the client mapping
drm/i915: Tidy slab cache allocations
drm/i915: Introduce HAS_64BIT_RELOC
drm/i915: Show the execlist queue in debugfs/i915_engine_info
drm/i915: Unify global_list into global_link
...
0day continues to complain about trying to save a stacktrace for the
users of the drm_mm range allocator. This time, it is that m68k has no
save_stack_trace(), which is apparently guarded by STACKTRACE_SUPPORT.
Make it depend so!
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161109143906.11057-1-chris@chris-wilson.co.uk
I misread the kbuild result thinking that we had missed the include
(which we had for completeness anyway), what kbuild was actually warning
me about was that depot_save_stack was not exported.
Temporarily fix this by only selecting STACKDEPOT iff drm.ko is builtin
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Fixes: 5705670d04 ("drm: Track drm_mm allocators and show leaks on shutdown")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161108131917.6253-2-chris@chris-wilson.co.uk
