Commit Graph

2 Commits

Author SHA1 Message Date
Hirosh Dabui
c284d9fa48 davinci: tnetv107x: fix register indexing for GPIOs numbers > 31
This patch fix a bug in the register indexing for GPIOs numbers >  31
to get the relevant hardware registers of tnetv107x to control the GPIOs.

In the structure tnetv107x_gpio_regs:

struct tnetv107x_gpio_regs {
            u32     idver;
            u32     data_in[3];
            u32     data_out[3];
            u32     direction[3];
            u32     enable[3];
};

The GPIO hardware register addresses of tnetv107x are stored.
The chip implements 3 registers of each entity to serve 96 GPIOs,
each register provides a subset of 32 GPIOs.
The driver provides these macros: gpio_reg_set_bit, gpio_reg_get_bit
and gpio_reg_clear_bit.

The bug implied the use of macros to access the relevant hardware
register e.g. the driver code used the macro like this:
'gpio_reg_clear_bit(&reg->data_out, gpio)'

But it has to be used like this:
'gpio_reg_clear_bit(reg->data_out, gpio)'.

The different results are shown here:
- &reg->data_out + 1 (it will add the full array size of data_out i.e. 12 bytes)
- reg->data_out + 1 (it will increment only the size of data_out i.e. only 4 bytes)

Acked-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Hirosh Dabui <hirosh.dabui@snom.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-02-28 14:53:19 -08:00
Cyril Chemparathy
d92c796247 Davinci: tnetv107x initial gpio support
This patch adds support for the tnetv107x gpio controller.

Key differences between davinci and tnetv107x controllers:
 - register map - davinci's controller is organized into banks of 32 gpios,
   tnetv107x has a single space with arrays of registers for in, out,
   direction, etc.
 - davinci's controller has separate set/clear registers for output, tnetv107x
   has a single direct mapped register.

This patch does not yet add gpio irq support on this controller.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-06-21 12:48:31 -07:00