Commit Graph

914 Commits

Author SHA1 Message Date
Will Deacon
7665d9d2df ARM: proc: add proc info for Cortex-A15MP using classic page tables
Multicore implementations of the Cortex-A15 require bit 6 of the
auxiliary control register to be set in order for cache and TLB
maintenance operations to be broadcast between CPUs.

This patch adds a new proc_info structure for Cortex-A15, which enables
the SMP bit during setup and includes the new HWCAP for integer
division.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-07-07 19:20:52 +01:00
Pawel Moll
15eb169bfe ARM: proc: add Cortex-A5 proc info
This patch adds processor info for ARM Ltd. Cortex A5,
which has SCU initialisation procedure identical to A9.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-07-07 19:20:52 +01:00
Pawel Moll
dc939cd835 ARM: proc: convert v7 proc infos into a common macro
As most of the proc info content is common across all v7
processors, this patch converts existing A9 and generic v7
descriptions into a macro (allowing extra flags in future).

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-07-07 19:20:52 +01:00
Dave Martin
2ba564b90f ARM: mm: tlb-v7: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:12 +01:00
Dave Martin
3b7f39fa9a ARM: mm: tlb-v6: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:12 +01:00
Dave Martin
ca56096367 ARM: mm: tlb-v4wbi: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:12 +01:00
Dave Martin
2284ece2d6 ARM: mm: tlb-v4wb: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:12 +01:00
Dave Martin
f249a6425a ARM: mm: tlb-v4: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:12 +01:00
Dave Martin
d7b84d2438 ARM: mm: tlb-v3: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:11 +01:00
Dave Martin
27eebe4cc9 ARM: mm: tlb-fa: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:11 +01:00
Dave Martin
ab1a746da9 ARM: mm: proc-xscale: Use new generic struct definition macros
Without this patch, xscale_80200_A0_A1 is missing the
icache_flush_all entry, which would result in the wrong functions
being called at run-time.

This patch re-uses xscale_icache_flush_all for
xscale_80200_A0_A1_cache_fns.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:11 +01:00
Dave Martin
c21898f9f0 ARM: mm: proc-xsc3: Use new generic struct definition macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:11 +01:00
Dave Martin
78a8f3c365 ARM: mm: proc-v7: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:11 +01:00
Dave Martin
7b7dc6e888 ARM: mm: proc-v6: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:10 +01:00
Dave Martin
f58d59f6c5 ARM: mm: proc-sa1100: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:10 +01:00
Dave Martin
5973ba5886 ARM: mm: proc-sa110: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:10 +01:00
Dave Martin
a39a32187b ARM: mm: proc-mohawk: Use the new processor struct macros
This patch also defines a suitable flush_icache_all implementation
which would otherwise be missing, resulting in a link failure.
Thanks to Nicolas Pitre for suggesting the code for this.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-07-07 15:31:10 +01:00
Dave Martin
e43b670e24 ARM: mm: proc-feroceon: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-07-07 15:31:10 +01:00
Dave Martin
d6ed10ce39 ARM: mm: proc-fa526: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:09 +01:00
Dave Martin
b4a19f03c4 ARM: mm: proc-arm9tdmi: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:09 +01:00
Dave Martin
b1b9892bcd ARM: mm: proc-arm946: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:09 +01:00
Dave Martin
b375580147 ARM: mm: proc-arm940: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:09 +01:00
Dave Martin
be90da45a9 ARM: mm: proc-arm926: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:09 +01:00
Dave Martin
6c240aec6f ARM: mm: proc-arm925: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:09 +01:00
Dave Martin
f3e7383f2a ARM: mm: proc-arm922: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:08 +01:00
Dave Martin
68f5e1acb5 ARM: mm: proc-arm920: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:08 +01:00
Dave Martin
fd10e2725e ARM: mm: proc-arm7tdmi: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:08 +01:00
Dave Martin
4cc1f0fa06 ARM: mm: proc-arm740: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:08 +01:00
Dave Martin
449870b1de ARM: mm: proc-arm720: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:07 +01:00
Dave Martin
c3be06eb58 ARM: mm: proc-arm6_7: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:07 +01:00
Dave Martin
5c9369bc2e ARM: mm: proc-arm1026: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:07 +01:00
Dave Martin
f2d8cae1d5 ARM: mm: proc-arm1022: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:07 +01:00
Dave Martin
fbaa840730 ARM: mm: proc-arm1020e: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:07 +01:00
Dave Martin
56d916509b ARM: mm: proc-arm1020: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:07 +01:00
Dave Martin
455a01ec30 ARM: mm: cache-v7: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:06 +01:00
Dave Martin
641d8233a6 ARM: mm: cache-v6: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:06 +01:00
Dave Martin
d5b5b2e2f8 ARM: mm: cache-v4wt: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:06 +01:00
Dave Martin
eec95e56e6 ARM: mm: cache-v4wb: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:06 +01:00
Dave Martin
54d4e9ebbc ARM: mm: cache-v4: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:06 +01:00
Dave Martin
9c373968d6 ARM: mm: cache-v3: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:05 +01:00
Dave Martin
9bc7491341 ARM: mm: cache-fa: Use the new processor struct macros
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07 15:31:05 +01:00
Dave Martin
66a625a881 ARM: mm: proc-macros: Add generic proc/cache/tlb struct definition macros
This patch adds some generic macros to reduce boilerplate when
declaring certain common structures in arch/arm/mm/*.S

Thanks to Russell King for outlining what the
define_processor_functions macro could look like.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-07-07 15:30:35 +01:00
Russell King
111b20d013 ARM: pm: ensure ARMv7 CPUs save and restore the TLS register
Ensure that the TLS register is saved and restored over a suspend
cycle, so that userspace programs don't see a corrupted TLS value.

Tested-by: Kevin Hilman <khilman@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-06-24 08:47:09 +01:00
Russell King
7a0ee92b4a ARM: pm: proc-v7: fix missing struct processor pointers for suspend code
Add the missing suspend/resume pointers for the suspend code.  This
is needed when building for multiple CPUs.

Tested-by: Kevin Hilman <khilman@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-06-24 08:47:01 +01:00
Russell King
8f4b8c7613 ARM: initrd: disable initrds outside of memory
We can't cope with initrds outside of memory, so check that the
initrd is within some declared memory to the kernel before using
it.  Otherwise we're likely to OOPS during boot.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-06-11 00:43:21 +01:00
Russell King
a0a54d37b4 Revert "ARM: 6944/1: mm: allow ASID 0 to be allocated to tasks"
This reverts commit 45b95235b0.

Will Deacon reports that:

 In 52af9c6c ("ARM: 6943/1: mm: use TTBR1 instead of reserved context ID")
 I updated the ASID rollover code to use only the kernel page tables
 whilst updating the ASID.

 Unfortunately, the code to restore the user page tables was part of a
 later patch which isn't yet in mainline, so this leaves the code
 quite broken.

We're also in the process of eliminating __ARCH_WANT_INTERRUPTS_ON_CTXSW
from ARM, so lets revert these until we can properly sort out what we're
doing with the context switching.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-06-09 10:13:16 +01:00
Russell King
07989b7ad6 Revert "ARM: 6943/1: mm: use TTBR1 instead of reserved context ID"
This reverts commit 52af9c6cd8.

Will Deacon reports that:

 In 52af9c6c ("ARM: 6943/1: mm: use TTBR1 instead of reserved context ID")
 I updated the ASID rollover code to use only the kernel page tables
 whilst updating the ASID.

 Unfortunately, the code to restore the user page tables was part of a
 later patch which isn't yet in mainline, so this leaves the code
 quite broken.

We're also in the process of eliminating __ARCH_WANT_INTERRUPTS_ON_CTXSW
from ARM, so lets revert these until we can properly sort out what we're
doing with the ARM context switching.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-06-09 10:13:04 +01:00
Rabin Vincent
45f6d7e0e6 ARM: 6951/1: include .bss in memory layout information
The "Virtual memory kernel layout" message at startup already prints
.text and .data.  Print .bss too.

Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-06-06 10:56:10 +01:00
Ben Hutchings
9a819d8ac8 ARM: 6948/1: Fix .size directives for __arm{7,9}tdmi_proc_info
gas used to accept (and ignore?) .size directives which referred to
undefined symbols, as these do.  In binutils 2.21 these are treated
as fatal errors.

The issue in proc-arm7tdmi.S was also fixed independently by Peter
Chubb.

Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-06-06 10:56:10 +01:00
Russell King
239df0fd5e Merge branches 'devel', 'devel-stable' and 'fixes' into for-linus 2011-05-27 22:59:57 +01:00