Commit Graph

43180 Commits

Author SHA1 Message Date
Kai-Heng Feng
6c24a85d23 drm/amdgpu: add new device to use atpx quirk
The affected system (0x0813) is pretty similar to another one (0x0812),
it also needs to use ATPX power control.

Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-02-19 14:19:46 -05:00
Rex Zhu
9ac870c777 drm/amd/pp: Restore power profile mode in auto dpm level on Vega10
As auto power profile mode still not support on vega10, so
just restore default profile mode in auto dpm level.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:46 -05:00
Rex Zhu
8d81bce71d drm/amdgpu: Get/set dgpu power cap via hwmon API
v2: change power unit to microWatt

Adust power limit through power1_cap
Get min/max power limit through power1_cap_min/power1_cap_max

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:45 -05:00
Rex Zhu
6ab8555e04 drm/amd/pp: Expose set/get_power_limit for DGPU
User can change power limit between
[0, 1] * max power limit.

Set power limit to 0, restore to max power limit.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:44 -05:00
Matthias Kaehlcke
71d0a89812 amdgpu/dc: Fix enum mismatch in calls to program_color_matrix()
The driver passes GRAPHICS_CSC_ADJUST_TYPE_SW of type enum
graphics_csc_adjust_type to program_color_matrix(), however the function
expects a parameter of type enum grph_color_adjust_option. Supposedly
the intention was to pass GRPH_COLOR_MATRIX_SW, which has the same value
as GRAPHICS_CSC_ADJUST_TYPE_SW, so the mismatch didn't cause any trouble.

Pass GRPH_COLOR_MATRIX_SW to program_color_matrix() instead of
GRAPHICS_CSC_ADJUST_TYPE_SW, this also fixes the following warning when
building the kernel with clang:

drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.c:1129:24:
  error: implicit conversion from enumeration type
  'enum graphics_csc_adjust_type' to different enumeration type
  'enum grph_color_adjust_option' [-Werror,-Wenum-conversion]
    xfm_dce, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW);

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:44 -05:00
Matthias Kaehlcke
81875979f0 drm/amd/display: Remove extra pairs of parentheses in dce_calcs.c
The double parentheses are not needed. Removing them fixes multiple
warnings like this when building with clang:

drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:617:42:
  error: equality comparison with extraneous parentheses
    [-Werror,-Wparentheses-equality]
  if ((data->graphics_micro_tile_mode == bw_def_rotated_micro_tiling)) {

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:43 -05:00
Shaoyun Liu
e966a725c0 drm/amdgpu: Enable ip block bit mask print out info by default
Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Reviewed-by: Christian Konig <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:43 -05:00
Matthias Kaehlcke
7227c91130 drm/amd/powerplay: Remove extra pair of parentheses
The double parentheses are not needed. Removing them fixes the following
warning when building with clang:

drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c:419:29:
  error: equality comparison with extraneous parentheses
    [-Werror,-Wparentheses-equality]
  if ((data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2)) {

Reviewed-by: Guenter Roeck <groeck@chromium.org>
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:42 -05:00
Matthias Kaehlcke
42b5122e82 drm/amd/powerplay: Fix enum mismatch
In several locations the driver uses AMD_CG_STATE_UNGATE (type enum
amd_clockgating_state) instead of AMD_PG_STATE_UNGATE (type enum
amd_powergating_stat) and vice versa. Both constants have the same
value, so this doesn't cause any problems, but we still want to pass
the correct type.

Fixing the mismatch resolves multiple warnings like this when building
with clang:

drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:169:7:
  error: implicit conversion from enumeration type 'enum
  amd_powergating_state' to different enumeration type 'enum
  amd_clockgating_state' [-Werror,-Wenum-conversion]
    AMD_PG_STATE_UNGATE);

Reviewed-by: Guenter Roeck <groeck@chromium.org>
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:41 -05:00
Eric Huang
7e452ce9c9 drm/amdgpu: add mmhub powergating set by smu
PSP will disable legacy mmhub PG setting that is programming
registers, and drive will use SMC message to
set it up.

Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:41 -05:00
Eric Huang
72d7619106 drm/amd/powerplay: add mmhub powergating by smu in powerplay
new generic interface is added in powerplay.

Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:40 -05:00
Eric Huang
b01a4f4897 drm/amd/powerplay: implement set_mmhub_powergating_by_smu for Raven
mmhub PG is enabled by SMU FW only for Raven.

Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:40 -05:00
Eric Huang
913fa7a14d drm/amdgpu: add an interface of amdgpu_dpm_set_mmhub_powergating_by_smu
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:39 -05:00
Dan Carpenter
858bef6e89 drm/amd/powerplay: delete some dead code
We deleted some code in e154162ef7 ("drm/amd/powerplay: refine pp code
for raven") but there were a few related bits that were missed.  Let's
delete them as well.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:38 -05:00
Tom St Denis
fda519fb5d drm/amd/powerplay: Zero out power data in AMDGPU_PP_SENSOR_GPU_POWER readout
Since 12 of the 16 bytes are not initialized with anything let's ensure they're
sensibly zeroed out otherwise debugfs callers will read back garbage
(because they assume debugfs wrote sensible data back...)

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:38 -05:00
Yongqiang Sun
cf8c19a305 drm/amd/display: Add primary tmz_c and meta tmz tmz_c.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:37 -05:00
Charlene Liu
25b3044718 drm/amd/display: enable #PME code path for RV.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:37 -05:00
Tony Cheng
4900a04c14 drm/amd/display: dal 3.1.32
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:36 -05:00
Krunoslav Kovac
8f8372c7d1 drm/amd/display: Optimize regamma calculations
There are several optimizations:
1) Use predefined SRGB, don't calculate. This is the most common case.
2) Precompute HW X points at boot since they're fixed in ColModule
3) Precompute PQ - it never changes and is very CPU intensive in fixed pt.
4) Reduce number of points in ColModule to 512 (32x16) from 1024. This also
requires reducing some regions for legacy DCEs to 16 pts at most.

Performance
1) is super-fast, build_output_tf is 1-2us, down from 25000-30000.
Programming also fast since only one reg write.
2)+3) gives build_output_tf for PQ in ~100us range, down from ~80000-110000
2) + 4) results in slightly over 50% improvement. It gives an idea of the
savings when we can't use SRGB or PQ table (e.g. sdr white level > 80).

There's also a bit of refactoring: renaming some stuff that was misleading
and removing a lot of magic numbers that novices might not be able to
understand where they come from and what they mean.

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:35 -05:00
Charlene Liu
c5fc7f59a7 drm/amd/display: resume from S3 bypass power down HW block.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:35 -05:00
Charlene Liu
5180d4a476 drm/amd/display: add eDP 1.2+ polling for T7
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:34 -05:00
Tony Cheng
60eb6d98ec drm/amd/display: dal 3.1.31
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:34 -05:00
John Barberiz
e14af1dd74 drm/amd/display: Fixed if statement parameters to add a delay on disconnect
Signed-off-by: John Barberiz <jbarberi@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:33 -05:00
Yongqiang Sun
cdb3979808 drm/amd/display: Add return value for detect dp.
System soft hang when hotplug specific 4K DP panel
due to link caps read error and incorrect link setting
parmas to enable dp.
Add status check for DPCD read and add return value
for detect dp, in case of false, return from caller,
avoid further false operation.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:32 -05:00
Roman Li
dc75dd707c drm/amd/display: fix boot-up on vega10
Fixing null-deref on Vega10 due to regression after
'fix cursor related Pstate hang' change.
Added null checks in setting cursor position.

Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:32 -05:00
Nikola Cornij
5f353208c3 drm/amd/display: Remove couple of unused OPTC registers
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:31 -05:00
Eric Yang
5af9d013ef drm/amd/display: turn off cursor when disconnect plane
As a precaution to prevent cases where cursor is enabled on a pipe
that is disabled, always turn off cursor when disconnecting plane.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:31 -05:00
Eric Bernstein
b3a1cbc0c5 drm/amd/display: Expose is_rgb_cspace function in hw_sequencer
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:30 -05:00
Ken Chalmers
a6e59fa806 drm/amd/display: WBSCL filter init calculation fixes
* Previous code did some calculations with a mix of normal integers and
  integers aligned as U2.24 fixed-point values.
* There were bugs in the conversion of the final result into the
  S4.19 values required for the registers.

Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:29 -05:00
Eric Yang
f774b33982 drm/amd/display: remove unused function prototypes
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:29 -05:00
Eric Yang
33fd17d912 drm/amd/display: fix cursor related Pstate hang
Move cursor programming to inside the OTG_MASTER_UPDATE_LOCK

If graphics plane go from 1 pipe to hsplit, the cursor updates
after mpc programming and unlock. Which means there is a window
of time where cursor is enabled on the wrong pipe if it's on
the right side of the screen (i.e. case where cursor need to
move from pipe 0 to pipe 3 post split). This will cause pstate hang.

Solution is to program the cursor while still locked.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:28 -05:00
Mikita Lipski
a83ccf7cad drm/amd/display: Set irq state only on existing crtcs
Because AMDGPU_CRTC_IRQ_VLINE1 = 6, it expected 6 more crtcs to be
programed with disabled irq state in amdgpu_irq_disable_all. That caused errors and accessed
the wrong memory location.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:28 -05:00
Yongqiang Sun
f9549850a4 drm/amd/display: Null check for gamma correction.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:27 -05:00
Yongqiang Sun
24a30505f3 drm/amd/display: Check hubp in pipe_ctx not in res_pool.
When disable plane, check power gate flag in hubp with pipe_ctx,
not with res_pool.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:27 -05:00
Christian König
29e8357b4c drm/amdgpu: sync the VM PD/PT before clearing it
Otherwise we might overwrite stuff which is still in use.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:26 -05:00
Tony Cheng
c8ce5da527 drm/amd/display: dal 3.1.30
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:25 -05:00
John Barberiz
3e5df76ae5 drm/amd/display: Bypass gamma set if not standard type
If non-standard gamma type detected set identity matrix flag
so that we can bypass the gamma mode.

Signed-off-by: John Barberiz <jbarberi@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:25 -05:00
Charlene Liu
69b9723a81 drm/amd/display: wait for T9 after backlight off mainlink blank.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:24 -05:00
Leo (Sunpeng) Li
fdb401d03d drm/amd/display: Fix multiple definitions of handle_crc_irq
If CONFIG_DEBUG_FS is disabled, then CRC should also be disabled.
Therefore, amdgpu_dm_crtc_handle_crc_irq was redefined as a no-op
function within amdgpu_dm.h.

However, since amdgpu_dm.h is included in multiple files, this caused
conflicts when linking during compile. Therefore, Use a macro to
define the function as a no-op instead.

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:24 -05:00
Jerry (Fangzhi) Zuo
f783577c85 drm/amd/display: Fixed non-native modes not lighting up
There is no need to call drm_mode_set_crtcinfo() again once
crtc timing is decided. Otherwise non-native/unsupported timing
might get overwritten.

Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:23 -05:00
Martin Tsai
ac916c914c drm/amd/display: Remove return when no EDID read.
Signed-off-by: Martin Tsai <martin.tsai@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:22 -05:00
Charlene Liu
c3b1c061f4 drm/amd/display: BL setting save/restore
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:22 -05:00
Harry Wentland
d89746ec4f drm/amd/display: Adding missing TMZ sh/mask entries for DCN1 SURFACE_CONTROL
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <tony.cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:21 -05:00
Christian König
e61736daa9 drm/amdgpu: clear the shadow fence as well
It also needs to be initialized.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:20 -05:00
Christian König
e5197a4c3d drm/amdgpu: release the VM shadow in the error path as well
Without it we run into a memory leak.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:20 -05:00
Alex Deucher
a3405d0c71 drm/amdgpu: remove unused display_vblank_wait interface
No longer used since we changed the MC programming sequence.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:19 -05:00
Alex Deucher
e5e0e86717 drm/amdgpu/dce: fix mask in dce_v*_0_is_in_vblank
Using the wrong mask.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Noticed-by: Hans de Ruiter <hans@keasigmadelta.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:19 -05:00
Arnd Bergmann
ac5d44fbf3 drm/amd/display: fix incompatible structure layouts
Building the amd display driver with link-time optimizations revealed a bug
that caused dal_cmd_tbl_helper_dce80_get_table() and
dal_cmd_tbl_helper_dce110_get_table() get called with an incompatible
return type between the two callers in command_table_helper.c and
command_table_helper2.c:

drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce80/command_table_helper_dce80.h:31: error: type of 'dal_cmd_tbl_helper_dce80_get_table' does not match original declaration [-Werror=lto-type-mismatch]
 const struct command_table_helper *dal_cmd_tbl_helper_dce80_get_table(void);

drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce80/command_table_helper_dce80.c:351: note: 'dal_cmd_tbl_helper_dce80_get_table' was previously declared here
 const struct command_table_helper *dal_cmd_tbl_helper_dce80_get_table(void)

drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce110/command_table_helper_dce110.h:32: error: type of 'dal_cmd_tbl_helper_dce110_get_table' does not match original declaration [-Werror=lto-type-mismatch]
 const struct command_table_helper *dal_cmd_tbl_helper_dce110_get_table(void);

drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce110/command_table_helper_dce110.c:361: note: 'dal_cmd_tbl_helper_dce110_get_table' was previously declared here
 const struct command_table_helper *dal_cmd_tbl_helper_dce110_get_table(void)

The two versions of the structure are obviously derived from the same
one, but have diverged over time, before they got added to the kernel.

This moves the structure to a new shared header file and uses the superset
of the members, to ensure the interfaces are all compatible.

Fixes: ae79c310b1 ("drm/amd/display: Add DCE12 bios parser support")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:18 -05:00
Christian König
3af81440a9 drm/amdgpu: cache the fence to wait for a VMID
Beneficial when a lot of processes are waiting for VMIDs.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:18 -05:00
Christian König
58592a095c drm/amdgpu: restructure amdgpu_vmid_grab
Now that we have the different cases for grabbing a VMID in separate
functions, restructure the top level function to only have one place
where VMIDs are assigned to jobs.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:17 -05:00
Christian König
25ddf75bb3 drm/amdgpu: move reusing VMIDs into separate function
Let's try this once more.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:16 -05:00
Christian König
cb5372ace9 drm/amdgpu: cleanup and simplify amdgpu_vmid_grab_reserved
Drop the "_locked" from the name, cleanup and simplify the logic a bit.
Add missing comments.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:16 -05:00
Christian König
782dcfdfd9 drm/amdgpu: stop checking GPU reset counter during VMID grab
We do this later on when we flush the VMID anyway.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:15 -05:00
Christian König
102374488d drm/amdgpu: make VMID owner none atomic v2
The variable is protected by the VMID mutex anyway.

v2: grab the mutex while resetting the VMID as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:15 -05:00
Christian König
3a80e92b6e drm/amdgpu: split finding idle VMID into separate function
No functional change, but makes it easier to maintain the code.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:14 -05:00
Christian König
8fe27f8fa0 drm/amdgpu: make VMID assignment more fair v2
Similar to finding an idle one before reuse.

This guarantees fairness between processes. Otherwise process with a reserved
VMID have an unfair advantage while scheduling jobs.

v2: improve commit message

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:13 -05:00
Bas Nieuwenhuizen
a20ee0b1f8 drm/amdgpu: Fix always_valid bos multiple LRU insertions.
If these bos are evicted and are in the validated list
things blow up, so do not put them in there. Notably,
that tries to add the bo to the LRU twice, which results
in a BUG_ON in ttm_bo.c.

While for the bo_list an alternative would be to not allow
always valid bos in there, that does not work for the user
fence.

v2: Fixed whitespace issue pointed out by checkpatch.pl

Signed-off-by: Bas Nieuwenhuizen <basni@chromium.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-02-19 14:19:13 -05:00
Andrey Grodzovsky
062d2e6af7 Revert "drm/amdgpu/gfx8: Fix compute ring failure after resetting"
This reverts commit 75737cb4eb.

Fixes compute rings test failure on bare metal during full GPU reset.

RCA:
the ring buffer has to be filled with valid packets (such as NOPs) first
before submitting MAP_QUEUEs packet into KIQ. Once a compute engine is mapped,
it will immediately execute the ring buffer if the RTPR is not equal to the
WTPR from the MQD. It could lead to engine hang if the ring buffer filled
with random data.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:12 -05:00
Christian König
f732b6b3c0 drm/amdgpu: move waiting for VM flush into gmc_v9_0_emit_flush_gpu_tlb
Keep that at a common place instead of spread over all engines.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:12 -05:00
Christian König
2b124b0b70 drm/amdgpu: implement vcn_v1_0_(dec|enc)_ring_emit_reg_wait v2
Add emit_reg_wait implementation for VCN v1.

v2: cleanup the existing code as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:11 -05:00
Christian König
d949315a66 drm/amdgpu: implement vce_v4_0_emit_reg_wait v2
Add emit_reg_wait implementation for VCE v4.

v2: call new function directly from existing code

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:10 -05:00
Christian König
38d32a7564 drm/amdgpu: implement uvd_v7_0_(enc_|)ring_emit_reg_wait v2
Add emit_reg_wait implementation for UVD v7.

v2: call new function directly from the existing code

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:10 -05:00
Christian König
5ad68ee4ca drm/amdgpu: implement sdma_v4_0_ring_emit_reg_wait
Add emit_reg_wait implementation for SDMA v4.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:09 -05:00
Christian König
230fcc34a8 drm/amdgpu: implement gfx_v9_0_ring_emit_reg_wait
Implement emit_reg_wait for gfx v9.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:09 -05:00
Christian König
c1e877da57 drm/amdgpu: add new emit_reg_wait callback
Allows us to wait for a register value/mask on a ring.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:08 -05:00
Christian König
491355937a drm/amdgpu: fix DW estimation on VI
Forgot to update that during recent changes.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:08 -05:00
Rex Zhu
61e208b16e drm/amd/pp: Fix sysfs pp_dpm_pcie bug on CI/VI
when echo "01">pp_dpm_pcie
the pcie dpm will fix in highest link speed.
But user should expect auto speed between
level 0 and level1

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:07 -05:00
Rex Zhu
337ecd6a98 drm/amd/pp: Enable pp_set_power_profile_mode under manual mode
Only user enter manual performance mode, driver allow user
configure the sclk/mclk dpm parameters through sysfs
pp_power_profile_mode.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:06 -05:00
Rex Zhu
948fd66c94 drm/amd/pp: Refine pp_dpm_force_clock_level functions
Only when user set manual performance mode, driver
enable pp_dpm_force_clock_level.
so check the mode in pp_dpm_force_clock_level,
and delete the same logic in callback functions.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:06 -05:00
Rex Zhu
6fa3ef3a9c drm/amd/pp: Delete debug info when set power_profile_mode
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:05 -05:00
Christian König
6b034e25c8 drm/amdgpu: limit the VM address space with older VCE FW versions
Older VCE FW versions are buggy and can't work with 48bit address
spaces.

RFC: Should we limit the address space or just reject loading the older
VCE firmware?

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:05 -05:00
Luis de Bethencourt
e2751493fc drm: Fix trailing semicolon
The trailing semicolon is an empty statement that does no operation.
Removing it since it doesn't do anything.

Signed-off-by: Luis de Bethencourt <luisbg@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:04 -05:00
Luis de Bethencourt
122fe39da4 drm: amd: Fix trailing semicolons
The trailing semicolon is an empty statement that does no operation.
Removing the two instances of them since they don't do anything.

Signed-off-by: Luis de Bethencourt <luisbg@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:03 -05:00
Alex Deucher
3fa203af4b drm/amdgpu: set DRIVER_ATOMIC flag early
The atomic debugfs stuff gets created in drm_dev_alloc()
but this gets called before we've enumerated all of our
IPs, so move the DRIVER_ATOMIC flag setting to fix that.

Since DRIVER_ATOMIC is a driver flag it's currently global
to the driver so setting it affects all GPUs driven by the
driver.  Unfortunately, not all GPUs support atomic.  Warn
the user if that is the case.

This is the same as our current behavior, but at least the
atomic debugfs stuff gets created now.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:03 -05:00
Alex Deucher
367e66870e drm/amdgpu: remove DC special casing for KB/ML
It seems to be working now.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=102372
Reviewed-by: Mike Lothian <mike@fireburn.co.uk>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:02 -05:00
Tom St Denis
7ca34ddc78 drm/ttm: Simplify ttm_dma_page_put()
Remove redundant store of return code.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:02 -05:00
Tom St Denis
42bdbb6e0f drm/ttm: Fix coding style in ttm_dma_pool_alloc_new_pages()
Add missing {} braces.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:01 -05:00
Tom St Denis
ddde985c41 drm/ttm: Fix coding style in ttm_tt_swapout()
Add missing {} braces.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:01 -05:00
Tom St Denis
07d48da4f4 drm/ttm: Simplify ttm_eu_reserve_buffers()
Hoist the comparison of the ret to -EDEADLK above
the two code paths to simplify the function.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:19:00 -05:00
Tom St Denis
de8dfb8e34 drm/ttm: Remove unncessary retval from ttm_bo_vm_fault()
The dual ret/retval was more complex than need be.  Now
we drop the retval variable and assign the appropriate VM
codes to ret instead.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:59 -05:00
Tom St Denis
449f797a94 drm/ttm: Fix coding style in ttm_bo_move_memcpy()
Add missing {} braces.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:59 -05:00
Tom St Denis
add3d95d73 drm/ttm: Simplify ttm_dma_find_pool() (v2)
Flip the logic of the comparison and remove
the redudant variable for the pool address.

(v2): Remove {} bracing.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:58 -05:00
Tom St Denis
c68edaa0c1 drm/ttm: Fix coding style in ttm_pool_store()
Correct missing {} style.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:58 -05:00
Tom St Denis
5b4262d7a2 drm/ttm: Change ttm_tt page allocations to return errors
Explicitly return errors in ttm_tt_alloc_page_directory() and
ttm_dma_tt_alloc_page_directory() instead of relying on
further logic to detect errors.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:57 -05:00
Tom St Denis
420457acfb drm/ttm: Add a default BO destructor to simplify code (v2)
(v2): Remove stray ; noticed by Felix

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:56 -05:00
Tom St Denis
43c7c41b25 drm/ttm: Fix coding style in ttm_bo.c
Correct indentation and {} brace style.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:56 -05:00
Christian König
4584312d38 drm/amdgpu: fill only the lower range with ATS entries v2
At least on x86-64 the upper range is purely used by the kernel,
avoid creating any ATS mappings there as security precaution and to
allow proper page fault reporting in the upper range.

v2: remove unused variable

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:55 -05:00
Christian König
44e1baeb63 drm/amdgpu: revert "Add support for filling a buffer with 64 bit value"
This reverts commit 7bdc53f925 and commit
330df03b3a.

Neither are needed any more.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:55 -05:00
Christian König
8febe617d8 drm/amdgpu: revert "Add a parameter to amdgpu_bo_create()"
This reverts commit 2046d46db9.

Not needed any more.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:54 -05:00
Christian König
4c77edbf74 drm/amdgpu: drop root shadow sync
Completely pointless, it is the same reservation object as the root PD
anyway.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Roger He <Hongbo.He@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:54 -05:00
Christian König
13307f7e1d drm/amdgpu: revert "drm/amdgpu: use AMDGPU_GEM_CREATE_VRAM_CLEARED for VM PD/PTs" v2
Using the standard clear turned out to be to inflexible.

First of all it is executed on the system queue, together with buffer
moves instead on the per VM queue.

And second we need to fill in the page tables with more than just zero.

We keep the new functionality of initializing the PDEs/PTEs with ATC
routing entries intact.

v2: update commit message.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:53 -05:00
Christian König
4383736340 drm/amdgpu: fix vcn_v1_0_dec_ring_emit_wreg
That got mixed up with the encode ring function.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:52 -05:00
Alex Deucher
0d35bc78ec drm/amdgpu/pm: rework the hwmon visibility settings
Previously we just always exposed everything for asics
supported by powerplay.  Make it a bit more fine grained.
In practice this shouldn't change anything.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:52 -05:00
Alex Deucher
21a381f79e drm/amdgpu/pp: remove the get_temperature API
This is also supported with the read_sensor API and there
were no more users of the get_temperature API.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:51 -05:00
Alex Deucher
71c9b9adad drm/amdgpu/pm: use read_sensor API to get temperature
Rather than using the amdgpu_dpm_get_temperature.  Both
provide access to the temperature.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:51 -05:00
Alex Deucher
2976fc2622 drm/amdgpu/pm: report gpu average power via hwmon API
Expose power via hwmon.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:50 -05:00
Alex Deucher
2bd376bf8f drm/amdgpu/pm: report gpu voltages via hwmon API
Expose vddgfx and vddnb via hwmon.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:49 -05:00
Alex Deucher
5ec36e2d70 drm/amdgpu/pm: handle fan properly when card is powered down
Return an error if the user tried to check or set the fan
parameters while the card is powered down (e.g., on a PX/HG
system for example).  This makes the fan consistent with the
temperature stuff.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:49 -05:00
Christian König
6f05c4e9d1 drm/amdgpu: move static CSA address to top of address space v2
Move the CSA area to the top of the VA space to avoid clashing with
HMM/ATC in the lower range on GFX9.

v2: wrong sign noticed by Roger, rebase on CSA_VADDR cleanup, handle VA
hole on GFX9 as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:48 -05:00
Rex Zhu
c1f2fb6b63 drm/amd/pp: Delete unnecessary function argument
in populate_single_graphic_level for smu7

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:48 -05:00
Rex Zhu
c7429b3ae9 drm/amd/pp: Add struct profile_mode_setting for smu7
Move configurable profiling parameters to struct
profile_mode_setting and initialize current_profile_setting.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:47 -05:00
Rex Zhu
527d9427fa drm/amd/pp: Delete dead code in powerplay
As not support per DPM level optimization,
so delete activity_target array.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:47 -05:00
Rex Zhu
ce91b71c9a drm/amd/pp: Change activity_target for performance optimization on Polaris
And not support perDPM level optimization on Polaris, so
delete sclk activity_target array.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:46 -05:00
Andrey Grodzovsky
ef4bccbdbf drm/amd/display: Remove timer handler.
Dead code, looks obsolete.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:45 -05:00
Andrey Grodzovsky
d45d97b243 drm/amd/display: Remove unsued mutex and spinlock.
They seem to be obsolete.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:45 -05:00
Harry Wentland
f3b72c7b00 drm/amd/display: Fix warning about misaligned code
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:44 -05:00
John Barberiz
cf5620562f drm/amd/display: Add temporary delay on disconnect patch
- Sequencing bug of not resetting delay on disconnect to default values

Signed-off-by: John Barberiz <jbarberi@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:44 -05:00
Mikita Lipski
6c1d03a4f2 drm/amd/display: Remove unnecessary register programming
Remove aux engine register programming,when freeing the engine
as it was a temporary workaround.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:43 -05:00
John Barberiz
243c46c5ce drm/amd/display: Add temporary delay on disconnect patch
Signed-off-by: John Barberiz <jbarberi@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:42 -05:00
Leo (Sunpeng) Li
9557080196 drm/amd/display: Fix unused variable compilation error
Fix:

drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dce110/dce110_hw_sequencer.c:
In function ‘dce110_blank_stream’:
drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dce110/dce110_hw_sequencer.c:1008:31:
error: unused variable ‘params’ [-Werror=unused-variable]
  struct encoder_unblank_param params = { { 0 } };

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:42 -05:00
Charlene Liu
41b497421a drm/amd/display: eDP sequence BL off first then DP blank.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:41 -05:00
Geling Li
cf5e4a67f4 drm/amd/display: Add debug flag for p010_mpo_support
Signed-off-by: Geling Li <geling.li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:41 -05:00
Krunoslav Kovac
a771c1f289 drm/amd/display: Force full update on pixel_format_change
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:40 -05:00
Tony Cheng
352ab654ea drm/amd/display: dal 3.1.29
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:40 -05:00
Charlene Liu
7c357e61e2 drm/amd/display: dpms off mute az audio endpoint only.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:39 -05:00
Dmytro Laktyushkin
c7d76452d2 drm/amd/display: revert to hacking bounding box for pipe split
Directly editing pipe config outside of formula is error prone
and results in higher clocks being used when splitting.
For this reason we reverted to using bounding box hacking
to split. Since sometimes this erroneusly results in higher dpm
being required we unhack the bounding box and recalculate to allow
dpm0 is possible.
Side effect is we will lose some stutter efficiency
in non dpm0 cases. This is not a big concern since increased stutter
efficiency saves an order of magnitude less power than lower dpm.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:38 -05:00
Charlene Liu
701ed303b2 drm/amd/display: disable az_clock_gating for endpoint register access only
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:38 -05:00
Arun Pandey
af1b00cdc6 drm/amd/display: Define dpp1_set_cursor_position in header
Signed-off-by: Arun Pandey <Arun.Pandey@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:37 -05:00
Charlene Liu
cf1835f03f drm/amd/display: fix backlight not off at resume from S4
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:37 -05:00
Yongqiang Sun
3be1406a72 drm/amd/display: Add timing generator count to resource pool.
Use tg count in resource pool for further reference.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:36 -05:00
SivapiriyanKumarasamy
05133ac856 drm/amd/display: Synchronize update plane addr for freesync
Lock top_pipe when doing update plane addr for split pipe freesync case

Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:36 -05:00
Harry Wentland
9182b4cb44 drm/amd/display: Call update_stream_signal directly from amdgpu_dm
There's no good place in DC to cover all place where stream signal should
be updated. update_stream_signal depends on timing which comes from DM.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:35 -05:00
Leo (Sunpeng) Li
d1bd7d61bc drm/amd/display: Early return on crc get
If crc is disabled, early return when getting crc's. That way, we avoid
reading extra registers within the pflip high irq.

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:34 -05:00
Yongqiang Sun
ff1374c94b drm/amd/display: Move output_tf to stream_state/update
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:34 -05:00
Ken Chalmers
b339743b89 drm/amd/display: Remove unused param in DML
Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:33 -05:00
Duke Du
3aa0caddf6 drm/amd/display: Update the register GRPH_SWAP_CNTL if surface pixel format changed.
Signed-off-by: Duke Du <Duke.Du@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:33 -05:00
Harry Wentland
a27267e01f drm/amd/display: dc: Remove unused display_mode_vba.c
We're currently not using this.

v2: More files and includes to remove.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:32 -05:00
Alex Deucher
f75a9a5d6c drm/amdgpu/soc15: don't abuse IP soft reset for adapter reset
The IP soft reset interface is for per IP reset but it was
being abused for adapter reset on soc15 asics.  Adjust the
interface to make it explicit.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:31 -05:00
Alex Deucher
e7f9ccb437 drm/amdgpu/psp: use a function pointer structure
This way we can make all of the IP specific functions static,
and we only need a single entry point into the PSP IP modules.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:31 -05:00
Christian König
97745f6852 drm/amdgpu: consistently use AMDGPU_CSA_VADDR
Instead of repeating this multiple times.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:30 -05:00
Christian König
a3e9a15a25 drm/amdgpu: apply top reserved VA space to pre Vega10 as well
Reserve VA space at the top for older generations as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:30 -05:00
Christian König
18d09e63e0 drm/amdgpu: reduce reserved VA size
1MB should be more than enough, currently we use about 8K.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:29 -05:00
Samuel Li
734dd01d56 drm/amdgpu: rename amdgpu_crtc_idx_to_irq_type
Add display to the name for consistency.

Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:29 -05:00
Samuel Li
aa8e286a8a drm/amdgpu: rename amdgpu_get_crtc_scanoutpos
Add display to the name for consistency.

Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:28 -05:00
Samuel Li
0c16443a1b drm/amdgpu: rename amdgpu_crtc_scaling_mode_fixup
Add display to the name for consistency.

Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:27 -05:00
Samuel Li
166140fb24 drm/amdgpu: rename amdgpu_update_display_priority
Rename as amdgpu_display_update_priority for consistency.

Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:27 -05:00
Samuel Li
3dc9b1ce80 drm/amdgpu: rename amdgpu_modeset_create_props
Add display to the name for consistency.

Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:26 -05:00
Samuel Li
4d4772f6ab drm/amdgpu: rename amdgpu_user_framebuffer_create
Add display to the name for consistency.

Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:26 -05:00
Samuel Li
9da3f2d934 drm/amdgpu: rename amdgpu_framebuffer_init
Add display to the name for consistency.

Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:25 -05:00
Samuel Li
e0b5b5ec0b drm/amdgpu: rename amdgpu_ddc_probe
Add display to the name for consistency.

Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:24 -05:00
Samuel Li
50af9193b3 drm/amdgpu: rename amdgpu_print_display_setup
Add display to the name for consistency.

Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:24 -05:00
Samuel Li
775a836425 drm/amdgpu: rename amdgpu_crtc_set_config
Add display to the name for consistency.

Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:23 -05:00
Samuel Li
0cd1193236 drm/amdgpu: rename amdgpu_crtc_page_flip_target
Add display to the name for consistency.

Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:23 -05:00
Samuel Li
3a05dc000a drm/amdgpu: rename static functions in amdgpu_display.c
Add display to the name for consistency.

Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:22 -05:00
Christian König
2ee150cda7 drm/amdgpu: remove now superflous *_hdp operation
All HDP invalidation and most flush can now be replaced by the generic
ASIC function.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:22 -05:00
Christian König
1b9d17db1c drm/amdgpu: fallback to generic HDP operation
When ring special operations aren't available we can fallback to the
generic ASIC operations.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:21 -05:00
Christian König
698825653f drm/amdgpu: add optional ring to *_hdp callbacks
This adds an optional ring to the invalidate_hdp and flush_hdp
callbacks. If the ring isn't specified or the emit_wreg function not
available the HDP operation will be done with the CPU otherwise by
writing on the ring.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:20 -05:00
Rex Zhu
3c9d1fde7f drm/amd/pp: Add update_avfs call when set_power_state
when Overdrive voltage, need to disable AVFS.
when OverDriv engine clock, need to recalculate
AVFS voltage by disable/enable avfs feature.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:20 -05:00
Rex Zhu
49fd66e5d5 drm/amd/pp: Update smu7 dpm table with OD clock/voltage
Delete old OD type code path when populate clk.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:19 -05:00
Rex Zhu
5e4d4fbea5 drm/amd/pp: Implement edit_dpm_table on smu7
v2: - check clk against OverDrive limits from VBIOS
    - set OD flag when user commit the setting.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19 14:18:19 -05:00